IEEE
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`8. The articles below have been attached as Exhibits A — B to this declaration:
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`
`A. Madjar,et al., “A novel DDS based 94 GHzhighlinearity FMCW RW
`front end” 26" European Microwave Conference, 1996 (Volume:1),
`
`September9-12, 1996.
`Z. Galani and R.A. Campbell, “An overview of frequency synthesizers for
`radars” IEEE Transactions on Microwave Theory and Techniques Vol. 39,
`Issue 5, May 1991.
`
`
`9.
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`I obtained copies of Exhibits A — B through IEEE Xplore, where they are maintained
`in the ordinary course of IEEE’s business. Exhibits A - B are true and correct copies
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`11. A. Madjar,et al., “A novel DDS based 94 GHz highlinearity FMCW RWfront end”
`waspublished as part of the 26"" European Microwave Conference, 1996 (Volume:
`1). The 26"" European Microwave Conference, 1996 (Volume: 1) was held from
`September 9-12, 1996. Attendees of the conference were provided copiesof the
`publication no later than the last day of the conference. The article is currently
`available for public download from the IEEE digital library, IEEE Xplore.
`
`12. Z. Galani and R.A. Campbell, “An overview of frequency synthesizers for radars”
`was published as part of IEEE Transactions on Microwave Theory and Techniques
`Vol. 39, Issue 5. IEEE Transactions on Microwave Theory and Techniques Vol. 39,
`Issue 5 was published in May 1991. Copies of this publication were madeavailable
`no later than the last day of the stated publication month. Thearticle is currently
`available for public download from the IEEE digital library, IEEE Xplore.
`
`13. I hereby declare that all statements made herein of my own knowledgeare true and
`that all statements made on information and belief are believed to be true, and further
`that these statements were made with the knowledgethat willful false statements and
`the like are punishable by fine or imprisonment, or both, under 18 U.S.C. § 1001.
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`I declare under penalty of perjury that the foregoing statementsare true and correct.
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`EXHIBIT A
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`PACT - BM204286003
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`26th EuMC * 9-12 September 1996 * Hotel Hilton Atrium « Prague * Czech Republic
`
`A novel DDSbased 94 GHz high
`linearity FMCW RF front end
`
`Asher Madjar, Zvi Nativ, Danny Adar
`and Saul Zoref.
`
`different approach. In this paper we demonstrate the
`realization of a very linear FM chirp at 94 GHz by using a
`DDSand an optimal combination of up-conversion and
`frequency multiplication. To our knowledge,this is the frst
`sourceofthis type at this frequency with excellentlinearity,
`potentially low cost and smallsize.
`
`RAFAEL,Haifa, Israel. P.O. Box 2250
`(code 87), Haifa, Israel.
`
`Tel. +972-4-8794128
`fax +972-4-8792037
`E-mail: asher@ee.technion.ac.il
`
`’
`
`Block Diagram
`Theprinciple of operation of a Direct Digital Synthesizer
`is well known and has been described in numerous papers
`andtutorials(i.e. [1]). Basically, the DDS consists of a clock
`controlled phase accumulator (counter) that simulates the
`instantaneousphase,a lookuptable containing a sine wave
`(converting phase mto amplitude), a DAC (digital to analog
`converter) andafilter. The waveform is generateddigitally
`Abstract
`with an almost absolute accuracy (frequency accuracy
`depends onthe clock, whichis crystal controlled). A linear
`FMCWmillimeter wave sensorsare very useful for both
`chirp can be generated easily by linearly stepping the
`military and civilian applications, due to their low cost,
`frequencyat the digital frequency controlport, as explained
`simplicity and low transmitted power. In this paper we
`in [2]. Present day DDS can operate using clock in excess
`present a novel approachtotherealization of linear FMCW
`of 1 GHz. as described in [3]. Thus DDS can be used to
`chirp at a frequency of 94 GHz based on a DDS(Direct
`generate signals in the VHF and UHFranges.
`Digital Synthesizer). This is a much superior method
`A block diagram of the novel RF front end is depicted in
`compared to the common approach using a VCO with a
`Fig. 1. The subsystem containsthe following blocks: a DDS
`linearization loop, the linearity of which is limited. Our
`unit with its linear chirp controlcircuit, an Lband assembly,
`approach enables realization of a relatively low cost, small
`an S band DRO, a Ku band assembly, a W band assembly
`size sensor with an extremely good linearity. We
`andthe receiver assembly. The DDSis a Sciteq ADS-43 1-
`demonstrated an excellent range resolution of better than
`000 unit, which can be clocked up to a frequency of 1600
`0.5 meter at a range of 1 kilometer.
`MHz. The DDScontrol circuit is a digital circuit which
`generates a stream of binary frequency control words
`representing a linear sawtooth, which makes the DDS sweep
`over a bandwidth of 80 MHz. This unit was developed by
`us using standard digital components. The DDSis clocked
`by a signal at around 900 MHz,whichis supplied by the L
`band assembly.
`
`Introduction
`In recent years millimeter wave sensors have becomevery
`useful for both military and commercial applications
`(seekers, collision avoidance, traffic control, etc.). Many
`applications already exist and many more are emerging
`shortly. The FMCW sensor is becoming more and more
`popular due to its low cost, low power and simplicity
`The Components
`compared to other types (i. e. pulsed radar). In FMCW
`The DROis a low noise dielectric resonator oscillator
`sensors a linear FM chirp is generated and transmitted
`toward a target. A sample of the transmitted signal is used
`Operating at S-band. The DRO drives the L band assembly
`as the LO for the receiver mixer. The signal reflected from
`and serves as the system reference. The L band assemblyis
`the target is received and routed to the mixer, where it mixes
`used to up-convert the DDSoutputsignal to L-band. The
`with the transmitted signal. Due to the delay between the
`DROsignal is used for three purposes: LO for the Ku unit
`transmitted and received signals there is a frequency
`(via the L bandunit), LO for the L- band mixer and a clock
`for the DDS.The last two tasks are achieved by a frequency
`difference. Thus, the IF frequency is proportional to the
`divider in the L band unit. The DDSsignal output in the
`target range.
`The implementation of an FMCWsensorisrelatively
`VHFbandis upconverted by a mixer to L band.
`simple, except for the linear FM chirp generator. The
`The Ku unit contains two components: a x4 subharmonic
`mixer, using the DRO as the LO, and a power amplifier.
`linearity of the chirpis the single most important parameter
`of the FMCWsensor, which determinesthe range resolution.
`The mixer converts the L band signal to Ku band, and
`exhibits a 10db conversion loss. The amplifier amplifies
`Any nonlinearity in the frequencyvs. time curve causes the
`IF frequency to fluctuate, and thus causes uncertainty in
`the chirped signal up to a level of around 2 watt. The W
`band unit is basically a x6 frequency multiplier, which
`the range measurement. For many applications moderate
`linearity is sufficient (~0.5%), and the chirp can be realized
`converts the signal
`into 94 GHz. This frequency
`
`by a MMwave VCOandalinearization loop with a linear multiplication is the only one in our system. We have
`sawtooth voltage ramp as the reference.
`avoided excessive frequency multiplication to prevent the
`In many applications very high linearity is needed to
`increase of spurious signals and noise (20log(n) rule) - most
`ensure good range resolution even at large distances (1
`of the frequency upconversion is performed by frequency
`kilometer and above). In these cases it is necessary to use a
`translation using a mixer. The receiver unit contains a
`
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`26th EuMC ¢ 9-12 September 1996 » Hotel Hilton Atrium * Prague * Czech Republic
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`circulator to separate betweenthe transmitted and received
`signals, a coupler to sample the transmitted signal for mixer
`LO, a mixer and an IF filter/amplifier. The power is
`transmitted via a reflector antenna, and the IF signal is
`processed by an FFT processor,which displays the spectrum
`of the received down converted signal. The IF frequencyis
`proportionalto the target range andis in the MHz band.
`
`Performance
`An experimental system was built for performance
`evaluation by using available components and without
`consideration to physical size. A photographofthis system
`is depicted in Fig. 2, which showsalso the reflector antenna
`used in the experiment. The level of transmitted powerat
`94 GHz is +12.5dbm. The LO powerat 94 GHz reaching
`the receive mixer is +4.5dbm. This powerlevel is low, and
`a “normal” mixer would have large conversion loss; thus
`we have used a mixer with bias, which was developed by
`us specifically for this system. The mixer exhibits a
`conversion loss of 8db at that LO powerlevel.
`We have experimented with the above system and were
`able to detect targets up to 1 km away.Therange resolution
`waslimited by the IF FFT processor (512 sampling points),
`which wasavailable for the experiment, to around 0.5 meter.
`
`This is not an inherentlimitation of the system, and can be
`improved by using a better FFT processor. We were able to
`distinguish between 2 target separated by 0.5 m at a range
`of 1 km, as depicted in Fig. 3. The DDS generated chirp
`has an absolute linearity, however, dispersion of the
`upconversion chain may degrade thelinearity. Experiment
`showsthat in our system dispersion effects are negligible,
`and the superb linearity was fully exploited.
`Presently we are designing the engineering prototype of
`the above system. Ourestimate is that the production cost
`of the umit in quantities of 1000 is around $3500, and the
`volumeofthe unit is around 500 cm?.
`
`References
`[1] Henry Eisenson, “Frequency Synthesis Using DDS/
`NCO Technology-a Tutorial”, Electro International
`Conference, April 16-18, 1991, Javits Convention Center,
`New York, NY.
`[2] Bar-Giora Goldberg,“Linear Frequency Modulation
`- Theory and Practice”, RF Design, September 1993, pp.
`39-46.
`Jack Browne, “Hybrid Circuit Sets DDS Clock
`[3]
`Beyond 1 GHz”, Microwaves and RF, February 1990, pp.
`128-130.
`
`
`
` DDS
`
`KU -BAND UNIT
`
`ONTROLG
`
`
`
`
`RECEIVER
`
`
`
` FFT
`BPROCESSOR J
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`Fig. 1 Block Diagram of the novel RF Front-end
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`26th EuMC ¢ 9-12 September 1996 * Hotel Hilton Atrium * Prague * Czech Republic
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`
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`Fig. 2 A photograph of the experimental setup
`
`|
`
`Fig. 3 An FFTplot
`
`two targets 50 cm apart at a ran
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`ge of 1 km
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`EXHIBIT B
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`782
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`IFFE TRANSACTIONS ON MICROWAVE THEORYAND ‘TECHNIQUES, VOL. 39, NO. 5, MAY1991
`
`An Overview of Frequency Synthesizers
`for Radars
`
`Zvi Galani, SeniorMember, IEEE, and Richard A. Campbell
`
`Abstract —This paper presents an overview of frequency syn-
`thesizer techniques suitable for radar systems. Included are the
`requirements which have a direct impact on the selection of
`synthesizer architectures and the choice of synthesizer compo-
`nents. Both direct and indirect architectures are presented,
`along with advantages, disadvantages, and representative exam-
`ples. A brief discussion of analytical procedures is followed by a
`survey of key synthesizer components and future trends.
`
`I.
`
`INTRODUCTION
`
`HE use of frequency synthesizers in test equipment,
`radar, and communication systems has been growing
`steadily because of their many advantages, especially fre-
`quency selection with digital commands and predictable
`frequency stability. Although all synthesizers share com-
`monfeatures, they also exhibit significant differences as a
`result of specific system requirements and/or specific
`applications.
`Radar synthesizers often have more stringent noise and
`spurious signal requirements than the other types, primar-
`ily because they arc used as the timing reference between
`the transmitted and the received signals of the radar.
`This paper presents various synthesizer architectures
`and key synthesizer components, along with a discussion
`of advantages and disadvantages. Some architectures are
`hardwareintensive and, because of their physical size, are
`more suitable for stationary or shipboard radars. Archi-
`tectures requiring smaller volume are more suitable for
`airborne applications.
`Direct, phase-locked, and frequency-locked architec-
`tures are covered, including key building blocks and per-
`formance limitations. The direct digital synthesizer (DDS)
`architecture is considered briefly, as it
`is not yet widely
`used in radar systems. Finally, projections are made of
`advances in components that have a direct effect on
`frequency synthesis.
`
`Il. REQUIREMENTS
`
`The electrical requirements of a frequency synthesizer
`are derived from the radar system performance require-
`ments, just as its mechanical requirementsreflect those of
`
`Manuscript received July 13, 1990; revised November 20, 1990.
`Z. Galani
`is with the Missile Systems Division, Raytheon Company,
`Hartwell Road, Bedford, MA 01730,
`R. A. Campbell
`is with the Missile Systems Division, Raytheon
`Company, 50 Apple Hill Drive. Tewksbury. MA O1876.
`IEEE Log Number 9143000,
`
`the radar. The major requirement categories are listed
`below.
`
`A. Electrical Requirements
`
`(total
`1) Frequency Format: The frequency format
`bandwidth, frequency spacing, etc.) is usually well defined
`by the requirements of the radar system. Occasionally
`there is a requirement for a specific pattern of frequen-
`cies versus time, but usually only frequency agility is
`required, i.e., a specific frequency upon command.
`2) Frequency Switching Time: Frequencyswitching time
`represents one of the driving requirements of various
`synthesizer architectures. While communication system
`and test equipment applications can usually perform ade-
`quately with millisecond frequency switching, radars often
`require microsecond switching. Fast switching has a defi-
`nite impact upon radar synthesizer design, because it
`eliminates from consideration closed-loop architectures
`with long frequency switching and settling times.
`3) Noise: Some radars, such as airborne ground avoid-
`ance systems, have modest noise requirements. The noise
`allocation of high-performance radars can be as much as
`70 dB lower, with all levels in between specified for other
`radar types. Amplitude noise levels are rarely as critical
`as phase noise since the amplitude noise can be reduced
`by balanced mixers, amplifiers in compression, or diode
`limiters. Phase noise close to the carrier, however, can be
`reduced only with either lower noise oscillators or with
`external closed-loop circuits. In most cases the net effect
`of amplitude noise is to add to the effective receiver noise
`level, but in applications involving nonlinear circuits, such
`as amplifiers in compression, some of the amplitude noise
`is converted to phase noise.
`4) Spurious Signals: Spurious signals either mask the
`radar returns or create false targets.
`5) Long-Term Frequency Stability: In some radar appli-
`cations long-term frequencystability is not as stringent as
`in communication systems,
`for when the same source
`determines both the transmission and the reception fre-
`quencies in a radar, a small amount of frequency drift is
`allowable. However, the absolute frequency must be con-
`trolled in radars requiring long integration times or radars
`that interact with other independent systems.
`6) Modulation: Modulation of radar signals is usually
`well defined in time, amplitude, and frequency. The typi-
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`GALANI AND CAMPBELL: AN OVERVIEW OF FREQUENCY SYNTHESIZERS
`
`783
`
`cal modulation waveform hasa fixed pattern in amplitude
`and frequency. Amplitude modulation and low-deviation
`phase modulation can be added following signal genera-
`tion, but frequency-modulated signals with large indiccs
`must be generated bytheoscillator.
`
`B. Mechanical Requirements
`
`The mechanical design of frequency synthesizers is
`influenced mainly by volume constraints and shielding
`requirements, While synthesizers for stationary radars
`have minimal volume constraints, synthesizers for air-
`borne applications, especially missiles, are designed to
`very rigidly defined form factors and weight limits which
`usually require some level of miniaturization. The degree
`of shielding needed in a synthesizer depends on the
`architecture,
`the allowable spurious levels, and EMI/
`EMC considerations.
`temperature ex-
`such as
`Environmental conditions
`tremes and vibration also have a significant
`impact on
`both electrical and mechanical designs of a synthesizer.
`Temperature extremes dictate the extent of the worst-case
`electrical design, thermal design, and the choice of appro-
`priate materials. Vibration levels dictate the integrity of
`the mechanical design and use of resilient mounts for
`potentially microphonic components. In the case of indi-
`rect synthesizers, they also dictate the use of loops with
`wider bandwidth to reduce oscillator phase noise under
`vibration.
`
`IL. FREQUENCY SYNTHESIZER ARCHITECTURES
`
`investigation of the specifications
`Usually an initial
`leads to the class of synthesizer architectures best suited
`for a given application. The choice is based upon such
`parameters as
`the number of frequencies,
`frequency
`spacing, frequency switching time, noise, spurious levels,
`volume constraints, and cost. The various classes of syn-
`thesizer architectures along with their essential character-
`istics are presented below.
`
`A. Direct Frequency Synthesizers
`
`This class of architectures creatcs its output frequency
`by mixing two or more signals to produce sum or differ-
`ence frequencies, by frequency multiplication, by fre-
`quency division, or by any combination thereof. The most
`widely uscd components are reference oscillators, fre-
`quency multipliers, frequency dividers, mixers, filters, and
`switches.
`The key advantages of direct synthesizers are fast fre-
`quency switching and the capability of some architectures
`to generate signals with very low phase noise. This low-
`noise performanceis achieved bythe selection of topolo-
`gies and components such that the additive phase noise of
`al] the components is considerably smaller than the multi-
`plied phase noise of the reference oscillators which deter-
`mine the output phase noise of the synthesizer. The
`disadvantages of direct synthesizers are that
`they are
`
` Fout= NF; +Fj
`
`1shjs4
`
`REFERENCE
`OSCILLATORS
`
`Fig.
`
`1. Direct frequency synthesizer block diagram.
`
`hardware intensive and tend to gencrate an excessive
`number of spurious signals.
`The various forms of direct synthesizers differ in the
`way their sets of frequencies are generated and in the
`number and organization of their mixers. The sets may be
`individual oscillators or synthesized frequencies them-
`selves. Mixers can be organized in series (the number of
`oulput frequencies being the product of the number of
`frequencies in the sets) or in parallel (for multiple fre-
`quency generation) or any combination thereof. The syn-
`thesizer can be described mathematically, wherein mixing
`is represented by addition or subtraction and harmonics
`(or subharmonics) by multiplication (or division).
`The exact form of a synthesizer is driven first by its
`gross features (number of frequencies, noise, etc.) and
`second by its spurious signal generation. The subject of
`spurious signals is considered in some detail in a subse-
`guent section of this paper.
`One direct frequency synthesizer capable of low-noise
`performance is shown in the block diagram of Fig. 1. It
`consists of a set of signal sources that are used twice to
`generate the output frequency. One source is selected
`and sent to a frequency multiplier, and then to the mixcr.
`The second signal to the mixer is another (or the same)
`source used directly. The output is the sum (or difference)
`of these two, yielding 16 frequencies at the output for a
`set of four sources. Variations on this concept would
`include the use of more than one multiplier and the use
`of multipliers in the direct path. An equivalent architec-
`ture could use frequencydividers such that the direct and
`divided paths to the mixer would produce the same result,
`provided the
`source
`frequencies were
`appropriately
`higher. This technique is often used to synthesize fre-
`quencics with spacings that are smaller than the reference
`frequency spacings.
`Another low-noise direct synthesizer architecture Is
`presented in Fig. 2. Here three sets of signal sources are
`used to gencrate 100 frequencies. One set has four fre-
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`IEEE TRANSACTIONS GN MICROWAVE THEORY AND TECHNIQUES, VOL. 39, NO. 5. MAY 1991
`
`REFERENCE
`OSCILLATORS
`
`
`
`
`REFERENCE OSCILLATORS
`
`Loop
`AMPLIFIER
`
` STABLE
`
`OSCILLATOR
`Fo
`PHASE
`DETECTOR
`
`
`
`
`OA
`COARSE
`Fout= NFo
`TUNING
`VOLTAGE
`
`Four= Fal + Fe) + Fox
`1sis4
`VepRkssd
`
`Fig. 2. Direct frequency synthesizer block diagram.
`
`Fig. 3. Analog phase-lock loop block diagram.
`
`LOOP
`AMPLIFIER
`
`quencies while the other two havefive. If the frequencies
`are chosen so that the output frequencies of the mixers
`are the difference between the input frequencies,
`then
`spurious signals with in-band frequencics caused by mixer
`intermodulation products are minimized.
`In any synthesizer architecture, the sources could all be
`oscillators, either free-running or phase-locked to a com-
`mon reference to achieve coherent operation, or CW
`signals generated bydirect or indirect means. Coherency,
`especially with respect to a radar’s pulse repetition rate,
`can reduce the effects of many spurioussignals.
`Many other direct synthesizer architectures are in exis-
`tence and are described in the literature [1]-[3]. A signifi-
`cant number of these architectures are not suitable for
`radar applications because of insufficicntly low noise
`and/or spurious signallevels.
`
`B. Direct Digital Synthesizers
`
`The DDS is the most recent addition to frequency
`synthesis architectures [1], [3], [4]. In response to digital
`commands, an accumulator generates a digital approxi-
`mation of a linearly increasing phase function, at a rate
`controlled by a reference oscillator. The output of the
`accumulator is applied to a read-only-memory (ROM)
`look-up table which converts the phase samples into sam-
`ples of a sinusoidal waveform. The ROM output is fed
`into a digital-to-analog (D/A) converter which generates
`an analog approximation of
`the sinusoidal waveform
`which, aftcr filtering by a low-pass filter, is the output of
`the synthesizer.
`The main advantages of the DDS architecture are fast
`and phase-continuous
`frequency switching, arbitrarily
`small frequency spacing, small size, and low cost. Its main
`disadvantages are a limited operating frequency and rela-
`tively high noise and spurious signal levels.
`
`C. Indirect Frequency Synthesizers
`
`Indirect frequency synthesizers serve a useful purpose
`in applications where very fast frequency switching and
`extremely low noise performance are not required. Indi-
`
`xn
`STABLE
`
`
`OSCILLATOR
`COMB
`vco
`
`
`GENERATOR
`
`
`Fo
`
`
`
`PHASE
`COARSE
`DETECTOR
`TUNING
`
`
`
`
`
`
`
`Fout= nFy
`nS AN INTEGER
`
`FREQUENCY
`SELECT
`
`Fig. 4.
`
`Block diagram of an analog indirect frequency synthesizer with
`a combgeneratorreference.
`
`into two broad cate-
`rect synthesizer architectures fall
`gories: analog and digital. Combinations of the two are
`also used in some applications. The fundamental building
`blocks of analog indirect synthesizers are either
`fre-
`quency-lock loops (FLL’s) [5] or analog phase-lock loops
`(PLL’s) [1], [4], [6] while digital indirect synthesizers com-
`prise digital PLL’s [1], [4], [6].
`1) Analog PLL Synthesizers: A block diagram of a basic
`analog PLL is presented in Fig. 3, in which a voltage-con-
`trolled oscillator (VCO) is phase-locked to a reference
`signal. Typically, the reference frequency is gencrated by
`a stable oscillator followed by a frequency multiplier. In
`this diagram a portion of the VCO signal and the refer-
`ence signal are the inputs to the phase detector. The
`output signal of the phase detector,
`representing the
`error signal,
`is amplified, filtered, and applied to the
`fine-tuning port of the VCO. Inside the loop bandwidth
`the phase noise of the VCO is reduced by the open-loop
`gain to a level limited by the phase noise of the reference.
`Frequency acquisition is accomplished by applying a volt-
`age to the coarse-tuning port of the VCO to slew its
`frequency into the capture range of the PLL.
`A frequency synthesizer based on an analog PLL with
`output frequencies corresponding to selected harmonics
`of a stable frequency is shown in Fig. 4. Here the refer-
`ence frequency is generated by a stable oscillator followed
`by a comb generator. Frequency switching is performed
`by applying a voltage to the coarse-tuning port of the
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`PACT -SMS 2024-0110
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`PACT - Ex. 2014.0010
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`GALANI AND CAMPBELL: AN OVERVIEW OF FREQUENCY SYNTHESIZERS
`
`785
`
`LOOP
`
`AMPLIFIER
`
`Four = Fx tNFo
`
`
`
`Fig. 5. Single-offset analog phase-lock loop block diagram.
`
`LOOP
`AMPLIFIER
`
`FREQ
`DETECTOR
`
`
`
`Fout=MFo
`
`FREQUENCYSPACING = Fo
`
`
`FREQUENCY
`SELECT
`
`Fig. 6. Digital indirect frequency synthesizer block diagram.
`
`VCO andeither opening the loop or slewing the voltage
`at a rate that is faster than the loop can follow, to prevent
`the loop from inhibiting the frequency change. An alter-
`native method of reference frequency generation could
`use a bank of switched stable oscillators followed by
`frequency multipliers.
`Offset PLL’s offer another method of frequency syn-
`thesis. A block diagram of a single-offset analog PLL is
`shown in Fig. 5. Here the VCO frequency is heterodyned
`to a lower frequency using the signal of an offset genera-
`tor. Frequency agility can be achieved with a multifre-
`quency offset generator
`in conjunction with a fixed-
`frequency or a multifrequency reference. An arbitrary
`frequency resolution can be realized by successively het-
`erodyning the VCO frequency with several multifre-
`quency offset generators with successively finer frequency
`resolution. In cases where the multifrequency offset gen-
`erators are indirect frequency synthesizers, the resultant
`is a multiloop architecture.
`The phase noise (inside the loop bandwidth) of the
`architectures in Figs. 3 and 4 is usually determined by the
`VCO noise, the open-loop gain, and the phase noise of
`the reference. In the case of the architecture in Fig. 5, it
`could be influenced also by the phase noise of the offset
`generator.
`2) Digital PLL Synthesizers: A block diagram ofa basic
`digital
`indirect synthesizer (based on a digital PLL) is
`shown in Fig. 6. Here the VCO is phase-locked to a
`harmonic of the reference frequency, the harmonic order
`
`LOOP
`
`AMPLIFIER “
`
`FREQUENCY.
`
`F our = FOMNLK) = F(M,1) NF
`F(M,K) = Fy ¢ MF/Kk
`FREQUENCY SPAGING = Fo/K
`
`Fig. 7. Block diagram of a two-loop digital indirect frequency synthe-
`sizer.
`
`being equal to the division ratio of the digital frequency
`divider. Synthesis of equally spaced frequencies (frequency
`spacing equal
`to the reference frequency) is performed
`using a programmable digital frequcncy divider, with all
`the frequencies synthesized by programming suitable divi-
`sion ratios. The operation of this PLL is similar to that in
`Fig. 3 except that here phase detection is performed at a
`reference frequency which is a subharmonic of the VCO
`frequency. The frequency is switched with a digital com-
`mand that changes the frequency division ratio and causes
`the
`loop to unlock. Under
`these
`conditions
`the
`phase /frequency detector generates a frequency-depen-
`dent voltage which, following amplification and filtering,
`slews the frequency of the VCO to the lock frequency. In
`some applications, external frequency acquisition aids arc
`added to reduce the frequency switching time. In the
`block diagram of Fig. 6 the phase noise of the VCO
`(inside the loop bandwidth) can be reduced by the open-
`loop gain to a level
`that
`is limited by the multiplied
`cumulative noise of the reference,
`the phase/frequency
`detector,
`the digital divider, and the loop amplifier.
`Therefore, large frequency division ratios cannot be used
`in low noise applications.
`Offset digital PLL’s are usually limited to a single offset
`because of the presence of the digital frequency dividers.
`Such PLL’s are used in applications where the VCO
`frequency exceeds the highest operating frequency of the
`programmable frequency divider and the phase noise
`requirements preclude the use of
`a_ high-frequency
`prescaler (fixed-division-ratio frequency divider) because
`it increases the frequency division ratios.
`In low-noise applications requiring synthesis of a large
`number of frequencies, multiple-loop architectures are
`used to reduce the maximum frequencydivision ratio and
`the numberof ratios that otherwise would be necessary.
`In the two-loop synthesizer shown in Fig. 7 an auxiliary
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`PACT -SiS 2024-00011
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`PACT - Ex. 2014.0011
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`

`

`786
`
`IEEE TRANSACTIONS ON MICROWAVE TIIEORY AND TECHNIQUES, VOL.30, NO. 5, MAY 1991
`
`
`
`é
`DC OFFSET
`VOLTAGE
`DELAYLINE
`RESONATOR
`Fig. 9. Block diagram of a single-resonator oscillator and frequency-
`Four =0/t +At(@)
`Four =F a+ At(o)
`lock loop.
`T= TIME DELAY
`Fp = RESONANT FREQUENCY
`n lS AN INTEGER
`
`
`
`zFp+At( St, 02)
`
`Four
`
`Fig. 8. Frequency-lock loop block diagram.
`
`loop is used to synthesize offset frequencies for the main
`loop. To synthesize 100 equally spaced frequencies the
`architecture in Fig. 6 would require 100 consecutive fre-
`quency division ratios while the architecture in Fig. 7
`could have ten consecutive frequency division ratios in
`each loop. For example,
`if the division ratios in Fig. 6
`ranged from 101 to 200, then inside the loop bandwidth
`the cumulative phase noise at
`the reference frequency
`would be enhanced by as much as 46 dB (20 log N). In
`Fig. 7, on the other hand, using K = 10, the lower loop
`would have division ratios (M) from 11
`to 20, which
`results in maximum noise enhancement of 26 dB. The
`upper loop would therefore have ratios (N) from 1 to 10,
`which cause 20 dB maximum noise enhancement. The
`total noise enhancement
`is 27 dB because the output
`noise is the statistical sum of the enhanced noise and the
`noise of the offset signal.
`3) FLL Synthesizers: Frequency-lock loops (FLL’s) of-
`fer another method of indirect frequency synthesis. The
`major difference between a PLL and a FLLis that the
`frequency stability of a PLL is related to that of a refer-
`ence oscillator while the frequency stability of a FLL is
`related to the phase stability of a passive dispersive ele-
`ment in the discriminator, such as a resonator or a delay
`line. In the block diagram of a typical FLL shown inFig.
`8, a portion of the VCO output signal is applied to the
`input of a discriminator. Variations in the VCO output
`frequency are converted to voltage variations which are
`amplified, filtered, and fed to the fine-tuning port of the
`VCO to reduce these frequency variations. The phase
`noise realizable with