PACT XPP SCHWEIZ AG
`
`
`
`
`
`INTEL CORPORATION,
`
`
`
`Plaintiff,
`
`
`
`v.
`
`
`
`Defendant.
`
`
`
`
`
`
`
`
`
`IN THE UNITED STATES DISTRICT COURT
`FOR THE DISTRICT OF DELAWARE
`
`
`
`
`C.A. No. 19-1006-JDW
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`
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`)
`)
`)
`)
`)
`)
`)
`)
`)
`
`JOINT CLAIM CONSTRUCTION CHART
`
`Pursuant to Paragraph 9 of the Scheduling Order (D.I. No. 20), Plaintiff PACT XPP Schweiz AG (“PACT”) and Intel Corporation
`
`(“Intel”) hereby submit this Joint Claim Construction Chart, identifying for the Court the terms and phrases of the claims in issue,
`
`including each party’s proposed construction of the disputed claim language with citations only to the intrinsic evidence in support of
`
`their respective proposed constructions.
`
`
`
`
`
`1
`
`INTEL - 1011
`
`
`
`
`
`
`
`INTEL CORPORATION,
`
`
`
`Plaintiff,
`
`
`
`v.
`
`
`
`Defendant.
`
`
`
`
`
`
`
`
`
`IN THE UNITED STATES DISTRICT COURT
`FOR THE DISTRICT OF DELAWARE
`
`
`
`
`C.A. No. 19-1006-JDW
`
`
`
`)
`)
`)
`)
`)
`)
`)
`)
`)
`
`JOINT CLAIM CONSTRUCTION CHART
`
`Pursuant to Paragraph 9 of the Scheduling Order (D.I. No. 20), Plaintiff PACT XPP Schweiz AG (“PACT”) and Intel Corporation
`
`(“Intel”) hereby submit this Joint Claim Construction Chart, identifying for the Court the terms and phrases of the claims in issue,
`
`including each party’s proposed construction of the disputed claim language with citations only to the intrinsic evidence in support of
`
`their respective proposed constructions.
`
`
`
`
`
`1
`
`INTEL - 1011
`
`
`
` |IntentionallyLeftBlank
`
`Excerpts of File History of U.S. Patent No. 9,552,047 relied on by
`Plaintiff
`25
`Intentionally Left Blank
`poIntentionallyLeftBlank
`26
`Intentionally Left Blank
`
`|IntentionallyLeftBlank
`27
`Intentionally Left Blank
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`TABLE OF EXHIBITS
`
`U.S. Patent No. 8,312,301
`
`Plaintiff
`
`
`
`1 : 3
`
`4 5 6 7 8 9 1
`
`0
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`18
`
`19
`
`20
`
`22
`
`23
`24
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`
`
`INTEL - 1011
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`
`
`Exhibit No.
`
`Document
`
`28
`29
`30
`
`31
`32
`
`33
`
`34
`35
`
`36
`
`37
`
`Intentionally Left Blank
`Intentionally Left Blank
`Excerpts of File History of U.S. Patent No. 8,819,505 relied on by
`Defendant
`Intentionally Left Blank
`Excerpts of File History of U.S. Patent No. 9,075,605 relied on by
`Defendant
`Excerpts of File History of U.S. Patent No. 9,170,812 relied on by
`Defendant
`Intentionally Left Blank
`Excerpts of File History of U.S. Patent No. 9,436,631 relied on by
`Defendant
`Excerpts of File History of U.S. Patent No. 9,552,047 relied on by
`Defendant
`
`DE 196 54 846 Al
`
`INTEL - 1011
`
`
`
`STIPULATED CLAIM TERMS
`
`
`
`Preambles (claims 2, 10, 14, 15
`Preambles (claims 1-6, 24, 26-27,
`29, 32, 44, and 73-74
`
`Preamblesare notlimiting.
`Preambles are notlimiting.
`
`807
`
`TERMS PROPOSED BY PLAINTIFF
`
`Plaintiff's Intrinsic
`Defendant’s
`Plaintiff’s
`:
`:
`Claim Terms
`Evidence
`Proposed
`Proposed
`dPh
`Patent
`an Construction|ConstructionFases
`
`
`
`“interconnecting|connectat Ex. 1, Figs. 1, 2(a)-2(c), 3,|See e.g., Ex. 1 (°763 patent) at 2:16-23;See Intel’s
`
`
`
`at runtimeat least one data|construction for|4, 5 12:5-17; 4:4-10; 12:38-83: 9:3-9:6:
`
`
`least one of data|processing “programmably|7:47-11:12; 11:21-45. 6:56-7:6; 1:26-28; 8:45-55.
`
`processing cells|cell, at least interconnecting
`and memory
`one memory
`at runtime”/
`cells with at
`cell, and at
`“dynamically
`least one of
`least one
`interconnecting
`°763
`
`memory cells interface unit|at runtime”
`and one or more|with each
`of the at least
`otherat
`one interface
`runtime.
`
`unit” (claims 1,
`
`Defendant’s Intrinsic Evidence
`
`INTEL - 1011
`
`
`
`Plaintiff’
`
`Proposed
`
`Evidence
`
`Plaintiffs Intrinsic
`
`Defendant’s Intrinsic Evidence
`
`6:56-7:6; 1:26-28; 8:45-55.
`
`Defendant’s
`on Terms
`Proposed
`Construction
`Construction
`Ex. 1, Figs. 1, 2(a)-2(c), 3,|See e.g., Ex. 1 (’763 patent) at 2:16-23;
`See Intel’s
`each of the
`“the data
`data
`construction for
`4,5
`12:5-17; 4:4-10; 12:38-83; 9:3-9:6;
`processing cells
`processing
`“programmably
`7:47-11:12; 11:21-45.
`are adapted to
`interconnecting
`cells is
`connect
`adapted to
`at runtime”/
`simultaneously
`simultaneously
`“dynamically
`to a plurality of
`interconnecting
`connect to a
`plurality of
`at least one of
`at runtime”
`elements; each
`cells and units
`of at least one of
`of the
`the memory
`elements is
`cells, the data
`either one of
`processing cells,
`the memory
`cells, another
`and the at least
`one interface
`one of the data
`units” (claim
`processing
`10)
`cells, or the
`interface unit.
`
`INTEL - 1011
`
`
`
`Plaintiff’
`
`Proposed
`
`Evidence
`
`Plaintiffs Intrinsic
`
`Defendant’s Intrinsic Evidence
`
`Defendant’s
`on Terms
`Proposed
`Construction
`Construction
`Ex. 1, Figs. 1, 2(a)-2(c), 3,|See e.g., Ex. 1 (’763 patent) at 2:16-23;
`See Intel’s
`the data
`“cells of the
`data processing
`processing
`construction for
`4,5
`12:5-17; 4:4-10; 12:38-83; 9:3-9:6;
`cells are adapted
`“programmably
`cells are
`7:47-11:12; 11:21-45.
`adapted to
`interconnecting
`to connect
`simultaneously
`simultaneously
`at runtime”/
`“dynamically
`to other cells of
`connect each
`interconnecting
`the data
`other and toa
`processing cells
`plurality of
`at runtime”
`elements: each
`and toa
`plurality of at
`of the
`least one of
`elements is
`cells and units
`either one of
`the memory
`of at least one of
`the memory
`cells, another
`one of the data
`cells, the data
`processing cells,
`processing
`cells, or the
`and the at least
`one interface
`interface unit.
`units” (claim
`
`6:56-7:6; 1:26-28; 8:45-55.
`
`INTEL - 1011
`
`
`
`Plaintiff’
`
`Proposed
`
`Evidence
`
`Plaintiffs Intrinsic
`
`Defendant’s Intrinsic Evidence
`
`Defendant’s
`on Terms
`Proposed
`Construction
`Construction
`
`simultaneously Ex. 1, Figs. 1, 2(a)-2(c), 3,|See e.g., Ex. 1 (’763 patent) at 2:16-23;
`See Intel’s
`“interconnecta
`data processing
`interconnect a
`construction for
`4,5
`12:5-17; 4:4-10; 12:38-83; 9:3-9:6;
`“programmably
`cell
`data
`7:47-11:12; 11:21-45.
`processing cell
`interconnecting
`simultaneously
`to a plurality of
`to a plurality
`at runtime”/
`“dynamically
`of elements;
`at least one of
`interconnecting
`cells and units
`each of the
`of at least one of
`elements is
`at runtime”
`the memory
`either one of
`the memory
`cells, others of
`cells, another
`the data
`processing cells,
`one of the data
`processing
`and the at least
`cells, or the
`one interface
`units” (claim
`interface unit.
`
`6:56-7:6; 1:26-28; 8:45-55;
`
`INTEL - 1011
`
`
`
`Plaintiff’
`
`Proposed
`
`Defendant’s
`on Terms
`Proposed
`Construction
`Construction
`
`simultaneously|See Intel’s Ex. 1, Figs. 1, 2(a)-2(c), 3,|See e.g., Ex. 1 (’763 patent) at 2:16-23;
`construction for|4, 5
`interconnect
`12:5-17; 4:4-10; 12:38-83; 9:3-9:6;
`“programmably|7:47-11:12; 11:21-45.
`“qnterconnect a
`each one of a
`6:56-7:6; 1:26-28; 8:45-55.
`plurality of data
`plurality of
`interconnecting
`processing cells
`at runtime”/
`data
`simultaneously
`processing
`“dynamically
`to a plurality of
`interconnecting
`cells toa
`plurality of
`at least one of
`at runtime”
`elements; each
`cells and units
`of at least one of
`of the
`the memory
`elements is
`cells and the
`either one of
`the memory
`interface units”
`(claim 13)
`cells or the
`interface unit.
`
`construction necessary
`
`Plaintiffs Intrinsic
`Evidence
`
`Defendant’s Intrinsic Evidence
`
`Preambles are|Ex.1, Fig. 1, 2(a)-(c), 3, Preamblesare not limiting / no
`
`
`Preamblesare
`limiting.
`not limiting /
`4,5, 6,
`Preambles
`no construction|2:52-59; 5:53-6:21; 7:31-
`(claims 1 and
`necessary
`8:10; 8:26-31; 10:34-11:2;
`31)
`11:13-20;
`Claims 20, 50.
`
`INTEL - 1011
`
`
`
`Defendant’s Intrinsic Evidence
`
`4863.
`
`Plaintiffs Intrinsic
`Defendant’s
`Plaintiffs
`.
`:
`Claim Terms
`Evidence
`Proposed
`Proposed
`and Phrases
`Patent
`Construction|Construction
`
`Preambles are|Claims 6, 8, 10,|Ex. 24, August 10, 2016 Claims 6, 8, 10, 12: Preambles are not
`
`
`limiting. 12: Preambles_|Remarks at 13-16; limiting / no construction necessary.
`are not limiting
`Claim 3: “reconfigurable and
`Ex.3, Fig. 1;
`/no
`
`construction 1:25-36; 2:1-19; 4:43-46;|sequential data processors where the
`
`necessary. 6:7-61; 8:64-9:2; 9:3-11;|data results from one processorare fed
`
`Claim 3: See 9:44-55; 10:23-36; 12:66-|to another, for each processor to
`Intel’s
`13:11;
`perform a separate computation” (See
`
`Preambles construction for|claim 3. term “reconfigurable and sequential
`
`(claims 3, 6, 8,
`“data
`data processors wherethe data results
`10, 12)
`processing
`from one processorare fed to another,
`element”
`for each processor to perform a
`and/or “data
`separate computation’)
`processing
`elements
`adapted for
`programmably
`processing
`sequences”
`Preambles are|Preambles are|Ex. 4, 2:17-36, 3:34-39, See e.g., Ex. 4 (593 patent) at 3:34-44;
`
`Preambles 6:7-58, 7:41-59, 8:55-58,|2:18-34.limiting. not limiting /
`
`
`
`
`(claims 1 and no construction|9:22-26, 9:34-10:26, 12:7-
`16)
`necessary
`16;
`Figs. 1-2, 9
`Preambles are|Preambles are|Ex.6, Figs. 1-19; See, e.g., Ex. 6 (505 patent) at 2:40-
`
`Preambles 1:20-60; 6:55-67; 7:5-35;|42;limiting. not limiting /
`
`
`
`
`(claims 1, 14, no construction|12:20-13:17.
`16-18, 27)
`necessary
`See, e.g., Ex. 30 (505 File History) at
`
`INTEL - 1011
`
`
`
`Plaintiffs Intrinsic
`
`Defendant’s Intrinsic Evidence
`
`Evidence
`
`See term “data processing element”
`and/or “data processing elements
`adapted for programmably processing
`sequences”
`
`Ex. 24, August 10, 2016
`Remarks at 13-16.
`
`Ex. 8, 4:50-53;
`Figs. 1, 2,
`7:66-8:18, 8:34-59, 9:4-
`18, 9:37-44, 11:31-12:3;
`claim 1.
`
`Defendant’s
`Proposed
`Construction
`See Intel’s
`construction for
`“data
`processing
`unit” and/or
`“data
`processing
`unit...adapted
`for sequentially
`processing
`data”
`
`4:37, 5:29-7:2, 7:52-8:62, 9:1-10:29.
`
`Plaintiff’
`
`Proposed
`
`Construction
`passing results
`onto one or
`more other
`data
`processing
`units which
`are
`subsequently
`processing
`data
`
`Preamble is
`limiting.
`
`on Terms
`
`“sequentially
`processing data”
`
`Preamble (claim
`12)
`
`See, e.g., Ex. 9 (812 patent) at
`Abstract, 2:10-14, 2:47-3:15, 3:47-
`
`Preamble is not
`limiting / no
`construction
`
`necessary
`
`Ex. 9, Abstract, 2:5-14,
`2:47-3:15, 8:7-20, 11:17-
`26, 31:56-32:6, 34:30-38
`44:19-22, 159:20-23;
`Figs. 16, 18, 20, 77, 80.
`
`Ex. 21, Amendment &
`Remarks (May 18, 2015),
`Office Action (Feb. 3,
`
`INTEL - 1011
`
`
`
`Plaintiffs Intrinsic
`
`Defendant’s Intrinsic Evidence
`
`Evidence
`
`Ex. 24, August 10, 2016
`Remarks at 13-16.
`
`Ex. 12, 4:54-57.
`
`Ex. 8, 7:66-8:18, 8:34-59,
`9:37-44 (corresponding
`disclosures in Ex. 12)
`
`See term “data processing element”
`and/or “data processing elements
`adapted for programmably processing
`sequences”
`
`Defendant’s
`Proposed
`Construction
`See Intel’s
`construction for
`“data
`processing
`element”
`and/or “data
`processing
`unit...adaptable
`for sequentially
`processing
`data”
`
`disclosures in Ex. 12
`
`Plaintiff’
`
`Proposed
`
`Construction
`passing results
`onto one or
`more other
`data
`processing
`units which
`are
`subsequently
`processing
`data
`
`Preamblesare
`limiting.
`
`on Terms
`
`“sequentially
`processing data”
`(claims 1-5, 8,
`10, 15, 19, 22,
`24)
`
`Preambles
`(claims 1, 19)
`
`Preamble is not limiting / no
`construction necessary
`
`Preamblesare
`not limiting /
`no construction
`
`necessary
`
`Ex. 12,Fig. 1;
`
`2:24-34; 4:58-67; 8:1-7:
`9:20-37; 11:57-2:4;
`Claims 19, 33.
`Ex. 8, 1:28-48, 2:45-67,
`3:61-4:49, 6:14-67, 8:29-
`9:3, 13:54-14:3, Fig. 4, 5
`(corresponding
`
`INTEL - 1011
`
`
`
`Al) at Col. 17.
`
`See e.g., Ex. 1 (’763 patent) at 7:20-28;
`1:23-25; 1:61-2:2; 3:18-33: 10:61-
`11:2; 3:58-4:2; 1:23-25: 3:34-51; 7:52-
`60; see e.g., Ex. 37 (DE 196 54 846
`
`Patent Claim Terms and
`Phrases
`
`“data processing
`cells, each adapted
`for sequentially
`executing” (claims
`1,31)
`
`Defendant’s Intrinsic Evidence
`
`TERMS PROPOSED BY DEFENDANT
`
`Plaintiff’
`
`Proposed
`
`Construction
`Plain and
`ordinary
`meaning. No
`construction
`
`necessary.
`
`Defendant’s
`Proposed
`Construction
`“reconfigurable
`processor
`function cells
`adapted for
`sequentially
`executing”
`
`Plaintiff’s Intrinsic
`Evidence
`
`Ex. 1, Figs. 2(a)-2(c),
`
`1:23-44; 2:16-45:
`3:18-33; 4:19-39:
`5:17-6:35; 8:61-
`10:30; 10:23-30.
`
`INTEL - 1011
`
`
`
`Patent Claim Terms and
`Phrases
`
`Plaintiff’
`
`Proposed
`
`Construction
`Noconstruction
`necessary for
`“programmably
`” or
`“dynamically.”
`Plain and
`ordinary
`meaning.
`
`Defendant’s
`Proposed
`Construction
`“programmably
`reconfiguring
`interconnects at
`runtime”/
`“dynamically
`reconfiguring
`interconnects at
`runtime”
`
`“programmably
`interconnecting at
`runtime”/
`“dynamically
`interconnecting at
`runtime” (claims
`1,31)
`
`Plaintiff’s Intrinsic
`
`Defendant’s Intrinsic Evidence
`
`Evidence
`
`Ex. 1, Figs. 2(a)-2(c);
`1:23-44; 2:16-45;
`
`See e.g., Ex. 1 (°763 patent) at 2:16-23;
`12:5-17; 4:4-10; 12:38-83; 9:3-9:6;
`
`5:17-6:35; 8:61-10:30|6:56-7:6; 1:26-28; 8:45-55.
`
`For
`“interconnectin
`g at runtime,”
`See PACT’s
`proposed
`construction of
`“interconnectin
`g at runtimeat
`least one of data
`processing cells
`and memory
`cells with at
`least one of
`memory cells
`and one or more
`of the at least
`one interface
`unit.””
`
`INTEL - 1011
`
`
`
`sequences”
`
`Ex. 8, Abstract, 1:28-
`48, 2:45-67, 3:61-
`4:49, 6:14-67, 8:29-
`9:3, 11:31-12:3,
`12:16-34, 13:53-
`14:3, Fig. 1, 4,5
`(corresponding
`disclosures in Ex. 3
`Ex. 24, August 10,
`2016 Remarks at 13-
`16.
`
`Plaintiff’s Intrinsic
`
`Defendant’s Intrinsic Evidence
`
`Evidence
`
`Ex. 24, August 10,
`2016 Remarks at 13-
`16.
`
`Ex. 3, 1:25-36; 2:1-
`19; 3:31-40, 7:58-
`8:11; 4:43-46, 6:7-61;
`9:44-55;
`claim 3.
`
`See e.g., Ex. 36 (’047 File History) at
`551-53;
`
`See, e.g., Ex. 3 (301 patent) at 4:43-
`46; 2:1-3; 11:23-28: 10:62; 11:49-58;
`2:22-24; 1:26-36; 4:66-5:4; 5:21-32;
`8:27-30.
`
`See term “data processing element”
`and/or “data processing elements
`adapted for programmably processing
`
`Ex. 8, 1:25-38; 2:4-
`23; 4:50-53.
`claim 1.
`
`Ex. 8, Abstract, 2:45-
`63, 11:31-12:3,
`12:16-34, 13:53-59,
`Fig. 1,4
`
`Plaintiff’
`
`Proposed
`
`Construction
`Plain and
`ordinary
`meaning. No
`construction
`necessary.
`
`Patent Claim Terms and
`Phrases
`
`“data processing
`element” and/or
`“data processing
`elements adapted
`for programmably
`processing
`sequences”
`(claims 3, 6, 8-10,
`12-14, 16-18, 23-
`26, 30, 32, 35)
`
`See PACT’s
`proposed
`construction of
`“sequentially
`processing
`data.”
`
`“data processing
`unit” and/or “data
`processing unit .. .
`adapted for
`sequentially
`processing data”
`(claim 1)
`
`Defendant’s
`Proposed
`Construction
`“reconfigurable
`and sequential
`data processors
`where the data
`results from one
`
`processorare
`fed to another,
`for each
`
`processorto
`perform a
`separate
`computation”
`
`“reconfigurable
`and sequential
`data processors
`where the data
`results from one
`
`processorare
`fed to another,
`for each
`processorto
`perform a
`separate
`computation”
`
`INTEL - 1011
`
`
`
`Patent Claim Terms and
`Phrases
`
`“to a minimum”
`(claim 1)
`
`Plaintiff’
`
`Proposed
`
`Construction
`Plain and
`ordinary
`meaning. No
`construction
`
`necessary.
`
`378; Ex. 8 at 3:24-30.
`
`Defendant’s
`Proposed
`Construction
`“to a level no
`more than is
`required for the
`preservation of
`memory
`contents or the
`like”
`
`Plaintiff’s Intrinsic
`
`Defendant’s Intrinsic Evidence
`
`See, e.g., Ex. 32 (°605 File History) at
`
`Evidence
`
`Ex. 8, col.3:22-36;
`4:18-33; 4:57-58;
`5:28-56; 5:63-6:14;
`7:3-20; 7:24-54;
`7:55-61; 8:34-59:
`10:1-19; 11:67-12:3;
`13:8-30.
`
`Ex. 12, claims 16, 30.
`
`INTEL - 1011
`
`
`
`Patent Claim Terms and
`Phrases
`
`Plaintiff’
`
`Proposed
`
`Construction
`Plain and
`ordinary
`meaning.
`
`“instruction
`dispatch
`unit...configured
`to dispatch
`software threads to
`the array data
`processorfor
`parallel execution
`by the parallel
`processing
`arithmetic units”
`(claim 12)
`
`Defendant’s
`Proposed
`Construction
`Subject to 35
`U.S.C. §112,
`sixth paragraph
`Function:
`Dispatch
`software
`threads to the
`array data
`processorfor
`parallel
`execution by
`the parallel
`processing
`arithmetic units.
`Structure:Fig.
`80A,
`configuration
`unit (CT).
`
`77A-J, 80A-C.
`
`Ex. 9, 13:55-59,
`16:44-45, 19:60-20:8,
`20:56-58, 25:9-12,
`26:37-46, 28:55-29:2,
`31:43-55, 32:60-
`33:24, 34:29-48,
`35:34-37, 36:7-14,
`39:26-37, 43:33-35,
`44:1-10, 44:42-58,
`138:37-139:4,
`140:21-27, 140:44-
`56, 158:46-49,
`159:20-160:38,
`162:62-66, 163:11-
`22, 164:53-56,
`165:16-21
`
`Plaintiff’s Intrinsic
`
`Defendant’s Intrinsic Evidence
`
`Evidence
`
`See e.g., Ex. 33 (812 File History) at
`Response to Rejection (5/18/15), Non-
`Final Rejection (2/17/15).
`
`See e.g., Ex. 9 (812 patent) at Fig.
`
`Figs. 13, 16-18, 20,
`80A-C
`
`Ex. 21, Amendment
`& Remarks (May 18,
`2015), Office Action
`eb. 3, 2015
`
`INTEL - 1011
`
`
`
`Plaintiff’
`
`Proposed
`
`Construction
`Plain and
`ordinary
`meaning. No
`construction
`
`necessary.
`
`See PACT’s
`proposed
`construction of
`“sequentially
`processing
`data.”
`
`Patent Claim Terms and
`Phrases
`
`“a plurality of bus
`segments for each
`processorof the
`multiprocessor
`system”(claim 1)
`
`.
`
`“data processing
`unit” and/or “data
`processing unit. .
`adaptable for
`sequentially
`processing data”
`(claims 1-5, 8, 10,
`15, 19, 22, 24)
`
`Defendant’s
`Proposed
`Construction
`“a plurality of
`bus segments
`for each
`processorof the
`multiprocessor
`system, each
`bus segment
`connected to
`only one of the
`processors”
`“reconfigurable
`and sequential
`data processors
`where the data
`results from one
`
`sequences”
`
`Plaintiff’s Intrinsic
`
`Defendant’s Intrinsic Evidence
`
`See, e.g., Ex. 11 (631 patent) at Figs.
`5, 6; 15:25-27, 24:58-61, 26:42-47,
`27:22-35;
`
`See, e.g., Ex. 35 (°631 File History) at
`Response After Final, 1/14/16; see also
`Final Rejection, 10/29/15 (Claim
`Rejections - 35 USC 103).
`
`See term “data processing element”
`and/or “data processing elements
`adapted for programmably processing
`
`Evidence
`
`Ex. 11,
`Claim 1;
`13:52-15:60;
`Fig. 5
`25:49-62:
`Fig. 6
`26:38-41.
`
`Ex. 24, August 10,
`2016 Remarks at 13-
`16.
`047 Patent, col.4:54-
`57.
`
`Ex. 12, 1:29-39; 2:4-
`23; claims 1-5, 8, 10,
`15, 19, 22, 24:
`
`Ex. 8, Abstract, 2:45-
`63, 11:31-12:3,
`12:16-34, 13:53-59,
`Fig. 1,4
`(corresponding
`disclosures in Ex. 12
`
`processorare
`fed to another,
`for each
`
`processorto
`perform a
`separate
`computation”
`
`INTEL - 1011
`
`
`
`Dated: January 31, 2020
`
`FARNAN LLP
`
`By: /s/ Brian E. Farnan
`Brian E. Farnan (Bar No. 4089)
`Michael J. Farnan (Bar No. 5165)
`919 North Market Street, 12th Floor
`Wilmington, DE 19801
`Telephone: (302) 777-0300
`Facsimile: (302) 777-0301
`bfarnan@farnanlaw.com
`mfarnan@farnanlaw.com
`
`Danielle L. Gilmore (Pro Hac Vice)
`daniellegilmore@quinnemanuel.com
`Frederick A. Lorig (Pro Hac Vice)
`fredericklorig@quinnemanuel.com
`Pushkal Mishra (Pro Hac Vice)
`pushkalmishra@quinnemanuel.com
`QUINN EMANUEL URQUHART &
`SULLIVAN, LLP
`865 S. Figueroa Street, 10th Floor
`Los Angeles, CA 90017
`Tel : (213) 443-3047
`
`Mark Tung (Pro Hac Vice)
`marktung@quinnemanuel.com
`QUINN EMANUEL URQUHART &
`SULLIVAN, LLP
`555 Twin Dolphin Dr., 5th Floor
`Redwood Shores, CA 94065
`Tel.: (650) 801-5016
`
`Respectfully submitted,
`
`Morris, Nichols, Arsht & Tunnell LLP
`
`By: /s/ Jack B. Blumenfeld__
`Jack B. Blumenfeld (#1014)
`Brian P. Egan (#6227)
`1201 North Market Street
`P.O. Box 1347
`Wilmington, DE 19899
`(302) 658-9200
`jblumenfeld@mnat.com
`began@mnat.com
`
`Gregory S. Arovas P. C.
`KIRKLAND & ELLIS LLP
`601 Lexington Avenue
`New York, NY 10022
`(212) 446-4800
`greg.arovas@kirkland.com
`
`Adam R. Alper
`Brandon Brown
`KIRKLAND & ELLIS LLP
`555 California Street, Suite 2700
`San Francisco, CA 94104
`(415) 439-1400
`adam.alper@kirkland.com
`
`Michael W. De Vries
`Christopher M. Lawless
`Sharre Lotfollahi
`Kevin Bendix
`
`
`
`18
`
`INTEL - 1011
`
`
`
`
`Ziyong Li (Pro Hac Vice)
`seanli@quinnemanuel.com
`QUINN EMANUEL URQUHART &
`SULLIVAN, LLP
`50 California Street, 22nd Floor
`San Francisco, CA 94111
`Tel.: (415) 875-6600
`
`ATTORNEYS FOR PLAINTIFF
`PACT XPP Schweiz AG
`
`
`
`Allison W. Buchner
`KIRKLAND & ELLIS LLP
`333 South Hope Street
`Los Angeles, CA 90071
`(213) 680-8400
`michael.devries@kirkland.com
`christopher.lawless@kirkland.com
`sharre.lotfollahi@kirkland.com
`kevin.bendix@kirkland.com
`allison.buchner@kirkland.com
`
`ATTORNEYS FOR DEFENDANT
`Intel Corporation
`
`19
`
`
`
`
`
`
`
`
`
`
`INTEL - 1011
`
`
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