`
`
`
`
`
`
`U.S. DEPARTMENT OF COMMERCE
`
`
`
`
`
`
`PATENT AND TRADEMARK OFFICE
`
`
`
`
`
`
`CONTINUATION PATENT APPLICATION
`
`
`TRANSMITTAL LETTER
`
`
`
`
`UNDER37 C.F.R. 1.53(b)
`
`
`
`ATTORNEY DOCKETNO.:
`
`
`
`
`2885/139
`
`
`
`Addressto:
`
`
`Commissioner for Patents
`
`
`
`P.O. Box 1450
`
`
`Alexandria, VA 22313-1450
`
`
`
`
`
`
`
`
`
`
`
`
`Transmitted herewith for filing is a patent application.
`
`
`
`
`Inventor(s):
`
`
`
`
`
`
`
`
`
`
`
`
`
`Martin VORBACH-- BerlinerStrasse 50, 67360 Lingenfeld, Federal Republic of Germany
`
`
`
`
`
`
`For: RECONFIGURABLE SEQUENCER STRUCTURE
`
`
`
`
`
`1.
`
`
`Enclosed are:
`
`
`
`
`
`
`
`
`
`A.
`
`B.
`
`C.
`
`
`
`
`
`
`
`
`
`
`-25- pages of specification, -4- pages of claims, and -1- page of abstract;
`
`
`
`
`
` -6- sheet(s) of drawing(s);
`
`
`
`
`
`Preliminary Amendment; and
`
`
`
`
`
`2.
`
`
`
`3.
`
`
`
`
`
`
`
`
`
`
`
`
`D. Declaration and Appointment of Power of Attorney (copies from prior application
`
`
`
`
`
`
`
`
`
`(37 CFR 1.63(d) and 3.73(b) Statement) (See paragraph 5 below),
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Incorporation by Reference. The entire disclosure of the prior application, from
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`which a copy of the oath or declaration is supplied underparagraph 1(D) aboveis
`
`
`
`
`
`
`
`
`
`
`
`
`
`considered as being part of the disclosure of the accompanying application and is
`
`
`
`
`
`hereby incorporated by reference therein.
`
`
`
`Related Applications:
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`This application is a continuation of and claims priority to U.S. Patent Application No.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`12/541,299, filed August 14, 2009, which is a continuation of and claims priority to U.S.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Patent Application Serial No. 12/082,073, filed on April 7, 2008, which is a continuation of
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`and claims priority to U.S. Patent Application Serial No. 10/526,595, filed on January 9,
`
`
`
`
`
`
`
`
`
`
`
`
`2006, which was the National Stage of International Application Serial No. PCT/EP03/38599,
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`filed on September 8, 2003, which claims benefit of and priority to German Patent
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Application Serial No. DE 102 41 812.8, filed on September 6, 2002, the entire contents of
`
`
`
`
`
`
`
`
`
`
`
`
`each of which are expressly incorporated in the accompanying application by reference
`
`thereto.
`
`
`Page 1
`
`
`
`INTEL- 1004
`Page 1 of 539
`
`INTEL - 1004
`Page 1 of 539
`
`

`

`
`
`4.
`
`
`
`
`
`
`
`
`
`
`
`The filing fee has been calculated as shown below:
`
`
`RO]
`
`FILING FEES
`
`
`
`
`
`
`
`EXAMINATION FEE
`
`
`
`
`SEARCH FEE
`
`
`
`
`
`
`
`
`
`
`220.00
`
`
`
`
`
`
`1,090.00
`
`
`
`
`
`
`
`
`
`TOTAL BASIC, EXAM AND SEARCH FEES
`NUMBER
`
`
`
`
`
`
`
`
`
` .|
`
`
`
`
`
`
`
`|__sao.|
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`\#Additional fee for specification and drawingsfiled in paper over 100 sheets (excluding sequencelisting or
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`computer program listing fited in an electronic medium). The fee is $250 for each additional 50 sheets of paper
`or fraction thercof.
`
`
`
`
`
`
`
`
`Total Sheets[ExtraSheets|NumberEwa[__RATES
`
`
`
`
`
`
`
`
`
`
`
`
`
`(50 et x $250.00
`
`
`
`
`
`
`
`
`TOTAL FEES =
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`805.00 (722.00
`If the applicant is a small entity under 37 C.F.R. §§ 1.9
`SMALL ENTITY
`and 1.27, then divide total fee by 2, and enter amounthere.
`TOTAL
`L
`ife-filing)
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`5.
`
`
`
`520.00
`
`
`
`0.90
`
`
`
`520.00
`
`
`
`
`
`
`TOTAL CLAIMS
`
`
`
`
`
`INDEPENDENT CLAIMS
`
`
`
`
`
`
`
`
`30
`10
`
`52.00
`
`
`
`1
`
`
`
`
`
`
`0
`
`
`220.00
`
`
`
`MULTIPLE DEPENDENT CLAIM PRESENT
`
`
`
`
`
`
`
`
`
`
`TOTAL CLAIMS FEES
`
`
`
`390.00
`
`
`
`
`
`fone
`
`L
`
`1610.00
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`The required application filing fee and claim fees of $805.00 ($722.00 for e-filing) is
`
`
`
`
`
`being paid by credit card.
`
`
`
`
`
`
`
`
`
`
`
`Dated: July 14, 2010
`
`
`
`
`
`Customer No.: 26646
`
`
`
`
`Respectfully submitted,
`
`
`
`
`
`
`
`By:_/Aaron Grunberger/
`
`
`Aaron Grunberger
`
`
`
`Reg. No. 59,210
`
`
`
`
`
`
`
`KENYON & KENYON
`
`
`One Broadway
`
`
`
`
`New York, New York 10004
`
`
`
`(212) 425-7200 (telephone)
`
`
`
`(212) 425-5288 (facsimile)
`
`
`
`Page 2
`
`
`
`INTEL- 1004
`Page 2 of 539
`
`INTEL - 1004
`Page 2 of 539
`
`

`

`
`
`10
`
`
`
`15
`
`
`
`20
`
`
`
`25
`
`
`
`
`
`
`RECONFIGURABLE SEQUENCER STRUCTURE
`
`[2885/1339]
`
`
`
`Description
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`The present invention relates to a cell element field anda
`
`
`
`
`
`
`
`
`method for operating same. The present invention thus relates
`
`
`
`
`
`
`in particular to reconfigurable data processing architectures.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`The term reconfigurable architecture is understood to refer to
`
`
`
`
`
`
`
`
`
`units (VPUs) having a plurality of elements whose function
`
`
`
`
`
`
`
`
`and/or interconnection is variable during run time. These
`
`
`
`
`
`
`
`
`elements may include arithmetic logic units, FPGA areas,
`
`
`
`
`
`
`
`input/output cells, memory cells, analog modules, etc. Units
`
`
`
`
`
`
`
`
`
`
`
`
`of this type are known by the term VPU, for example. These
`
`
`
`
`
`
`
`typically include arithmetic and/or logic and/or analog and/or
`
`
`
`
`
`
`memory and/or interconnecting modules and/or communicative
`
`
`
`
`
`
`
`
`(10s),
`peripheral modules
`typically referred to as PAEs, which
`
`
`
`
`
`
`
`
`
`
`are arranged in one or more dimensions and are linked together
`
`
`
`
`
`
`
`
`
`
`
`
`directly or by one or more bus systems. PAES are arranged in
`
`
`
`
`
`
`
`
`any configuration, mixture and hierarchy,
`the system being
`
`
`
`
`
`
`
`
`
`
`
`
`Known as a PAB array or, for short, a PA. A configuring unit
`
`
`
`
`
`
`
`
`
`
`
`
`may be assigned to the PAE.
`In addition to VPU units,
`
`
`
`
`
`principle systolic arrays, neural networks, multiprocessor
`
`
`
`
`
`
`systems, processors having multiple arithmetic units and/or
`
`
`
`
`
`
`
`
`logic cells,
`interconnection and network modules such as
`
`
`
`
`
`
`
`
`crossbar circuits, etc., as well as FPGAs, DPGAs,
`
`
`
`
`etc., are also known
`
`in
`
`
`
`
`
`transputers,
`
`
`
`
`
`
`
`
`
`
`
`
`
`It should be pointed out that essential aspects of VPU
`
`
`
`
`
`
`
`
`technology are described in the following protective rights of
`
`
`
`
`
`
`
`
`
`
`the same applicant as well as in the particular follow-up
`
`
`
`
`
`
`
`applications to the protective rights listed here:
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`P 44 16 881.0-53, DE 197 81 412.3, DE 197 81 483.2,
`
`
`
`
`
`
`
`
`
`
`
`DE 196 54 846.2-53, DE 196 54 593.5-53, DE 197 04 044.6-53,
`
`
`
`
`
`NYO1 1974077 v1
`
`
`
`
`
`INTEL- 1004
`Page 3 of 539
`
`INTEL - 1004
`Page 3 of 539
`
`

`

`
`
`10
`
`
`
`15
`
`
`
`20
`
`
`
`25
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`DE 198 80 129.7, DE 198 61 088.2-53, DE 199 80 312.9,
`
`
`
`
`
`
`
`
`
`PCT/DE 00/01869, DE 100 36 627.9-33, DE 100 28 397.7,
`
`
`
`
`
`
`
`
`
`
`DE 101 10 530.4, DE 101 11 014.6, PCT/EP 00/10516,
`
`
`
`
`
`
`
`
`
`
`
`
`EP 01 102 674.7, DE 102 06 856.9, 60/317,876, DE 102 02 044.2,
`
`
`
`
`
`
`
`
`DE 101 29 237.6-53, DE 101 39 170.6.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`It should be pointed out that the documents listed above are
`
`
`
`
`
`
`
`
`incorporated in particular with regard to particulars and
`
`
`
`
`
`
`details of the interconnection, configuration, embodiment of
`
`
`
`
`
`
`architecture elements,
`trigger methods, etc., for disclosure
`
`
`purposes.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`The architecture has considerable advantages in comparison
`
`
`
`
`
`
`
`with traditional processor architectures inasmuch as data
`
`
`
`
`
`
`
`
`processing is performed in a manner having a large proportion
`
`
`
`
`
`
`
`
`of parallel and/or vectorial data processing steps. However,
`
`
`
`
`
`
`
`
`
`the advantages of this architecture in comparison with other
`
`
`
`
`
`
`
`
`processor units, coprocessor units or data processing units in
`
`
`
`
`
`
`
`
`
`general are not as great when the advantages of
`
`
`
`
`
`
`
`interconnection and of the given processor architectonic
`
`
`
`
`
`
`
`
`
`particulars are no longer achievable to the full extent.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`This is the case in particular when data processing steps that
`
`
`
`
`
`
`
`
`are traditionally best mappable on sequencer structures are to
`
`
`
`
`
`
`
`
`
`
`be executed. It is desirable to design and use the
`
`
`
`
`
`
`
`
`
`reconfigurable architecture in such a way that even those data
`
`
`
`
`
`
`
`processing steps which are typically particularly suitable for
`
`
`
`
`
`
`
`being executed using sequencers are executable particularly
`
`
`
`rapidly and efficiently.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`The object of the present invention is to provide a novel
`
`
`
`
`
`
`
`
`device and a novel method for commercial application.
`
`
`
`
`
`
`
`
`
`
`
`The method of achieving this object is claimed independently.
`
`
`
`
`
`
`
`Preferred embodiments are characterized in the subclaims.
`
`
`
`30
`
`
`
`NYOL 1974077 v1
`
`
`
`
`
`
`2
`
`INTEL- 1004
`Page 4 of 539
`
`INTEL - 1004
`Page 4 of 539
`
`

`

`
`
`
`
`
`
`
`
`
`According to a first essential aspect of the present
`
`
`
`
`
`
`
`
`
`
`in the case of a cell element field whose function
`
`
`
`
`
`
`and/or interconnection is reconfigurable in particular during
`
`invention,
`
`
`
`
`
`
`
`
`
`
`
`run time without interfering with unreconfigured elements for
`
`
`
`
`
`
`
`
`
`
`data processing with coarsely granular function cell elements
`
`
`
`
`
`
`
`
`
`
`
`in particular for execution of algebraic and/or logic
`
`
`
`
`
`
`
`
`functions and memory cell means for receiving, storing and/or
`
`
`
`
`
`10
`
`
`
`15
`
`
`
`20
`
`
`
`25
`
`
`
`30
`
`
`
`
`
`
`
`
`
`
`outputting information, it is proposed that function cell-
`
`
`
`
`
`
`
`
`
`memory cell combinations be formed in which a control
`
`
`
`
`
`
`
`
`
`
`connection to the memory means is managed by the function cell
`
`
`
`
`
`
`
`
`
`means. This control connection is for making the address
`
`
`
`
`
`
`
`and/or data input/output from the memory controllable through
`
`
`
`
`
`
`
`
`
`the particular function cell,
`typically an ALU-PAE. It is thus
`
`
`
`
`
`
`
`
`
`possible to indicate, for example, whether the next
`item of
`
`
`
`
`
`
`
`
`
`
`information transmitted is to be handled as an address or as
`
`
`
`
`
`
`
`
`
`
`
`
`data and whether read and/or write access is necessary. This
`
`
`
`
`
`
`
`
`
`transfer of data from the memory cell, i.e., the memory cell
`
`
`
`
`
`
`
`
`
`
`
`
`to the function
`
`
`then makes
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`means, which may be a RAM-PAE, for example,
`
`
`
`
`
`
`
`
`cell means, which may be an ALU-PAE, for example,
`
`
`
`
`
`
`
`
`
`
`
`it possible for new commands that are to be executed by the
`
`
`
`
`
`
`
`
`
`
`
`ALU to be loadable into the latter. It should be pointed out
`
`
`
`
`
`
`
`
`
`
`that function cell means and memory cell means may be combined
`
`
`
`
`
`
`
`
`
`In such a case it is
`by integration into a structural unit.
`
`
`
`
`
`
`
`
`
`
`
`possible to use a single bus connection to input data into the
`
`
`
`
`
`
`
`
`
`memory cell means and/or the ALU. Suitable input registers
`
`
`
`
`
`
`
`
`
`and/or output registers may then be provided and, if desired,
`
`
`
`
`
`
`additional data registers and/or configuration registers
`
`
`
`
`
`
`
`
`
`
`different from the former may also be provided as memory cell
`means.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`It should also be pointed out that it is possible to construct
`
`
`
`
`
`
`
`
`
`a cell element field containing a plurality of different cells
`
`
`
`
`
`
`
`
`
`and/or cell groups, strips or similar regular patterns being
`
`
`
`
`
`
`
`
`preferably provided with the different cells because these
`
`
`
`
`WYO1l 1974077 v1
`
`
`
`
`
`3
`
`
`INTEL- 1004
`Page 5 of 539
`
`INTEL - 1004
`Page 5 of 539
`
`

`

`
`
`10
`
`
`
`15
`
`
`
`20
`
`
`
`25
`
`
`
`30
`
`
`
`
`
`
`
`
`
`
`permit a very regular arrangement while facilitating the
`
`
`
`
`
`
`
`
`
`design equally in terms of hardware design and operation. With
`
`
`
`
`
`
`
`
`
`
`such a strip-like arrangement or other regular layout of a
`
`
`
`
`
`
`
`
`small plurality of different cell elements, for example,
`
`
`
`
`
`
`elements having integrated function cell means-memory cell
`
`
`
`
`
`
`
`
`means combinations, i.e., cells in which function cell means
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`and memory cell means are integrated according to the present
`
`
`
`
`
`
`
`
`invention, are provided centrally in the field, where
`
`
`
`
`
`
`
`
`
`typically only a few different program steps are to be
`
`
`
`
`
`
`
`executed within a sequencer structure because, as has been
`
`
`
`
`
`
`
`this provides very good results for traditional
`recognized,
`
`
`
`
`
`
`
`data stream applications, while more complex sequencer
`
`
`
`
`
`
`
`
`
`
`structures may be constructed at the edges of the field where,
`
`
`
`
`
`
`
`
`
`for example, an ALU-PAE which represents a separate unit
`
`
`
`
`
`
`
`
`
`possibly may be provided in addition to a separate RAM-~PAE and
`
`
`
`
`
`
`
`optionally a number of I/0O-PAES using, i.e., arranging
`
`
`
`
`
`
`appropriate control lines or connections thereof because
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`to temporarily
`frequently more memory is needed there, e.g.,
`
`
`
`
`
`
`
`
`
`
`store results generated in the field central area of the cell
`
`
`
`
`
`
`element field and/or for datastreaming,
`to pre-enter and/or
`
`
`
`
`process data needed thereby.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`When cells that integrate memory cell means and function cell
`
`
`
`
`
`
`
`
`
`
`
`means are provided, e.g.,
`in the center of the field, a small
`
`
`
`
`
`
`
`
`
`
`memory may then be provided there for different commands to be
`
`
`
`
`
`
`
`
`
`
`
`
`executed by the function cell means such as the ALU. It is
`
`
`
`
`
`
`
`
`
`possible here in particular to separate the command memory
`
`
`
`
`
`
`
`
`
`
`and/or the configuration memory from a data memory, and it is
`
`
`
`
`
`
`
`
`
`
`
`possible to design the function memory to be so large that
`
`
`
`
`
`
`
`alternatively, one of several, e.g.,
`two different sequences
`
`
`
`
`
`
`
`
`
`
`may be executed. The particular sequence to be executed may
`
`
`
`
`
`
`
`
`
`
`occur in response to results generated in the cell and/or
`
`
`
`
`
`
`
`
`control signals such as carry signals, overflow signals,
`
`
`
`
`
`
`
`
`
`and/or trigger signals arriving from the outside.
`In this way,
`
`
`
`
`
`
`
`
`
`
`
`
`NYO1L 1974077 vi
`
`
`
`
`
`4
`
`
`INTEL- 1004
`Page 6 of 539
`
`INTEL - 1004
`Page 6 of 539
`
`

`

`
`
`
`
`
`
`
`
`this arrangement may also be used for wave reconfiguration
`
`
`methods.
`
`
`
`In this way it is possible to construct a sequencer structure
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`in a cell element field by providing a dedicated control
`
`
`
`
`
`
`
`connection controlled by function cells in a dedicated manner
`
`
`
`
`
`
`
`
`
`between function cell and function cell means and memory cell
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`and/or memory cell means with only two elements connected by
`
`
`
`
`
`
`
`suitable buses without requiring additional measures and/or .
`
`
`
`
`
`
`
`design changes otherwise. Data, addresses, program steps,
`
`
`
`
`
`
`
`
`
`
`
`etc., may be stored in the memory cell in a manner known per
`se from traditional processors. Since both elements, if
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`properly configured, may also be used in another way,
`this
`
`
`
`
`
`
`
`yields a particularly efficient design which is particularly
`
`
`
`
`
`
`
`
`adaptable to sequencer structures as well as vectorial and/or
`
`
`
`
`
`
`parallelizable structures. Parallelization may thus be
`
`
`
`
`
`
`
`supported merely via suitable PAE configurations, i.e., by
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`providing PAEs that operate in two different spatial
`
`
`
`
`
`
`
`
`
`
`
`directions and/or via cell units equipped with data throughput
`
`
`registers.
`
`
`
`10
`
`
`
`15
`
`
`
`20
`
`
`
`25
`
`
`
`30
`
`
`
`
`
`
`
`
`
`
`
`
`
`Tt is clear here that a plurality of sequencer type structures
`
`
`
`
`
`
`
`
`
`may be constructed in the reconfigurable cell element field by
`
`
`
`
`
`
`
`
`
`
`using only two cells in a cell element field, namely the
`
`
`
`
`
`
`
`
`function cell and the information processing cell. This is
`
`
`
`
`
`
`
`
`
`advantageous inasmuch as a number of different tasks that are
`
`
`
`
`
`
`
`
`
`
`
`different from one another per se must often be executed in
`
`
`
`
`
`
`data processing, e.g.,
`in a multitasking-capable operating
`
`
`
`
`
`
`
`
`
`
`system. A plurality of such tasks must then be executed
`
`
`
`
`
`
`
`effectively and simultaneously in a single cell element field.
`
`
`
`
`
`
`
`
`The advantages of real time applications are obvious.
`
`
`
`
`
`
`
`
`Furthermore it is also possible to operate the individual
`
`
`
`
`
`
`
`sequencer structures that are constructed in a cell element
`
`
`
`
`
`
`
`
`field, providing the control connection according to the
`
`
`
`
`
`
`
`
`present invention, at different clock rates, e.g.,
`to lower
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`NYO1 1974077 vi
`
`
`
`
`
`5
`
`
`INTEL- 1004
`Page 7 of 539
`
`INTEL - 1004
`Page 7 of 539
`
`

`

`
`
`
`
`
`
`
`
`power consumption by executing lower priority tasks at a
`
`
`
`
`
`
`
`
`
`slower rate. It is also possible to execute sequencer type
`
`
`
`
`
`
`
`
`
`
`program parts in the field in parallel or vectorially in
`
`
`
`
`
`
`
`
`
`
`
`
`execution of algorithms that are largely parallel per se and
`
`
`
`
`
`
`vice versa.
`
`
`
`
`
`
`
`
`
`
`
`Typically, however, it is preferable for sequencer-type
`
`
`
`
`
`
`
`
`
`
`
`structures to be clocked at a higher rate in the cell element
`
`
`
`
`
`
`
`
`field, whether they are sequencer-type structures having an
`
`
`
`
`
`
`
`
`
`area connected to neighboring cells or buses or whether they
`
`
`
`
`
`
`
`are combinations of spatially differentiable separate and
`
`
`
`
`
`
`
`
`separately useable function cell elements such as ALU-PAEs and
`
`
`
`
`
`
`
`
`
`
`memory cell elements such as RAM-PAEsS. This has the advantage
`
`
`
`
`
`
`
`
`
`that sequential program parts, which are very difficult to
`
`
`
`
`
`
`
`
`
`
`parallelize in any case, may be used in a general data flow
`
`
`
`
`
`
`
`
`
`processing without any negative effect on the overall data
`
`
`
`
`
`
`
`
`processing. Examples of this include, e.g., a HUFFMANN coding
`
`
`
`
`
`
`
`
`
`
`
`LO
`
`
`
`L5
`
`
`
`20
`
`
`
`
`
`
`
`
`
`
`
`which is executable much better sequentially than in parallel
`
`
`
`
`
`
`
`
`
`
`and which also plays an important role for applications such
`
`
`
`
`
`
`
`
`
`
`
`as MPEG4 coding, but
`in this case the essential other parts of
`
`
`
`
`
`
`
`
`the MPEG4 coding are also easily parallelizable. Parallel data
`
`
`
`
`
`
`
`
`
`
`
`
`processing is then used for most parts of an algorithm anda
`
`
`
`
`
`
`
`
`sequential processing block is provided therein. An increase
`
`
`
`
`
`
`
`
`
`
`
`
`in the clock frequency in the sequencer range by a factor of 2
`
`
`
`
`
`to 4 is typically sufficient.
`
`
`
`
`
`
`
`
`25
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`It should be pointed out that instead of a strip arrangement
`
`
`
`
`
`
`
`
`of different cell elements, another grouping,
`in particular a
`
`
`
`
`
`
`multidimensional grouping, may also be selected.
`
`
`
`
`
`
`
`
`
`
`The cell element field having the cells whose function and/or
`
`
`
`
`
`
`
`interconnection is configurable may obviously form a
`
`
`
`30
`
`
`
`
`
`
`
`
`
`
`
`processor, a coprocessor and/or a microcontroller and/or a
`
`
`
`
`
`parallel plurality of combinations thereof.
`
`NYQ1 1974077 v1
`
`
`
`
`
`6
`
`
`INTEL- 1004
`Page 8 of 539
`
`INTEL - 1004
`Page 8 of 539
`
`

`

`
`
`10
`
`
`
`15
`
`
`
`20
`
`
`
`25
`
`
`
`30
`
`
`
`
`
`
`
`
`
`
`
`The function cells are typically formed as arithmetic logic
`
`
`
`
`
`
`
`
`
`units, which may be in particular coarsely granular elements
`
`
`
`
`
`
`
`
`
`
`
`but may also be provided with a fine granular state machine,
`
`
`
`
`
`
`
`for example.
`In a particularly preferred exemplary embodiment,
`
`
`
`
`
`
`
`
`
`
`the ALUs are extended ALUs
`(EALUs) as described in previous
`
`
`
`
`
`
`
`
`patent applications of the present applicant. An extension may
`
`
`
`
`
`
`
`
`
`inckude in particular the control line check, command decoder
`
`
`
`
`unit, etc., if necessary.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`The memory cells may store data and/or information ina
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`volatile and/or nonvolatile form. When information stored in
`
`
`
`
`
`
`
`
`the memory cells, whether program steps, addresses for access
`to data or data stored in a register-type form, i.e., a heap
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`is stored as volatile data, a complete reconfiguration may
`
`
`
`
`
`
`
`
`
`take place during run time. Alternatively it is possible to
`
`
`
`
`
`
`
`provide nonvolatile memory cells. The nonvolatile memory cells
`
`
`
`
`
`
`
`
`
`
`
`
`may be provided as an BEPROM area and the like, where a
`
`
`
`
`
`
`
`
`
`
`rudimentary BIOS program that is to be executed on boot-up of
`
`
`
`
`
`
`
`
`
`
`the system is stored. This permits booting up a data
`
`
`
`
`
`
`processing system without additional components. A nonvolatile
`
`
`
`
`
`
`
`
`
`
`
`
`data memory may also be provided if it is decided for reasons
`
`
`
`
`
`
`
`
`
`
`
`of cost and/or space that the same program parts are always to
`
`
`
`
`
`
`
`
`
`
`be executed repeatedly, and it is also possible to alternate
`
`
`
`
`
`
`
`
`
`among such fixed program parts during operation, e.g.,
`in the
`
`
`
`
`
`
`
`
`manner of a wave reconfiguration. The possibilities of
`
`
`
`
`
`
`
`
`providing and using such nonvolatile memories are the object
`
`
`
`
`
`
`
`
`
`
`of other protective rights of the present applicant. It is
`
`
`
`
`
`
`
`
`
`possible to store both volatile and nonvolatile data in the
`
`
`
`
`
`
`
`
`
`memory cells, e.g., for permanent storage of a BIOS program,
`
`
`
`
`
`
`
`
`
`
`
`and nevertheless be able to use the memory cell for other
`
`
`purposes.
`
`
`
`
`
`
`
`
`
`
`
`
`
`The memory cell is preferably designed to be able to store a
`
`
`
`
`
`
`
`
`
`sufficient variety of data to be executed and/or program parts
`
`
`
`
`
`
`
`
`
`
`
`to be executed. It should be pointed out here that these
`
`
`
`NYOL 1974077 v1
`
`
`
`
`
`
`7
`
`INTEL- 1004
`Page 9 of 539
`
`INTEL - 1004
`Page 9 of 539
`
`

`

`
`
`10
`
`
`
`15
`
`
`
`20
`
`
`
`25
`
`
`
`30
`
`
`
`
`
`
`
`
`
`
`
`
`program parts may be designed as program steps, each
`
`
`
`
`
`
`
`
`specifying what an individual PAE,
`in particular the assigned
`
`
`
`
`
`
`
`
`
`PAE, i.e.,
`in particular the function cell controlling the
`
`
`
`
`
`
`
`
`
`
`
`
`
`memory cell,
`is to do in the next step, and they may also
`
`
`
`
`
`
`
`
`include entire configurations for field areas or other fields.
`
`
`
`
`
`
`
`
`
`
`
`In such a case, it is readily possible for the sequencer
`
`
`
`
`
`
`
`
`
`
`
`structure that has been created to issue a command on the
`
`
`
`
`
`
`
`
`
`basis of which cell element field areas are reconfigured. The
`
`
`
`
`
`
`
`
`
`function cell triggering this configuration then operates as a
`
`
`
`
`
`
`
`
`
`
`
`
`
`load logic at the same time. It should be pointed out that the
`
`
`
`
`
`
`
`
`
`
`configuration of other cells may in turn be accomplished in
`
`
`
`
`
`
`
`
`
`
`such a way that sequencer type data processing is performed
`
`
`
`
`
`
`
`
`
`
`
`there and it is in turn possible in these fields to configure
`
`
`
`
`
`
`
`
`
`and/or reconfigure other cells in the course of program
`
`
`
`
`
`
`
`[execution]. This results in an iterative configuration of
`
`
`
`
`
`
`
`
`cell element areas, and nesting of programs having sequencer
`
`
`
`
`
`
`
`these
`structures and parallel structures is possible,
`
`
`
`
`
`
`
`
`structures being nested one inside the other like babushka
`
`
`
`
`
`
`
`
`
`
`dolls. It should be pointed out that access to additional cell
`
`
`
`
`
`
`
`
`
`element fields outside of an individual integrated module is
`
`
`
`
`
`
`
`
`possible through input/output cells in particular, which may
`
`
`
`
`
`
`
`
`massively increase the total computation performance. It is
`
`
`
`
`
`
`
`
`possible in particular when configurations occur in a code
`
`
`
`
`
`
`
`
`
`part of a sequencer structure configured into a cell element
`
`
`
`
`
`
`
`field to perform,
`if necessary,
`the configuration requirements
`
`
`
`
`
`
`
`
`
`
`
`on an assigned cell element field which is managed only by the
`
`
`
`
`
`
`
`particular sequencer structure and/or such requirements may be
`
`
`
`
`
`
`
`
`
`
`issued to a configuration master unit to ensure that there is
`
`
`
`
`
`
`
`
`
`uniform occupancy of all cell element fields. This therefore
`
`
`
`
`
`
`
`results in a quasi-subprogram call by transferring the
`
`
`
`
`
`
`
`
`required configurations to cells or load logics. This is
`
`
`
`
`
`
`
`
`regarded as independently patentable. It should be pointed out
`
`
`
`
`
`
`
`
`
`that the cells,
`if they themselves have responsibility for
`
`
`
`
`
`
`
`
`
`configuration of other cell element field areas, may be
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`NYO1 1974077 v1
`
`
`
`
`8
`
`INTEL- 1004
`Page 10 of 539
`
`INTEL - 1004
`Page 10 of 539
`
`

`

`
`
`
`
`
`
`
`
`provided with FILMO structures and the like implemented in
`
`
`
`
`
`
`
`hardware or software to ensure proper reconfiguration. The
`
`
`
`
`
`
`
`
`
`
`
`possibility of writing to memory cells while executing
`
`
`
`
`
`
`
`
`thereby altering the code, i.e.,
`the program to
`instructions,
`
`
`
`
`
`
`
`
`be executed, should be pointed out.
`In a particularly
`
`
`
`
`
`
`
`
`
`preferred variant, however,
`
`
`
`
`
`
`
`is suppressed by appropriate control via the function
`
`
`
`(SM)
`
`cell.
`
`
`
`
`
`
`this type of self-modification
`
`
`
`
`
`
`
`
`
`
`
`It is possible for the memory cell to send the information
`
`
`
`
`
`
`
`
`
`
`stored in it directly or indirectly to a bus leading to the
`
`
`
`
`
`
`
`
`
`function cell in response to the triggering of the function
`
`
`
`
`
`
`
`
`cell controlling it. Indirect output may be accomplished in
`
`
`
`
`
`
`
`
`
`particular when the two cells are adjacent and the information
`
`
`
`
`
`
`
`
`
`
`
`requested by the triggering must arrive at the ALU-PAE via a
`
`
`
`
`
`
`
`
`
`
`bus segment that is not directly connectable to the output of
`
`
`
`
`
`
`
`
`
`
`
`
`the memory cell.
`In such a case the memory cell may output
`
`
`
`
`
`
`
`
`
`data onto this bus system in particular via backward
`
`registers. It is therefore preferable if at least one* memory
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`cell and/or function cell has such a backward register, which
`
`
`
`
`
`
`
`
`
`may be situated in the information path between the memory
`
`
`
`
`
`
`
`
`
`
`cell and function cell.
`In such a case,
`these registers need
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`10
`
`
`
`15
`
`
`
`20
`
`
`
`25
`
`
`
`
`
`
`
`
`
`not necessarily be provided with additional functionalities,
`
`
`
`
`
`
`
`
`
`although this is readily conceivable, e.g., when data is
`
`
`
`
`
`
`
`
`requested from the memory cell for further processing,
`
`
`
`
`
`
`
`corresponding to a traditional LOAD of a typical
`
`
`
`
`
`
`
`
`
`microprocessor for altering the data even before it is loaded
`
`
`
`
`
`to implement a LOAD++ command. Data
`
`
`
`
`into the PAB, e.g.,
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`conduction through PARs having ALUs and the like operating in
`
`
`
`
`
`
`
`
`the reverse direction should be mentioned.
`
`
`
`30
`
`
`
`
`
`
`
`
`
`
`
`The memory cell is preferably situated to receive information
`
`
`
`
`
`
`
`
`from the function cell controlling it,
`information saving via
`
`
`
`
`
`
`
`
`
`
`1 TN: omitting "von" (eine von Speicherzelle..)
`
`
`
`N¥O1 1974077 v1
`
`
`
`
`
`3
`
`
`
`INTEL - 1004
`Page 11 of 539
`
`INTEL - 1004
`Page 11 of 539
`
`

`

`
`
`
`
`
`
`
`
`
`
`an input/output cell and/or a cell that does not control the
`
`
`
`
`
`In particular when data is to
`
`
`
`
`
`memory cell also being possible.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`be written into the memory cell from an input/output cell, it
`
`
`
`
`
`
`
`is preferable if this input/output cell
`is also
`
`(I/O-PAE)
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`controlled by the function cell. The address at which
`
`
`
`
`
`
`
`
`information to be written into the memory cell or,
`
`if
`
`
`
`
`
`
`necessary,
`
`cell
`
`
`
`(PAE)
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`to also be transmitted directly to the function
`
`
`
`
`
`
`
`
`
`
`is to be read, may also be transferred to the I/0-
`
`
`
`
`
`
`
`
`
`
`In this connection it should be pointed
`PAE from the ALU-PAE.
`
`
`
`
`
`
`
`
`
`
`out that this address may be determined via an address
`
`
`
`
`
`
`
`
`
`translation table, an address translation buffer or an MMU
`
`
`
`
`
`
`
`
`
`In such a case,
`type structure in the I/O-PAF.
`this yields the
`
`
`
`
`
`
`
`full functionalities of typical microprocessors. It should
`
`
`
`
`
`
`
`
`
`
`
`also be pointed out that an I/O functionality may also be
`
`
`
`
`
`
`
`
`
`integrated with a function cell means, a memory cell means
`
`
`
`
`
`
`
`and/or a function cell means-memory cell means combination.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`10
`
`
`
`15
`
`
`
`20
`
`
`
`
`
`
`
`
`
`
`
`
`In a preferred variant, at least one input-output means is
`
`
`
`
`
`
`
`
`
`
`
`
`thus assigned to the combination of function cells and memory
`
`
`
`
`
`
`
`
`
`cells, whether as an integrated function cell and a memory
`
`
`
`
`
`
`
`
`
`cell combination or as a function cell and/or memory cell
`
`
`
`
`
`
`
`
`
`
`
`
`
`the input/output means
`combination composed of separate units,
`
`
`
`
`
`
`
`
`being used to transmit information to and/or receive
`
`
`
`
`
`
`
`information from an external unit, another function cell,
`
`
`
`
`
`
`
`function cell memory cell combination and/or memory cells.
`
`
`
`
`
`
`
`
`
`25
`
`
`
`
`
`
`
`
`
`
`The input-output unit is preferably likewise designed for
`
`
`
`
`
`
`
`
`receiving control commands from the function cell and/or the
`
`
`
`
`
`
`
`function cell means.
`
`
`
`
`
`
`In a preferred variant,
`
`
`
`
`
`
`
`
`the control connection is designed to
`
`
`
`
`
`
`
`
`transmit some and preferably all of the following commands:
`
`
`
`
`
`
`30
`
`
`OPCODE FETCH,
`
`
`
`
`
`DATA WRITE INTERNAL,
`
`
`
`DATA WRITE EXTERNAL
`
`
`
`NY¥O1 1974077 v1
`
`
`
`
`
`10
`
`
`
`INTEL- 1004
`Page 12 of 539
`
`INTEL - 1004
`Page 12 of 539
`
`

`

`
`
`
`
`
`
`
`
`INTERNAL,
`
`
`
`
`STACK POINTER WRITE INTERNAL,
`STACK POINTER WRITE EXTERNAL,
`
`
`
`
`
`
`STACK POINTER READ.
`
`
`
`STACK POINTER READ EXTERNAL,
`
`
`
`
`DATA READ EXTERNAL,
`
`
`
`
`ADDRESS
`
`ADDRESS
`
`
`ADDRESS
`
`ADDRESS
`
`
`PROGRAM
`
`PROGRAM
`
`
`PROGRAM
`
`
`PROGRAM
`
`POINTER
`
`POINTER
`
`POINTER
`
`POINTER
`
`POINTER
`
`POINTER
`
`POINTER
`
`POINTER
`
`
`
`
`
`
`
`
`
`
`
`
`WRITE INTERNAL,
`
`WRITE EXTERNAL,
`
`
`
`
`
`READ INTERNAL,
`
`READ EXTERNAL,
`
`
`
`
`
`
`WRITE INTERNAL,
`
`
`WRITE EXTERNAL,
`
`
`
`
`
`READ INTERNAL,
`
`READ EXTERNAL,
`
`
`
`
`
`
`10
`
`
`
`PUSH,
`
`15
`
`
`
`POP,
`
`
`
`
`
`PROGRAM POINTER INCREMENT .
`
`
`
`20
`
`
`
`25
`
`
`
`
`
`
`
`
`
`
`
`
`This may be accomplished through a corresponding bit width of
`
`
`
`
`
`
`
`
`
`
`the control line and an associated decoding at the receivers.
`
`
`
`
`
`
`
`
`
`The particular required control means and decoding means may
`
`
`
`
`
`
`
`
`
`
`
`be provided inexpensively and with no problems. As it shows, a
`
`
`
`
`
`
`
`practically complete sequencer capability of the arrangement
`
`
`
`
`
`
`
`
`
`
`is obtained with these commands. It should also be pointed out
`
`
`
`
`
`
`
`that a general-purpose processor data processing unit is
`
`
`
`
`obtained in this way.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`The system is typically selected so that the function cell is
`
`
`
`
`
`
`
`
`
`
`
`the only one able to access the control connection and/or a
`
`
`
`
`
`
`
`
`bus segment, i.e., bus system functioning as the control
`
`
`
`
`
`
`
`
`
`
`
`connection as a master. The result is thus a system in which
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`the control line functions as a command line such as that
`
`
`
`provided in traditional processors.
`
`
`
`
`
`30
`
`
`
`
`
`
`
`
`
`
`
`
`
`I/O cell, are
`The function cell and the memory cell, i.e.,
`
`
`
`
`
`
`
`
`
`preferably adjacent to one another. The term "adjacent" may be
`
`
`
`
`
`NYO 1974077 vi
`
`
`
`
`
`11
`
`
`
`INTEL - 1004
`Page 13 of 539
`
`INTEL - 1004
`Page 13 of 539
`
`

`

`
`
`10
`
`
`
`15
`
`
`
`20
`
`
`
`25
`
`
`
`30
`
`
`
`
`
`
`
`
`
`
`
`understood preferably as the cells being situated directly
`
`
`
`
`
`
`
`
`side by side. "Directly" means in particular a combination of
`
`
`
`
`
`
`
`
`
`such cells to form integrated units which are provided
`
`
`
`
`
`
`
`
`
`
`
`repeatedly on the cell element field, i.e., as part of same to
`
`
`
`
`
`
`
`
`
`
`
`form the field. This may mean an integral unit of memory cells
`
`
`
`
`
`
`
`
`
`and logic cells. Alternatively,
`they are at least close
`
`
`
`
`
`
`
`
`
`
`together. The system of the function cells and memory cells in
`
`
`
`
`
`
`
`
`integrated, i.e., close, proximity to one another thus ensures
`
`
`
`
`
`
`
`
`
`
`
`that there are no latency times, or at least no significant
`
`
`
`
`
`
`
`
`
`latency times, between triggering and data input of the
`
`
`
`
`
`
`
`
`required information in the function cell, merely because the
`
`
`
`
`
`
`
`
`
`connections between the cells are too long. This is understood
`
`
`
`
`