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`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________________________________
`
`INTEL CORPORATION,
`Petitioner
`v.
`
`PACT XPP SCHWEIZ AG,
`Patent Owner
`
`DECLARATION OF DR. PINAKI MAZUMDER UNDER 37 C.F.R. § 1.68
`IN SUPPORT OF PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 7,928,763
`
`INTEL - 1001
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`Ex. 1001 - Declaration of Dr. Mazumder
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`TABLE OF CONTENTS
`
`I.
`II.
`
`Page
`Introduction ...................................................................................................... 1
`Background and Qualifications ....................................................................... 3
`A.
`Educational Background ....................................................................... 3
`B.
`Career Background ................................................................................ 6
`C.
`Relevant Publications ............................................................................ 9
`D.
`Patents.................................................................................................. 13
`III. Understanding of Patent Law ........................................................................ 15
`IV. Background .................................................................................................... 18
`A.
`Technology Background ..................................................................... 18
`1.
`Processors (Generally) .............................................................. 18
`2. Multiprocessor Systems ............................................................ 21
`Summary of the ’763 patent ................................................................ 33
`1.
`The Alleged Problem in the Art ................................................ 33
`Summary of the Prosecution History .................................................. 35
`C.
`Level of Ordinary Skill in the Art ................................................................. 35
`V.
`VI. Claim Construction ........................................................................................ 37
`VII. Detailed Invalidity Analysis .......................................................................... 37
`A.
`Background on Prior Art References .................................................. 37
`1.
`Balmer ....................................................................................... 37
`2. Wilkinson .................................................................................. 39
`3. Miyamori ................................................................................... 40
`
`B.
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`Ex. 1001 - Declaration of Dr. Mazumder
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`B.
`
`4.
`Nicol .......................................................................................... 42
`Hennessy ................................................................................... 43
`5.
`Claims 1-3, 9-14, 16-20, 22, 24, 26, 30, 31-33, 39-44, 46-50,
`52, 54, 56, and 60 of the ’763 Patent Are Obvious In View Of
`Balmer ................................................................................................. 44
`1.
`Independent Claims 1 and 31 .................................................... 44
`2.
`Dependent Claims 2 and 32 ...................................................... 65
`3.
`Dependent Claims 3 and 33 ...................................................... 67
`4.
`Dependent Claims 9 and 39 ...................................................... 68
`5.
`Dependent Claims 10 and 40 .................................................... 70
`6.
`Dependent Claims 11 and 41 .................................................... 71
`7.
`Dependent Claims 12 and 42 .................................................... 72
`8.
`Dependent Claims 13 and 43 .................................................... 73
`9.
`Dependent Claims 14 and 44 .................................................... 73
`10. Dependent Claims 16 and 46 .................................................... 76
`11. Dependent Claims 17 and 47 .................................................... 78
`12. Dependent Claims 18 and 48 .................................................... 79
`13. Dependent Claims 19 and 49 .................................................... 80
`14. Dependent Claims 20 and 50 .................................................... 81
`15. Dependent Claims 22 and 52 .................................................... 83
`16. Dependent Claims 24 and 54 .................................................... 84
`17. Dependent Claims 26 and 56 .................................................... 86
`18. Dependent Claims 30 and 60 .................................................... 88
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`Ex. 1001 - Declaration of Dr. Mazumder
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`C.
`
`D.
`
`Claims 21 and 51 of the ’763 Patent Are Obvious In View of
`Balmer and Nicol ................................................................................. 89
`1.
`Dependent Claims 21 and 51 .................................................... 89
`Claims 1-3, 9-14, 16-22, 24, 26, 30, 31-33, 39-44, 46-52, 54,
`56, and 60 of the ’763 patent Are Obvious In View Of
`Wilkinson in combination with Hennessy .......................................... 93
`1.
`Independent Claims 1 and 31 .................................................... 93
`2.
`Dependent Claims 2 and 32 .................................................... 110
`3.
`Dependent Claims 3 and 33 .................................................... 111
`4.
`Dependent Claims 9 and 39 .................................................... 112
`5.
`Dependent Claims 10 and 40 .................................................. 113
`6.
`Dependent Claims 11 and 41 .................................................. 114
`7.
`Dependent Claims 12 and 42 .................................................. 115
`8.
`Dependent Claims 13 and 43 .................................................. 116
`9.
`Dependent Claims 14 and 44 .................................................. 116
`10. Dependent Claims 16 and 46 .................................................. 117
`11. Dependent Claims 17 and 47 .................................................. 118
`12. Dependent Claims 18 and 48 .................................................. 119
`13. Dependent Claims 19 and 49 .................................................. 119
`14. Dependent Claims 20 and 50 .................................................. 120
`15. Dependent Claims 22 and 52 .................................................. 120
`16. Dependent Claims 24 and 54 .................................................. 121
`17. Dependent Claims 26 and 56 .................................................. 122
`18. Dependent Claims 30 and 60 .................................................. 123
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`Ex. 1001 - Declaration of Dr. Mazumder
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`E.
`
`Claims 1-3, 9-14, 16-20, 22, 24, 26, 30, 31-33, 39-44, 46-50,
`52, 54, 56, and 60 of the ’763 Patent Are Obvious in View of
`Wilkinson in Combination with Hennessey and Miyamori .............. 125
`1.
`Independent Claims 1 and 31 .................................................. 125
`2.
`Dependent Claims 10-14 and 40-44 ....................................... 133
`3.
`Dependent Claims 2-3, 9, 16-20, 22, 24, 26, 30, 32-33,
`39, 46-50, 52, 54, 56, and 60 .................................................. 133
`4. Motivation to Combine Wilkinson and Hennessy with
`Miyamori ................................................................................. 133
`Dependent Claims 13 and 43 .................................................. 134
`5.
`Claims 21 and 51 of the ’763 Patent Are Obvious in View of
`Wilkinson in Combination with Hennessy, Nicol, and
`Miyamori ........................................................................................... 135
`1.
`Dependent Claims 21 and 51 .................................................. 135
`VIII. Secondary Considerations of Non-Obviousness ......................................... 138
`IX. Conclusion ................................................................................................... 138
`
`F.
`
`
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`Ex. 1001 - Declaration of Dr. Mazumder
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`I, Pinaki Mazumder, Ph.D., do hereby declare as follows:
`
`I.
`
`INTRODUCTION
`I have been retained as an expert witness on behalf of Intel Corporation
`1.
`
`(“Intel”) for the above-captioned Petition for Inter Partes Review (“IPR”) of U.S.
`
`Patent No. 7,928,763 (“’763 patent”). I am being compensated for my time in
`
`connection with this IPR at my standard consulting rate of $400 per hour. My
`
`compensation is not affected by the outcome of this matter.
`
`2.
`
`I have been asked to provide my opinions regarding whether or not
`
`Claims 1-3, 9-14, 16-22, 24, 26, 30-33, 39-44, 46-52, 54, 56, and 60 of the ’763
`
`patent (“the Challenged Claims”) would have been obvious to a person having
`
`ordinary skill in the art (henceforth, “POSITA”) at the time of the alleged invention
`
`based on prior art.
`
`3.
`
`In preparing this Declaration, I have reviewed the ’763 patent, the file
`
`histories of the ’763 patent, numerous prior art references, and technical references
`
`from the time of the alleged invention.
`
`4.
`
`The patent application that resulted in the ’763 patent, U.S. App. No.
`
`12/836,364 (the “’364 application”), was filed on July 14, 2010. Ex. 1001 (’763
`
`patent), Cover. The ’763 patent claiming priority, through multiple divisional and
`
`continuation patents, to German Patent Application Serial No. DE 102 41 812.8,
`
`filed on September 6, 2002. Id.
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`Ex. 1001 - Declaration of Dr. Mazumder
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`5.
`
`The only named inventor of the ’763 patent is Martin Vorbach Id. The
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`original assignee of the ’763 patent was PACT XPP TECHNOLOGIES AG. Id.
`
`6.
`
`For the purposes of my Declaration, I have been asked to assume that
`
`the priority date of the alleged invention recited in the ’763 patent is March 5, 2001.
`
`7.
`
`I understand that in Inter Partes Review (“IPR”) proceedings at the
`
`United States Patent and Trademark Office (“USPTO”), claims are given their
`
`ordinary and customary meaning in view of the patent specification and the
`
`understandings of one having ordinary skill in the relevant art.
`
`8.
`
`In forming the opinions expressed in my Declaration, I have relied upon
`
`my education and experience in the relevant field of the art, and I considered the
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`viewpoint of a person having ordinary skill in the relevant field of the art as of the
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`priority date of the ’763 patent. For the purposes of my Declaration, I have been
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`asked to assume that the priority date of the alleged invention recited in the ’763
`
`patent is September 6, 2002. My opinions are based, at least in part, on the following
`
`references:
`
`Reference
`United States Patent No. 5,197,140
`(“Balmer”)
`
`Date of Public Availability
`Filed: November 17, 1989
`Issued: March 23, 1993
`prior art under §§ 102(a), (b), and
`(e)
`
`2
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`Ex. 1001 - Declaration of Dr. Mazumder
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`Reference
`U.S. Patent No. 6,141,762 (“Nicol”)
`filed
`
`United States Patent No. 5,761,523
`(“Wilkinson”)
`
`T. Miyamori, A Quantitative
`Analysis of Reconfigurable
`Coprocessors for Multimedia
`Applications (“Miyamori”)
`
`John L. Hennessy & David A.
`Patterson, Computer Organization
`and Design: The Hardware/Software
`Interface (2d. ed. 1998)
`(“Hennessy”)
`
`Date of Public Availability
`Filed: August 3, 1998
`Issued: October 31, 2000
`prior art under 35 U.S.C. §§ 102(a),
`(b), and (e)
`
`Filed: June 23, 1982
`Published: February 16, 1983
`§§ 102(a), (b), (e)
`
`Published: April 17, 1998
`prior art under §§ 102(a) and (b)
`
`Published 1998
`prior art under §§ 102(a), (b)
`
`
`II. BACKGROUND AND QUALIFICATIONS
`9. My curriculum vitae (“CV”) is attached hereto as Ex. 1010 and
`
`provides an accurate identification of my background and experience.
`
`A. Educational Background
`I received my Bachelor of Science degree in Electrical Engineering
`10.
`
`from the Indian Institute of Science in Bangalore, India in 1976. I also received
`
`Bachelor of Science degree in Physics (Honors) from Guwahati University in India
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`in 1973, where I was the valedictorian across disciplines amongst approximately
`
`100,000 students.
`
`11.
`
`I received my Masters in Science degree in Computer Science from the
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`University of Alberta in Edmonton, Canada in 1985. My M.S. thesis related to
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`“Networks and Embedding Aspects of Hyper-cellular Structures for On-Chip
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`Parallel Processing.” The thesis evaluated different types of multiprocessing
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`architectures by developing a new VLSI asymptotic modeling technique and
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`demonstrated that meshes and torus class of interconnection topologies were most
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`suited for on-chip parallel processing. The thesis also developed cellular layout
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`techniques for placement and wiring of processors to embed fault-tolerant mesh
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`networks. The core cellular embedding technique was extended to describe planar
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`tessellation of quad-tree data-structures in computer vision, graphics and image
`
`processing.
`
`12.
`
`I continued on to receive my Ph.D. in Electrical and Computer
`
`Engineering from the University of Illinois in Urbana-Champaign, Illinois in 1988.
`
`My doctoral work focused on the semiconductor design of testable memory
`
`products, which were subsequently adopted and used in DRAM devices by several
`
`semiconductor memory manufacturers in the industry. Since that time, I have
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`secured 54 research grants amounting to nearly $54 million collectively from
`
`National Science Foundation, Air Force Office of Scientific Research, Office of
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`Naval Research, Army Research Office, Defense Advanced Research Projects
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`Agency, State of Michigan, and several private sources. These grants allowed me
`
`to perform research in areas including CMOS design tools, nano-circuit and nano-
`
`system design, testable designs for memories, and the use of ionic and/or spin-based
`
`devices as non-volatile memory.
`
`13.
`
`I was a recipient of Digital’s Incentives for Excellence Award, BF
`
`Goodrich National Collegiate Invention Award, and DARPA Research Excellence
`
`Award in 1999.
`
`14.
`
`I am a 2007 Fellow of American Association for the Advancement in
`
`Science (AAAS) for my “distinguished contributions to the field of very large scale
`
`integrated (VLSI) systems.” The honor of being elected a Fellow of AAAS is given
`
`to those whose “efforts on behalf of the advancement of science or its applications
`
`are scientifically or socially distinguished.”
`
`15.
`
`I am also a 1999 Fellow of IEEE for my “contributions to the field of
`
`VLSI Design.”
`
`16. Further, the IEEE Electron Devices Society recognized me as an IEEE
`
`Distinguished Lecturer. Part of this recognition stems from the fact that I have
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`presented over 100 invited talks at universities and companies around the world.
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`Ex. 1001 - Declaration of Dr. Mazumder
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`B. Career Background
`17. After my baccalaureate degrees in Physics and Electrical Engineering,
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`I worked for six years from 1976 to 1982 as a Senior R&D Engineer at Bharat
`
`Electronics Ltd. (“BEL”) in its Integrated Circuits Division. I designed several
`
`bipolar and CMOS analog and digital integrated circuits for consumer electronic
`
`systems. I was involved with the following chip development projects: (1) Raster-
`
`scan vertical deflection system microchip for TV display, (2) Sync processing and
`
`horizontal deflection system microchip for TV display, (3) Video and audio IF stage
`
`IC’s for vestigial-AM and FM signal detection in TV receiver, and (4) High-gain
`
`audio amplifier microchip for TV audio stage. Several million commercial chips
`
`were fabricated based on these designs.
`
`18. After finishing my M.S. degree in Computer Science and while
`
`working towards my Ph.D. degree in Electrical and Computer Engineering, I worked
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`during the summers of 1985 and 1986 as a member of the Technical Staff at AT&T
`
`Bell Laboratories. I was one of two engineers who started the Bell Laboratory
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`Cones/Spruce project, a new behavioral synthesis and layout automation tool for
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`rapid prototyping of digital circuits. The main contribution of this effort was to
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`demonstrate how a restricted version of the C programming language could be used
`
`to model digital hardware, long before engineers developed commercial hardware
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`description language (HDL) software tools like Verilog and System C.
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`19. Since finishing my Ph.D. from the University of Illinois at Urbana-
`
`Champaign in 1988, I have worked at the University of Michigan in the Department
`
`of Electrical Engineering and Computer Science, where I was promoted to the rank
`
`of a full professor in 1998. I have supervised 21 Ph.D. students and over 35 students
`
`studying for their M.S. in Electrical Engineering. I have also mentored 12
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`international undergraduate students and 12 visiting professors and postdocs in my
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`research group to foster global collaboration and outreach activities.
`
`20.
`
`I spent my sabbatical at Stanford University, University of California
`
`at Berkeley, and NTT Basic Research Laboratory in Japan in 1996 and 1997.
`
`21.
`
`In 2007 and 2008, I worked as the lead Program Director for the
`
`Emerging Models and Technologies (EMT) program in the Division of Computing
`
`and Communication Foundations of the Directorate for Computer and Information
`
`and Science and Engineering at the National Science Foundation (“NSF”) in
`
`Arlington, Virginia. My mandate was to manage research grants in Nanoelectronic
`
`Modeling and Systems, Quantum Computing, and Biologically-Inspired
`
`Computing, for which I had an operating annual budget of about $18 Million.
`
`22.
`
`In 2009, I served as a program director for NSF’s Engineering
`
`Directorate where I managed research in three disciplines: Adaptive Intelligent
`
`Systems (Machine Learning); Quantum, Molecular, and High-Performance
`
`Modeling; and Electronic and Photonic Devices.
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`Ex. 1001 - Declaration of Dr. Mazumder
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`23.
`
`In my three years of service to the United States government, I
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`participated in several NSF programs such as Cyber-Enabled Discovery and
`
`Innovation (CDI), Expeditions in Computing, Major Research Instrumentation
`
`(MRI), Computing Research Infrastructure (CRI) and Cyber Physical Systems
`
`(CPS). I also worked with several managers and administrators of NSF, the Defense
`
`Advance Research Projects Agency (DARPA), the Army Research Office (ARO),
`
`the Office of Naval Research (ONR), and the Air Force Office of Scientific Research
`
`(AFOSR) to launch several major research initiatives at the national level.
`
`24. During my 27 years as a professor, I have regularly taught the following
`
`graduate-level courses: 1) VLSI System Design, 2) Optimization and Synthesis of
`
`VLSI Layout, 3) Testing of Digital Circuits and Systems, 4) Advanced Computer
`
`Architectures, 5) Nanocircuits and Nanoarchitectures, 6) Ultra-Low-Power
`
`Subthreshold CMOS Circuits, and 7) Terahertz Technology and Applications. In
`
`that same period, I have also regularly taught the following undergraduate-level
`
`courses: 1) Introduction to Digital Logic Design (sophomore level), 2) Digital
`
`Integrated Circuit Design (junior level), and 3) VLSI System Design (senior level).
`
`25. My experience with the design of computer systems is also evident
`
`from the subject matter of the courses I have taught. For example, every year since
`
`1991, I have taught a major design experience (“MDE”) course on VLSI Systems
`
`Design, taken by senior undergraduate and entry-level graduate students. As the
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`main design component of the course, each team of four to five students must design
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`a fully-customized 16-bit RISC microprocessor for the given instruction set
`
`architecture. After completing the processor, students must develop an interesting
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`application for the processor by building embedded DRAM, SRAM and ROM and
`
`connecting them with the microprocessor through buses. The main goal of this VLSI
`
`design course is to give students hands-on design experience for a large chip design
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`project, as mandated by the Accreditation Board for Engineering and Technology
`
`(ABET).
`
`26. Over the last 30 years, I have trained and supervised 21 doctoral
`
`students and 35 Master’s students, many of whom now work in the microelectronics
`
`and semiconductor industries. To promote international collaboration, I hosted 10
`
`visiting professors from various parts of the world. In addition to numerous domestic
`
`students, I have also advised 12 undergraduate students from various countries
`
`providing them opportunity to gain undergraduate research experience.
`
`C. Relevant Publications
`I have published or co-published 13 books, 125 journal articles, 183
`27.
`
`peer-reviewed conference papers, and 4 book chapters. A full list of my publications
`
`can be found in my CV, which is included alongside my declaration.
`
`28. My first book, published in 1996, relates to testing and testable
`
`designed for Random-Access Memories (“RAM”). I also published a book relating
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`to the layout and automated-testing of very-large-scale integration (“VLSI”)
`
`integrated circuits (“IC”)—which involves the combination of thousands of
`
`transistors into a single chip—in 1999, and then I published a “Handbook for VLSI
`
`Routing” in 2018, prioritizing the discussion of serial and parallel modes of
`
`transmitting signals within an integrated chip. My other books generally relate to
`
`fault tolerances in RAM (2002), digital logic design (2018) and neuromorphic
`
`computing (2018), the last of which generally looks to biology to inform the
`
`development of algorithms and the design of certain semiconductor architectures.
`
`29.
`
`I have published numerous articles and journal publications advancing
`
`the state of the art for semiconductor and memory design.
`
`30.
`
`I have conducted significant research into the design of VLSI systems,
`
`especially those built using CMOS technology, which is a complementary metal–
`
`oxide–semiconductor fabrication technique that allows the creation of low-power
`
`integrated circuits. Many of my publications focused on the optimal layout of
`
`various components in a CMOS VLSI semiconductor device, including “Hexagonal
`
`Array Machine for Multi-Layer Wire Routing,” published in 1990 with the IEEE
`
`Transactions on Computer-Aided Design of Integrated Circuits and Systems
`
`Journal; “VLSI Cell Placement Techniques,” published in 1991 with the ACM
`
`Computing Surveys Journal; “Layout Optimization for Yield Enhancement in On-
`
`Chip VLSI/WSI Parallel Processing,” published in 1992 with the IEE Proceedings-
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`E: Computers and Digital Techniques Journal; and “CHiRPS: A General-area
`
`Parallel Multi-layer Routing System,” published in 1995 with the IEE Proceedings-
`
`E: Computers and Digital Techniques Journal. The last publication demonstrated
`
`how extreme scale fine grained parallel processing can be achieved by using simple
`
`processing elements with ALU and local memory to reconfigure them several times
`
`with flexible interconnections to perform various types of VLSI routing algorithms
`
`such as maze routing, channel routing, switchbox routing, and area routing. The
`
`content-addressable parallel processing CHiRPS architecture is also suited to
`
`accelerate general class of pixel-level image processing.
`
`31.
`
`I have also conducted research on reconfigurable processor
`
`architectures comprising programmable logic blocks and on-chip memories
`
`interconnected by reconfigurable buses, as can be found in my publication: “DA
`
`Techniques for PLD and FPGA Based Systems,” Integration, the International VLSI
`
`Journal, Vol. 17, Dec. 1994, pp. 191-240.
`
`32.
`
`I have also conducted significant research into memories that are
`
`commonly used with processors.
`
` For example, I published an article
`
`“Methodologies for Testing Embedded Content-Addressable Memories” in 1988
`
`with the “IEEE Transactions on Computer-Aided Design of Integrated Circuits and
`
`Systems” journal, which discusses techniques for testing content-addressable
`
`memories (“CAMs”) in dynamic RAMs (“DRAMs”). Specific to DRAMs, I have
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`Ex. 1001 - Declaration of Dr. Mazumder
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`also published articles on “A Reconfigurable Parallel Signature Analyzer for
`
`Concurrent Error Correction in Dynamic Random-Access Memory” (1990), “Circuit
`
`Behavior Modeling and Compact Testing Performance Evaluation” (1991), “On
`
`Restructuring of Hexagonal Arrays” (1992), and “Restructuring of Square Processor
`
`Arrays by Built-in Self-Repair Circuit” (1993). I have also published a number of
`
`articles on static RAMs, including “A Robust 12T SRAM Cell with Improved Write
`
`Margin for Ultra-Low Power Applications in 40 nm CMOS”, Integration, the VLSI
`
`Journal, Vol. 57, pp 1-10, March 2017, and “Technology and Layout Related Testing
`
`in Static Random-Access Memories” in 1994 in the Journal of Electronic Testing:
`
`Theory and Applications.
`
`33.
`
`I have also been selected for and published a number of peer-reviewed
`
`conference publications. These include, among others: “Evaluation of Three
`
`Interconnection Networks for CMOS VLSI Implementation,” published in 1986
`
`with the Proceedings IEEE International Conference on Parallel Processing;
`
`“Hexagonal Array Machine for Multi-Layer Wire Routing,” published in 1989 with
`
`the Proceedings IEEE International Conference on Computer-Aided Design; “On
`
`Restructuring of Hexagonal Processor Arrays,” published in 1991 with the IEEE
`
`Intl. Conf. on Defect and Fault Tolerance in VLSI Systems; “Processor Array Self-
`
`Reconfiguration by Neural Networks,” published in 1992 with the IEEE
`
`International Wafer Scale Integration; and “Parallel VLSI-Routing Models for
`
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`Polymorphic Processors Array (embedded tutorial),” published in 1997 with the
`
`Proceedings on IEEE International VLSI Conference. Each of these publications
`
`examined or related to the interconnect structures on VLSI semiconductor devices.
`
`D.
`34.
`
`Patents
`I have been a named inventor on ten granted U.S. patents, and I am the
`
`named inventor on three U.S. patent applications currently being reviewed. A full
`
`list of my patents can be found in my CV, which is included alongside my
`
`declaration.
`
`35. For example, I am named inventor on U.S. Patent number 5,903,170,
`
`granted on June 3, 1997 and titled “Digital Logic Design Using Negative Differential
`
`Resistance Diodes and Field-Effect Transistors.” My invention related to the design
`
`of digital logic gates using negative differential-resistance diodes and metal oxide
`
`semiconductor field effect transistors (“MOSFETS”) or heterostructure field effect
`
`transistors.
`
`36. As another example, I am named inventor on U.S. Patent number
`
`6,323,709, granted on November 21, 2001 and titled “High-speed, compact, edge-
`
`triggered, flip-flop circuit.” Whereas static flip flops use functional logic gates to
`
`temporarily store data in a flip-flop circuit, edge-triggered flip-flop circuits use a
`
`dynamic approach that is more flexible. My invention introduced a specialized latch
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`Ex. 1001 - Declaration of Dr. Mazumder
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`circuit, which improved circuit reliability as compared to prior-art dynamic flip-
`
`flops.
`
`37. Other technologies in which I have been listed as named inventor
`
`include:
`
`• Ultra-low-power CMOS Static Random Access Memory Cell having
`Improved Write Margin for use in Ultra-Low Power Application, disclosed
`in U.S. patent number 9,627,042;
`
`• Resistive RAM single-cell and multi-cell memory technology, disclosed
`in U.S. patent number 9,111,613;
`
`• CMOS circuit techniques, such as Method and Apparatus to Improve
`Noise Tolerance of Dynamic Circuits, disclosed in U.S. patent number
`7,088,143;
`
`• Terahertz technology such as Terahertz Analog-to-Digital Converter
`Employing Active-Controlled Spoofed Surface Plasmon Polariton
`Architecture, disclosed in U.S. patent number 9,341,921;
`
`• Mach-Zehnder Interferometer Having a Doubly-Corrugated Spoofed
`Surface Plasmon Polariton Waveguide, disclosed in U.S. patent number
`9,557,223;
`
`• Dynamic Terahertz Switching Device Comprising Sub-Wavelength
`Corrugated Waveguides and Cavity that Utilizes Resonance and
`Absorption for Attaining On and Off States, disclosed in U.S. patent
`number 8,842,948;
`
`• Dynamic Terahertz Switch Using Periodic Corrugated Structures,
`disclosed in U.S. patent number 8,837,036; and
`
`• Metamaterial Sensors Platform for Terahertz Sensing, disclosed in U.S.
`patent number 9,551,655.
`
`14
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`INTEL - 1001
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`

`

`Ex. 1001 - Declaration of Dr. Mazumder
`
`III. UNDERSTANDING OF PATENT LAW
`I understand that for purposes of this proceeding, prior art to the ’763
`38.
`
`patent includes patents and printed publications in the relevant art that predate the
`
`alleged priority date of the ’763 patent.
`
`39.
`
`I understand that claims in an IPR are construed under the case Phillips
`
`v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005), decided by the Federal Circuit in
`
`2005. Under the rule in Phillips, words of claims are given their plain and ordinary
`
`meaning as understood by a person of ordinary skill in the art in view of the
`
`specification and prosecution history, unless those sources show an intent to depart
`
`from such meaning.
`
`40.
`
`I understand that a claim is invalid if it is anticipated or obvious.
`
`Anticipation of a claim requires that every element be disclosed expressly or
`
`inherently in a single prior art reference, arranged in the prior art reference as
`
`arranged in the claim. Obviousness of a claim requires that the claim be obvious
`
`from the perspective of a POSITA at the time the alleged invention was made. I
`
`understand that a claim may be obvious solely in view of a single reference, or may
`
`be obvious from a combination of two or more prior art references.
`
`41.
`
`I understand that an obviousness analysis requires an understanding of
`
`the scope and content of the prior art, any differences between the alleged invention
`
`and the prior art, and the level of ordinary skill in evaluating the pertinent art.
`
`15
`
`INTEL - 1001
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`

`

`Ex. 1001 - Declaration of Dr. Mazumder
`
`42.
`
`I also understand that the following factors are relevant to obviousness:
`
`(a) Combining prior art elements according to known methods to yield
`
`predictable results;
`
`(b)
`
`Simple substitution of one known element for another to obtain
`
`predictable results;
`
`(c) Use of known technique to improve similar devices (methods, or
`
`products) in the same way;
`
`(d) Applying a known technique to a known device (method, or product)
`
`ready for improvement to yield predictable results;
`
`(e)
`
`“Obvious to try” – choosing from a finite number of identified,
`
`predictable solutions, with a reasonable expectation of success;
`
`(f) Known work in one field of endeavor may prompt variations of it for
`
`use in either the same field or a different one based on design incentives
`
`or other market forces if the variations are predictable to one of ordinary
`
`skill in the art;
`
`(g)
`
`Some teaching, suggestion, or motivation in the prior art that would
`
`have led one of ordinary skill to modify the prior art reference or to
`
`combine prior art reference teachings to arrive at the claimed invention.
`
`43.
`
`I further understand that a claim is obvious if it unites old elements with
`
`no change to their respective functions, or it alters prior art by mere substitution of
`
`16
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`INTEL - 1001
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`

`

`Ex. 1001 - Declaration of Dr. Mazumder
`
`one element for another known in the field, and that combination yields predictable
`
`results. While it may be helpful to identify a reason for this combination, common
`
`sense should guide and no rigid requirement of finding a teaching, suggestion, or
`
`motivation to combine is required. When a product is available, design incentives
`
`and other market forces can prompt variations of it, either in the same field or
`
`different one. If a person having ordinary skill in the relevant art can implement a
`
`predictable variation, obviousness likely bars its patentability. For the same reason,
`
`if