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`USOOSI9714OA
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`United States Patent
`5,197,140
`[11] Patent Number:
`
`
`
`
`
`
`Balmer
`[45] Date of Patent: Mar. 23, 1993
`
`
`
`[191
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`[54] SLICED ADDRESSING MULTI-PROCESSOR
`AND METHOD OF OPERATION
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`
`[75]
`Inventor: Keith Balmer, Bedford, England
`
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`[73] Assignee: Texas Instruments Incorporated,
`Dallas, Tex.
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`[21] Appl. No.: 437,946
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`;[22] Filed:
`Nov. 17, 1989
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`[51]
`Int. Cl.5 ...................... G06F 12/00; GO6F 15/00;
`G06F 7/33; GOéF 7/50
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`[52] US. Cl. .................................... 395/400; 395/300;
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`.
`364/749; 364/786; 364/787
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`[58] Field of Search ............... 395/400, 800, 163, 166;
`364/749, 786, 787
`
`
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`
`[56]
`
`
`
`
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`
`
`3,260,840 7/1966 King .................................... 364/787
`
`
`
`
`
`
`8/1972 Hanslip ..
`..... 364/749
`3,683,163
`
`
`
`
`
`
`3,728,532 4/1973 Pryor .............................. 364/787
`
`
`
`
`
` 4,562,535 12/ 1985 Vincent et a1. ......... 395/325
`
`
`
`
`
`
`
`4,644,496 2/ l 987 Andrews ............. 395/800
`
`
`
`
`
`
`4,747,043
`5/1988 Rodman .......... 395/425
`
`
`
`
`
`
`4,860,248
`8/1989 Lumelsky ............ 395/163
`
`
`
`
`
`
`4,888,679 12/1989 Fossum et al.
`395/800
`.
`
`
`
`
`
`
`8/1980 Kellcher et al.
`..... 395/ 166
`4,953,101
`
`
`
`
`3/1992 Fujiwara et a1.
`................... 395/400
`5,101,338
`
`
`
`
`OTHER PUBLICATIONS
`
`
`
`
`
`
`
`“The Connection Machine”, W. D. Hillis, published in
`The MIT Press (1985).
`
`
`
`
`
`
`
`
`
`
`
`“Handling Real Time Images Comes Naturally to Sys-
`
`
`
`
`
`
`
`tolic Array Chip”, by Hannaway, Shea, Bishop in Elec-
`
`
`
`
`
`
`tronic Design, pp. 289—300, Nov. 1984.
`
`
`
`
`
`
`“Systolic Array Chip Recognizes Visual Patterns
`
`
`
`
`
`Quicker Than a Wink”, by W. W. Smith, P. Sullivan, in
`
`
`
`
`
`
`
`Electronic Design, pp. 257-266, No. 29, 1984.
`
`
`
`
`
`“Real Time 3D Object Tracking in a Rapid Prototyping
`
`
`
`
`
`Environment”, Robert J. Gove, Electronic Imaging
`
`
`
`
`
`’88, Oct. 4, 1989, pp. 54-59.
`
`
`
`
`
`
`
`“Integration of Symbolic and Multiple Digital Signal
`
`
`
`
`
`
`
`Processors with the Explorer/Odyssey for Image Pro-
`
`
`
`
`cessing and Understanding-Applications”, Robert J.
`
`
`
`
`
`
`Gove, Proceedings to the IEEE International Sympo-
`
`
`
`
`
`
`
`
`sium of Circuits and Systems, pp. 968—971 (May, 1987).
`
`
`
`
`
`“The Use of Parallel—Processing Computers in Digital
`
`
`
`
`
`
`
`Image Processing”, Lew Brown, Electronic Imaging
`
`
`
`
`
`
`’87, International Electronic Imaging Exposition and
`
`
`
`
`
`Conference, Nov. 2, 1987, pp. 1057—1060.
`
`
`
`
`
`“VITec Parallel C Compiler”, by Butler, Electronic
`
`
`
`
`
`
`Imaging ’89, International Electronic Imaging Exposi-
`
`
`
`
`
`
`
`tion and Conference, Nov. 1989, pp. 741—747.
`
`
`
`
`
`
`
`
`“A Single Board Image Computer with 64 Parallel
`
`
`
`
`
`
`Processors” by Stephen Wilson, Electronic Imaging
`
`
`
`
`
`’87, International Electronic Imaging Exposition &
`
`
`
`
`
`Conference, Nov. 2, 1987, pp. 470—475.
`
`
`
`
`
`
`
`“The Androx Parallel Image Array Processor", Wayne
`
`
`
`
`
`
`Threatt, Electronic Imaging ’87, International Elec-
`
`
`
`
`
`
`tronic Imaging Exposition & Conference, Nov. 2, 1987,
`
`
`pp. 1061—1064.
`
`
`
`
`
`“Design of a Massively Parallel Processor”, Kenneth
`
`
`
`
`
`Batcher, IEEE Transactions on Computers, v. C—29,
`
`
`
`
`
`No. 9, Sep. 1980, pp. 836—840.
`
`
`
`
`
`
`“High Resolution Frame Grabbing and Processing
`
`
`
`
`
`
`Through Parallel Architecture”, Daniel Crevier, Elec-
`
`
`
`
`
`
`tronic Imaging ’87, International Electronic Imaging
`
`
`
`
`
`
`Exposition & Conference, Nov. 2, 1987, pp. 681—682.
`
`
`
`
`(List continued on next page.)
`
`
`
`Primary Examiner—Joseph L. Dixon
`Assistant Examiner—Michael A. Whitfield
`
`
`
`
`
`
`
`Attorney, Agent, or Firm—Robert D. Marshall, Jr.;
`James C. Kesterson; Ricth L. Donaldson
`
`
`
`
`
`
`ABSTRACT
`[57]
`
`
`
`
`
`
`A multi-processor system arranged, in one embodiment,
`
`
`
`
`
`
`
`as an image and graphics processor. The processor is
`
`
`
`
`
`
`structured with several individual processors all having
`communication links to several memories. An address-
`
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`
`
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`
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`ing scheme, called sliced addressing, is used to spread
`
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`contiguous related data over several memories so that
`
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`
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`the data can be concurrently accessed by several pro-
`cessors. A crossbar switch serves to establish the pro-
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`
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`cessor memory links. The entire image processor, in-
`
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`
`
`cluding the individual processors, the crossbar switch
`
`
`
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`
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`and the memories, is contained on a single silicon chip.
`
`
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`
`
`13 Claims, 35 Drawing Sheets
`
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`
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`SUCE
`CAPABIUTY
`
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`SUCE WSK BUS FROM PROCESSOR REGISTER
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`INTEL - 1005
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`INTEL - 1005
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`

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`snsznw
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`Page 2
`
`OTHER PUBLICATIONS
`
`
`
`
`
`
`
`
`“Multiple Digital Signal Processor Environment for
`
`
`
`
`
`
`Intelligent Signal Processors by Gass et al.”, Proceed—
`
`
`
`
`
`
`
`
`
`ings of the IEEE, v. 75, No. 9 (Sep. 1987) pp.
`1246—1259.
`
`
`
`
`
`
`
`“Architecture and Design of the Mars Hardware Ac-
`
`
`
`
`
`
`celerator”, AGRA Wall, in 24th ACM/IEEE Design
`
`
`
`
`
`Automation Conference (1987), pp. 101- 107.
`
`
`
`
`
`‘.‘A 200 MIPS Single—Chip IKFFY Processor”, by on I
`
`
`
`
`
`
`Brien, Mather & Holland, IEEE International Solid—S-
`
`
`
`
`
`
`
`
`;tate Circuits Conference, Feb 16, 1989, pp. 166- 167
`
`
`
`
`
`
`
`“An Architectural Study, Design and Implementation
`
`
`
`
`
`
`
`of Digital Image Acquisition Processing and Display
`
`
`
`
`
`Systems with Micro-Processor—Based Personal Com-
`
`
`
`
`
`
`puters and Charge-Coupled Device Imaging Technol-
`
`
`
`
`
`
`ogy”, a Dissertation by Robert J. Gove, SMU, May 17,
`1986.
`
`
`
`
`
`
`
`
`“A Medium Grained Parallel Computer for Image Pro-
`
`
`
`
`lcessing” by R. S. Cok, published by Digital Technology
`
`
`
`
`
`
`‘ Center, Eastman Kodak Co., Rochester, N.Y., pp.
`927—936.
`
`
`
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`
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`INTEL-1005
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`INTEL - 1005
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`US. Patent
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`Mar. 23, 1993
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`Sheet 1 of 35
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`5,197,140
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`lNTERRUPT—OR—POLL
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`ASSIGNMENT
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`FIG. 2
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`PACKET REQUEST
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`INTEL - 1005
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`US. Patent
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`Mar. 23, 1993
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`Sheet 2 of 35
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`5,197,140
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`INTEL - 1005
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`INTEL - 1005
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`US. Patent
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`Mar. 23, 1993
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`Sheet 3 of 35
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`5,197,140
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`US. Patent
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`Mar. 23, 1993
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`Sheet 4 of 35
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`5,197,140
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`U.S. Patent
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`Mar. 23, 1993
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`Sheet 5 of 35
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`5,197,140
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`FIG. 13
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`US. Patent
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`Mar. 23, 1993
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`Sheet 6 of 35
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`5,197,140
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`US. Patent
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`Mar. 23, 1993
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`Sheet 7 of 35
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`US. Patent
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`Mar. 23, 1993
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`Sheet 8 of 35
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`5,197,140
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`US. Patent
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`Mar. 23, 1993
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`Sheet 9 of 35
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`5,197,140
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`US. Patent
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`Mar. 23, 1993
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`Sheet 10 of 35
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`5,197,140
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`

`

`
`US. Patent
`
`
`
`
`Mar. 23, 1993
`
`
`
`Sheet 11 of 35
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`
`5,197,140
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`

`

`US. Patent
`
`Mar. 23, 1993
`
`Sheet 12 of 35
`
`5,197,140
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`U.S. Patent
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`
`hdar.23,1993
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`
`Sheet 14 of 35
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`

`US. Patent
`
`
`
`
`Mar. 23, 1993
`
`
`
`
`
`Sheet 15 of 35
`
`
`5,197,140
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`
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`

`

`US. Patent
`
`
`
`
`Mar. 23, 1993
`
`
`
`
`Sheet 16 of 35
`
`
`5,197,140
`
`
`
`
`PARALLEL
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`FIG. 30
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`INTEL - 1005
`
`INTEL - 1005
`
`

`

`US. Patent
`
`
`
`
`Mar. 23, 1993
`
`
`
`
`Sheet 17 of 35
`
`
`5,197,140
`
`
`
`PROGRAM FLOW CONTROL UNH
`r --------------------- ‘-------------------- fl
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`INTEL - 1005
`
`

`

`US. Patent
`
`
`
`
`Mar. 23, 1993
`
`
`
`
`
`Sheet 18 of 35
`
`
`5,197,140
`
`
`
`
`ADDRESS UNH
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`
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`GLOBAL ll
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`FIG. 32
`
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`
`INTEL-1005
`
`INTEL - 1005
`
`

`

`US. Patent
`
`
`
`
`Mar. 23, 1993
`
`
`
`
`
`Sheet 19 of 35
`
`
`5,197,140
`
`
`
`
`
`
`
`
`
`
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`
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`FIG. 34
`
`
`
`
`
`
`
`
`
`STATUS REGISTER (SR)
`
`
`
`
`
`
`
`
`
`INTEL - 1005
`
`INTEL - 1005
`
`

`

`US. Patent
`
`
`
`Mar. 23, 1993
`
`
`
`
`
`Sheet 20 of 35
`
`
`5,197,140
`
`
`
`
`SIMDI PAUSE
`
`
`
`
`
`FIG 35
`
`
`
`
`
`
`
`pc
`
`
`
`
`EtI
`
`A
`
`F
`
`E
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`
`
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`
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`Fcrn - CACHE-MISS
`
`
`
`
`
`
`
`
`
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`
`
`
`
`
`
`Exb - CROSSBAR ACCESS(ES) OCCUR.
`STORES COMPLETE TO MEMORY.
`LOADS
`
`
`
`
`
`
`
`
`COMPLETE INTO TWPORARY LATCHES, MASTER PHASE OF DATA UNIT
`
`
`OPERATIONS KILLED.
`
`
`
`
`
`Enm - N0 MASTER PHASE OF DATA UNIT.
`
`
`
`
`
`Fwa - WAIT FOR CACHE—MISS ACKNOWIEDGE FROM TP.
`
`
`
`
`
`
`ch - TRANSFER PC AND SEGMENT NUMBER TO TP
`
`
`
`
`
`
`
`
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`
`
`
`
`
`
`
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`
`
`
`
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`DATA UNIT PERFORMS ITS ALU MPY OPERATIONS.
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`F
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`
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`
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`an - N0 MASTER PHASE ON FETCH.
`PIPE NOT LOADED.
`
`
`
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`LOCAL BUS TRANSFER OCCURS.
`
`
`
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`
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`STORE TO MEMORY. OR LOAD TO TEMP REGISTER.
`NO MASTER PHASE IN
`
`
`DATA UNII.
`
`
`
`
`
`
`
`
`EtL - TEMPORARY LATCH DATA (LOADS) COMPLETE INTO DESTINATION REGISTER(S).
`
`
`
`
`
`DATA UNIT PERFORMS ITS ALU/MPY OPERATIONS.
`
`
`
`
`
`
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`
`Anm - NO MASTER PHASE IN ADDRESS UNIT. ADDRESS REGISTER NOT MODIFIED.
`
`
`
`
`NO MASTER
`
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`
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`
`INTEL - 1005
`
`INTEL - 1005
`
`

`

`US. Patent
`
`
`
`
`Mar. 23, 1993
`
`
`
`
`Sheet 21 of 35
`
`
`5,197,140
`
`
`
`F
`
`
`
`A
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`
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`cId:=cId-—1
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`Fsa — START ADDRESS OF LOOP.
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`Fer - END ADDRESS, REPEAT LOOP.
`
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`WITH START ADD.
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`
`Fen - END ADDRESS. NO—REPHIIION.
`
`
`INCREMENTS NORMALLY.
`
`
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`
`PC INCREMENTS NORMALLY.
`
`
`
`
`
`
`LOOP COUNTER NOT ONE. LOAD PC
`'
`
`
`
`
`LOOP COUNTER IS ONE.
`
`FIG. 3 7
`
`PC
`
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`
`
`
`
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`
`
`
`
`
`I
`
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`
`retz=pc+1
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`
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`FdI - DELAY SLOT 1
`
`
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`
`
`
`
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`
`
`
`
`# — INTERRUPTS LOCKED OUT.
`
`
`
`
`
`INTEL - 1005
`
`INTEL - 1005
`
`

`

`US. Patent
`
`
`
`
`Mar. 23, 1993
`
`
`
`
`Sheet 22 of 35
`
`
`5,197,140
`
`
`
`
`
`I
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`
`
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`SIMD MASTER" PP T0
`SLAVE" PP INTERRUPT SIGNAL
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`SIMD 'SLAVE' PP TO "MASTER" PP INTERRUPT SIGNAL
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`ML"IIIIII
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`F
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`
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`
`
`
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`
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`FETCH INTERRUPT VECTOR INTO PC.
`
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`
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`(PUSH RET).
`
`
`
`
`Apr - CALCULATE STACK PUSH ADDRESS.
`
`
`
`
`
`Epr - PUSH RET ONTO STACK.
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`
`
`
`
`Fps - PSEUDO INSTRUCTION.
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`
`
`
`
`Aps - CALCULATE STACK PUSH ADDRESS.
`
`
`
`
`
`
`
`
`
`
`Eps — PUSH SR ONTO STACK.
`CLEAR S.
`I AND CID BITS IN SR.
`
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`
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`
`
`Fin - FIRST INSTRUCTION 0F INTERRUPT ROUTINE
`
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`s - SYNC,
`INTERRUPTS AND LOOPING DISABLED UNnL AFTER SR HAS BEEN PUSHED.
`
`
`
`
`
`
`
`
`
`NEITHER OF FIRST Two INSTRUCTIONS OF INIERRUPT ROUTINE MAY BE A LCK.
`
`
`
`
`
`
`FIG. 39
`
`
`
`INTEL - 1005
`
`INTEL - 1005
`
`

`

`US. Patent
`
`
`
`
`Mar. 23, 1993
`
`
`
`Sheet 23 of 35
`
`
`5,197,140
`
`
`
`I
`I
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`
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`
`
`
`
`
`
`
`SYNC SIG I
`
`F
`
`
`
`
`
`
`F
`
`
`
`A
`Fnd
`
`
`
`
`Etl
`
`A
`va
`
`
`
`
`Apv
`Fpr
`
`
`
`
`
`Epv
`
`Apr
`
`Fps
`
`
`Epr
`
`Aps
`
`SHn
`
`
`
`Eps
`
`A
`
`SE
`
`E
`A
`
`
`
`
`
`
`pc
`
`
`
`pc
`
`
`
`pc
`
`
`
`pc
`
`pc+1
`
`
`
`
`
`
`
`
`
`pc
`
`
`
`
`Exb
`Enm
`
`
`
`
`.
`.
`.
`.
`Anm .
`.
`
`
`an .
`.
`.
`.
`.
`.
`
`Int
`
`Int
`
`IN
`SIove
`
`PP
`
`
`
`pc
`pc+1pc+1pc+1
`
`
`
`
`FId - IDLE INSTRUCTION FETCHED.
`
`
`
`
`
`
`
`
`PIPELINE NOT LOADED.
`an — N0 MASTER PHASE ON INSTRUCTION FETCH.
`
`
`
`
`
`
`
`
`Anm - NO MASTER PHASE ON INSTRUCTION FETCH. ADDRESS REGISTERS NOT MODIFIED.
`
`
`
`
`
`
`Exb - CROSSBAR ACCESS(ES) OCCUR.
`STORES COMPLETE TO MEMORY.
`LOADS
`
`
`
`
`
`
`
`
`COMPLETE INTO TEMPORARY LATCHES. MASTER PHASE OF DATA UNTT OPERATIONS
`
`KILLED.
`
`
`
`
`Enm - NO MASTER PHASE IN DATA UNTT.
`
`
`
`Int - INTERRUPT OCCURS.
`
`
`
`
`
`
`
`
`EtL - TEMPORARY LATCH DATA (LOADS COMPLETE INTO DESTINATION REGISTER(S).
`
`
`
`
`
`
`DATA UNTT PERFORMS TTS ALU MPY OPERATIONS.
`
`
`
`
`
`
`
`
`
`va - PSEUDO INSTRUCTION.
`(PC T0 RET.
`IECTOR FETCH INTO PC).
`
`
`
`
`
`
`Apv - CALCULATE INTERRUPT VECTOR ADDRESS.
`
`
`
`
`
`
`
`Epv — COPY PC TO RET.
`FETCH INTERRUPT VECTOR INTO PC.
`
`
`
`
`
`Fpr - PSEUDO INSTRUCTION.
`(PUSH RET).
`
`
`
`
`Apr - CALCULATE STACK PUSH ADDRESS.
`
`
`
`
`
`Epr - PUSH RET ONTO STACK.
`
`
`
`
`Fps - PSEUDO INSTRUCTION.
`(PUSH SR).
`
`
`
`
`Aps - CALCULATE STACK PUSH ADDRESS.
`
`
`
`
`
`
`
`
`
`Eps — PUSH SR ONTO STACK.
`I AND CID BITS IN SR.
`CLEAR S,
`
`
`
`
`
`
`Fin - FIRST INSTRUCTION OF INTERRUPT ROUTINE.
`'
`
`
`
`
`
`
`
`
`
`
`S - SYNC.
`INTERRUPTS AND LOOPING DISABIED UNTIL AFTER SR HAS BEEN PUSHED.
`
`
`
`
`
`
`
`
`
`NETTHER OF FIRST TWO INSTRUCTIONS OF INTERRUPT ROUTINE MAY BE A LCK.
`
`
`FIG. 40
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`INTEL - 1005
`
`INTEL - 1005
`
`

`

`US. Patent
`
`
`
`
`Mar. 23, 1993
`
`
`
`
`Sheet 24 of 35
`
`
`5,197,140
`
`
`
`
`FIG. 41
`
`
`
`I
`
`
`
`|
`
`
`
`
`
`
`
`INCOMING SYNC SIGNAL
`
`
`
`pc+1
`
`
`
`
`
`pc
`
`
`
`
`
`
`pc+1
`pc
`pc
`pc+1
`pc+1
`
`
`
`
`
`
`
`
`
`PC UNALTERED.
`PIPE NOT LOADED.
`Fns — N0 SYNC CONDITION.
`
`
`
`
`
`
`
`
`Anm - N0 MASTER PHASE IN ADDRESS UNIT. ADDRESS REGISTERS NOT MODIFIED.
`
`
`
`
`
`
`
`Exb - CROSSBAR ACCESS(ES) OCCUR.
`STORES COMPLETE TO MEMORY.
`LOADS
`
`
`
`
`
`
`
`
`COMPLETE INTO TEMPORARY LATCHES. MASTER PHASE OF DATA UNIT
`
`
`OPERATIONS KILED.
`
`
`
`
`
`Enm — NO MASTER PHASE IN DATA UNIT.
`
`
`
`
`
`
`
`
`EtL - TEMPORARY LATCH DATA (LOADS COMPIEIE INTO DESIGNATION REGISTER(S).
`
`
`
`
`
`
`DATA UNIT PERFORMS TTS ALU MPY OPERATIONS.
`
`
`
`
`
`
`
`LOADS:
`
`
`
`
`
`(ASSUMING N0 SIGN—EXTENSION)
`
`
`
`
`FIC. 42
`
`
`
`
`BYTE N0.
`
`
`
`3 2 1 0
`SOURCE DATA:
`
`
`D C B A
`OOOOh =
`
`
`0004h = HGFE
`
`
`? ? ? ?
`
`
`
`=
`
`DESTINATION
`
`(MEMORY)
`
`
`
`(REGISTER)
`
`
`
`
`2P.— ADD.
`
`LD
`LDU
`
`
`
`
`
`
`16-BIT
`
`
`
`
`REG VALUE
`LOADS...
`
`
`
`OOBA
`OOOOh OOBA
`
`
`
`
`OOBA
`0002h ----
`
`
`
`0001h
`--—B ???B
`
`
`
`0003h 00C— 0008
`
`
`
`0002h OODC
`OODC
`
`
`
`---— OODC
`0004-h
`
`
`
`0003h —--D ???D
`
`
`
`
`0005h OOE— OOED
`
`
`LD
`LDU
`
`
`
`LD
`LDU
`
`
`
`
`LD
`LDU
`
`
`
`
`
`
`32-BIT
`
`
`
`
`REG VALUE
`LOADS...
`
`
`
`DCBA
`OODOh DCBA
`
`
`
`DCBA
`OOO4h ----
`
`
`
`0001h
`-DCB ?DCB
`
`
`
`0005h E—-— EDCB
`
`
`
`
`0002h
`--DC ??DC
`
`
`
`OOOGh FE--
`FEDC
`
`
`
`0003h ---D ???D
`
`
`
`0007b GFE- GFED
`
`
`OF.— ADD.
`
`LD
`LDU
`
`
`
`
`LD
`LDU
`
`
`LD
`LDU
`
`
`
`
`
`
`LD
`‘LDU
`
`
`
`INTEL - 1005
`
`INTEL - 1005
`
`

`

`
`US. Patent
`
`
`
`
`Mar. 23, 1993
`
`
`
`
`Sheet25 of35
`
`5,197,140
`
`
`
`STORES:
`
`
`
`SOURCE DKUt
`
`
`
`
`
`
`
`
`DESflNAHON DKUt
`
`
`
`OOOOh
`
`0004h
`
`
`16-3”
`
`
`
`STORES...
`
`
`
`0 0 B A
`
`OOOOh
`0004h
`
`
`
`D C B A
`
`
`
`
`BYTE N0.
`
`3 2 1 0
`
`
`? ? ? ?
`
`? ? ? ?
`
`(REGISTER)
`
`
`
`(MEMORY)
`
`32-8”
`
`
`
`
`
`STORES".
`
`D C B A
`
`
`0_P_
`
`
`ST
`
`
`__D-
`
`0000h
`
`
`
`
`
`
`01 ADD-
`
`
`.ST
`
`OOOOh
`
`
`
`
`
`STU
`
`
`
`0002h
`
`
`
`
`
`STU
`
`
`
`0004h
`
`
`
`
`
`ST
`
`
`
`
`0001h
`
`
`
`
`
`
`
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`
`
`
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`
`
`
`
`
`STU
`
`
`
`0003b
`
`
`
`
`
`
`
`STU
`
`
`
`0005h
`
`
`
`
`
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`
`REG VfiLUE
`
`
`
`
`
`
`
`
`
`
`
`~0m'0m'00'90
`
`noa:-ono-0«a-o«a~o-o-o-o
`
`
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`
`0002h
`
`
`
`
`
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`
`
`
`
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`
`
`
`
`
`
`
`-o>-o>«am-om~o-o-o-o
`
`
`
`
`
`
`
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`
`
`
`ST
`
`
`
`
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`
`
`
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`
`
`
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`
`
`
`
`
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`
`
`
`
`
`'0'0'0-0 0s)d0 m-0‘000
`
`
`
`
`
`
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`
`
`
`ST
`
`
`
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`
`
`
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`
`
`
`STU
`
`
`
`
`
`
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`
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`
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`
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`
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`
`
`
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`
`
`
`
`
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`U'0'0'0
`
`
`
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`
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`
`
`
`
`
`
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`
`
`
`
`
`
`
`FIG.
`
`
`
`43
`
`
`
`TNTEL - 1005
`
`INTEL - 1005
`
`

`

`US. Patent
`
`Mar. 23, 1993
`
`Sheet 26 of 35
`
`5,197,140
`
`ADD WITH SATURATE
`
`
`. MAXIMUM
`
`
`TRANSPARENCY
`
`D0, D1, D2
`ADDM
`MM 02, D3, DZ
`
`SUBM
`MRGM
`
`D0, D1, D2
`00. D1, D2
`
`. CMPM
`MRGM
`
`DO. D1
`DO. 02. 03
`
`m=8923cu87
`+01 = 01 A8 45 EF
`
`00:89230067
`-D1 = 01 AB 45 at
`
`00:89230067
`(—)01 = 23 23 23 23
`
`
`DZ:=8ACE1256
`MFLAcs: = 9? ?? 9° '23
`
`D2:=886 8867
`MHAcs: = ?? '2? '2? '25
`
`(=66008A44)
`MFLAGS: = '2? 2? ?? '24
`
`DZ=8ACE1256
`D3=FFFFFFFF
`
`
`D0=8923C067
`D1=01AB45EF
`
`
`DO=8923CDG7
`
`Dz=87854321
`
`DIS:=89650067
`02:=89ABCDEF
`D2:=8ACEFFFF
`_-———__—__——__——-————_——_——_——_———_—_——————
`
`COLOUR EXPANSION
`
`COLOUR COMPRESSION
`
`GUIDED COPY
`
`ID #AO, MFLAGS
`MRGM
`D0, D1, DZ
`
`MFLAGS = XX XX XX X6
`
`DO=11111111
`D1 =8888 88 88
`
`D2: = 11 88 8811
`
`CMPM
`
`DO. D1, 02
`
`DD = 89 23 CD 67
`(-)D1 = 89 89 89 89
`
`= 00 89 44 co)
`MFLAGS = ?? ?? ?? ?8
`
`FIG. 44
`
`LD
`MRGM
`
`#10. MFLAGS
`DO, D1. D1
`
`MFLAGS=XXXXXXXC
`
`DO=89230067
`
`D1=87654321
`
`D1: = 87 65 CD 67
`
`
`
`L—UNE OF 512 PIXELS
`
`FIG. 45
`
`INTEL - 1005
`
`INTEL - 1005
`
`

`

`US. Patent
`
`
`
`
`Mar. 23, 1993
`
`
`
`
`
`Sheet 27 of 35
`
`
`5,197,140
`
`
`
`
`
`
`
`REMOTE
`
`
`#—
`
`
`
`TRANSMISSION
`
`RECENER
`
`
`
`
`
`INTEL - 1005
`
`INTEL - 1005
`
`

`

`U.S. Patent
`
`
`
`
`Mar. 23, 1993
`
`
`
`
`Sheet 23 of 35
`
`
`5,197,140
`
`
`
`TELEPHONE
`
`UNE
`
`
`
`
`
`
`
`
`
`
`
`6163
`”(WWW
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`CONTROLLER
`
`
`
`5001
`
`
`
`5002
`
`
`
`
`
`
`
`OBJECT OR
`
`DOCUMENT
`FOR COPYING
`
`
`
`
`
`
`
`
`
`
`
`
`FACSIMILE
`PRODUCT
`
`
`
`
`5009
`
`
`
`
`
`
`
`5007
`
`
`
`ACCUMULATED
`
`' ECORDKEEPI 0
`
`
`
`
`
`
`
`
`
`
`INTEL - 1005
`
`INTEL - 1005
`
`

`

`US. Patent
`
`
`
`Mar. 23, 1993
`
`
`
`
`Sheet 29 of 35
`
`
`5,197,140
`
`
`
` FRONT END
`
`
`
`
`PROCESSOR
`
`
`FIG. 52
`
`
`
`
`
` IMAGE
`
`PROCESSOR
`
`
`
`
`
`
`
`INTEL - 1005
`
`INTEL - 1005
`
`

`

`US. Patent
`
`
`
`
`Mar. 23, 1993
`
`
`
`
`
`Sheet 30 of 35
`
`
`5,197,140
`
`
`
`°
`
`0
`
`0
`
`
`
`5424
`
`N Z
`
`Z
`Z
`
`_____ 30.- __-___ 2.0.- ___..- ___ _-__ ___
`
`5436T§426c
`{54260
`'1 5426b
`
`
`428:
`:
`54360
`5428.0
`432.5430
`g
`. '
`I 54340
`54320 5434
`
`
`
`
`0 1-
`
`
`
`INTEL-1005
`
`INTEL - 1005
`
`

`

`US. Patent
`
`Mar. 23, 1993
`
`Sheet 31 of 35
`
`5,197,140
`
`
`
`5666
`
`ROW
`COUNTS
`
`5668
`
`FIG. 56
`
`5670
`
`0000000001
`
`nZUnUnununZUnun.9g
`
`0011111003
`
`0010100001.
`
`123456789
`543210
`
`COLUMN
`COUNTS
`
`INTEL - 1005
`
`INTEL - 1005
`
`

`

`US. Patent
`
`
`
`Mar. 23, 1593
`
`
`
`Sheet 32 of 35
`
`
`5,197,140
`
`
`
`5703
`
`
`
`
`5701
`
`5700
`
`
`
`‘5702
`
`
`
`'
`
`8x64 Brr FIFO
`
`
`
`
`
`
`
`GENERATOR g
`
`SOURCE
`ADDRESS
`
`
`
`32-3”ADDRESSBUS
`
`
`EXPAND/AUGN LOGIC
`
`5705
`
`
`
`
`
`5708
`
`
`
`
`FIG. 57
`
`
`
`5706
`
`DESHNATION E
`
`ADDRESS
`
`GENERATOR
`
`
`
`
`
`B
`
`E
`
`
`
`
`FROM CCD
`
`
`ASYNC CLOCK
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`INTEL - 1005
`
`INTEL - 1005
`
`

`

`US. Patent
`
`
`
`
`Mar. 23, 1993
`
`
`
`
`
`Sheet 33 of 35
`
`
`5,197,140
`
`
`
`
`
`FIG, 5 9
`
`
`
`
`
`MM; GENERAL CASE (PRIOR ART)
`
`
`5901
`
`
`
`
`
`
`
`
`
`
`
`
`
`FIG. 60
`
`
`
`
`
`
`
`
`6°42
`
`
`
`6001
`
`
`
`6000
`
`
`
`
`
`
`
`
`
`
`
`6040
`
`
`
`
`
`
`
`INTEL - 1005
`
`INTEL - 1005
`
`

`

`US. Patent
`
`
`
`
`Mar. 23, 1993
`
`
`
`
`
`Sheet 34 of 35
`
`
`5,197,140
`
`
`
`I I
`
`I
`
`
`
`
`
`.8
`
`'
`
`MEMORY
`
`I
`
`I
`
`'
`
`O
`
`
`
`
`
`101
`
`3100
`
`M]—
`3002“i |_
`-|
`r-——————4
`
`
`3100fimK=dI
`
`
`40
`DA_APATH 4—;I———l-.. I
`
`
`
`
`
`
`
`
`3002“W '
`INSTRUCTION
`I
`
`
`a
`3100 =
`i
`w
`—— MEMORY
`I
`
`
`
`
`
`g
`|_°A—_.TAPAP
`.
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`I
`
`
`g 30—,02-‘—_I‘_____ INSTRUCTION
`I
`
`
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`E DA_APATTI <-—:—::—-> DATA MEMORY
`:
`
`
`
`1023002“.—_—:-
`INSTRUCTION
`I
`I
`I
`JWC-OHR:hlfil—I- MEMORY
`I
`
`
`I
`
`
`DA_APATH 4—__-_., I
`L ______ _|
`
`
`
`FIC.
`
`
`
`13100
`
`
`
`
`
`
`
`
`
`
`410
`
`
`
`
`: I
`
`I I I I
`
`II
`
`I
`I
`I
`I
`I
`
`I I
`
`I I
`
`
`
`_II
`
`I—_l
`
`INTEL - 1005
`
`IMD
`
`
`
`40
`
`
`
`
`§
`
`
`0
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`§
`
`m
`
`
`
`
`FIG. 62
`
`
`
`INTEL - 1005
`
`

`

`US. Patent
`
`
`
`
`Mar. 23, 1993
`
`
`
`
`
`Sheet 35 of 35
`
`
`5,197,140
`
`
`
`.2
`
`______
`
`
`
`100
`
`N
`
`
`
`3100
`
`*
`
`
`
`I
`
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`
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`INTEL - 1005
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`MIM
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` PROCESSORSYNCBUS
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`FIG. 64
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`INTEL - 1005
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`1
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`5,197,140
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`SLICED ADDRESSING MULTI-PROCESSOR AND
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`METHOD OF OPERATION
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`TECHNICAL FIELD OF THE INVENTION
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`This invention relates generally to multi-processor
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`systems and more particularly to an addressing arrange-
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`ment and method for use in such systems. CROSS REF-
`ERENCE TO RELATED APPLICATIONS
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`10
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`All of the following patent applications are cross-
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`referenced to one another, and all have been assigned to
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`Texas Instruments Incorporated. These applications
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`have been concurrently filed and are hereby incorpo-
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`rated in this patent application by reference.
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`US. Pat. Application
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`Ser. No.
`Title
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`437,591
`Multi-Processor With Crossbar Link of
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`Processors and Memories and Method of
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`Operation
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`SIMD/MIMD Reconfigurable Multi-
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`Processor and Method of Operation
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`Reconfigurable Communications for
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`Multi-Processor and Method of Operation
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`Reduced Area of Crossbar and Method of
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`Operation
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`Synchronized MIMD Multi-Processors,
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`System and Method of Operation
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`Sliced Addressing Multi-Processor and
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`Method of Operation
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`Ones Counting Circuit and Method of
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`Operation
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`Memory Circuit Reconfigurable as Data
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`Memory or Instruction Cache and
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`Method of Operation
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`Imaging Computer and Method of
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`Operation
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`Switch Matrix Having Integrated
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`Crosspoint Logic and Method of
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`Operation
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`2
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`throughput of the system and negating much of the
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`power of the multi-processing system.
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`Accordingly, there exists a need in the art for a paral-
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`lel processing system which can store contiguous data
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`in different concurrently accessible address spaces.
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`There also exists a need in the art for such a system
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`where the fact of the actual location is transparent to
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`the user such that the address spaces continue to have
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`consecutive addresses regardless of the physical loca-
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`tion of the corresponding storage locations.
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`One method of solving the huge interconnection
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`problem in complex systems such as the image process-
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`ing system shown in one embodiment of the invention is
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`to construct the entire processor as a single device.
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`Conceptually this might appear easy to achieve, but in
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`reality the problems are complicated.
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`First of all, an architecture must be created which
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`allows for the efficient movement of information while
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`at the same time conserving precious silicon chip space.
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`The architecture must allow a very high degree of flexi-
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`bility, since once fabricated, it cannot easily be modified
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`for different applications. Also, since the processing
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`capability of the system will be high, there is a need for
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`high band width in the movement of information on and
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`off the chip. This is so since the physical number of
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`leads which can attach to any one chip is limited.
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`It is also desirable to design an entire parallel proces-
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`sor system, such as an image processor, on a single
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`silicon chip while maintaining the system flexible
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`enough to satisfy wide ranging and constantly changing
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`operational criteria.
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`It is further desirable to construct such a single chip
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`parallel processor system where the processor memory
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`interface is easily adaptable to operation in various
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`modes, such as SIMD and MIMD, as well as adaptable
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`to efficient on-off chip data communications.
`SUMMARY OF THE INVENTION
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`These problems have been solved b