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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
`Petitioner
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`v.
`
`DR. URI COHEN
`Patent Owner
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`
`
`Case IPR2018-00724
`Patent 6,518,668
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`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT 6,518,668
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`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`U.S. Patent & Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`

`

`
`
`Petition for Inter Partes Review of U.S. Patent No. 6,518,668
`
`I.
`II.
`III.
`
`C.
`
`D.
`E.
`
`TABLE OF CONTENTS
`Introduction. .................................................................................................... 1
`Grounds for standing (37 C.F.R. §42.104(a)). ............................................... 2
`Identification of challenge (37 C.F.R. §42.104(b)). ....................................... 2
`A.
`Citation of prior art. ............................................................................... 2
`B.
`Statutory grounds for the challenge. ..................................................... 3
`IV. The ’668 patent. .............................................................................................. 4
`A.
`Background of technology. ................................................................... 4
`B.
`The ’668 patent purports to improve interconnect structures
`by depositing multiple seed layers on surfaces of
`interconnect openings. ........................................................................... 7
`Claim construction. .............................................................................10
`“seed layer” .............................................................................. 11
`1.
`“substantially conformal seed layer” / “substantially
`2.
`non-conformal seed layer” ....................................................... 11
`“substantially conformal deposition technique” /
`“substantially non-conformal deposition technique” .............. 13
`Level of ordinary skill in the art. .........................................................15
`The challenged claims of the ’668 patent are not entitled to
`claim priority. ......................................................................................15
`1.
`The earlier-filed ’151 and ’707 patents do not provide
`written description support for the “substantially
`conformal”/ “substantially non-conformal” seed layer
`limitations. ................................................................................ 17
`The disclosure of conformal/non-conformal seed
`layers in the ’151 and ’707 patents do not extend to
`the entire thickness ranges required by the ’668
`patent’s “substantially conformal”/ “substantially
`non-conformal” seed layer express definitions. ....................... 19
`V. Ground 1: Wang in combination with Chen renders claims 17 and 19
`obvious. ......................................................................................................... 21
`A. Overview of Wang. .............................................................................21
`B.
`Overview of Chen ...............................................................................23
`C. Motivation to combine Wang and Chen. ............................................25
`D.
`Independent claim 1. ...........................................................................29
`
`3.
`
`2.
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`Petition for Inter Partes Review of U.S. Patent No. 6,518,668
`
`1. Wang discloses a “multiple seed layer structure used
`to fabricate devices” [1.P]. ....................................................... 29
`2. Wang discloses “a substrate” [1.1] and “a patterned
`insulating layer formed on said substrate” [1.2]. .................... 30
`3. Wang discloses the “barrier layer” limitation [1.3]. ............... 31
`4. Wang discloses the “first seed layer” limitation [1.4]. ............ 32
`a) Wang discloses a “first seed layer disposed
`over the barrier layer” [1.4.1]. ....................................... 32
`b) Wang discloses that the “first seed layer”
`includes a “substantially conformal seed layer
`whose thickness on the sidewalls of the opening
`(at about mid-depth) is about 25-100% of its
`thickness on the field” [1.4.2]. ....................................... 33
`5. Wang teaches or suggests the “second seed layer”
`limitation [1.5]. ........................................................................ 36
`a) Wang discloses a “second seed layer disposed
`over the first seed layer” [1.5.1]. ................................... 36
`b) Wang discloses that the “second seed layer”
`includes a “substantially non-conformal seed
`layer whose thickness on the sidewalls of the
`opening (at about mid-depth) is less than about
`25% of its thickness on the field” [1.5.2]. ..................... 38
`c) Wang teaches or suggests that the “second seed
`layer” is “thicker than said first seed layer over
`the field” [1.5.3]. ............................................................ 40
`i. Wang’s Figure 7 explicitly teaches that
`copper alloy material 216 is thicker than
`copper seed layer 214. ..........................................40
`ii. Wang’s specification suggests that
`copper alloy material 216 is thicker than
`copper seed layer 214. ..........................................41
`iii. Depositing a “substantially non-
`conformal seed layer” that is thicker than
`the “substantially conformal seed layer”
`would have been obvious to try. ..........................45
`6. Wang discloses the “electroplated metallic layer”
`limitation [1.6]. ........................................................................ 47
`Dependent claim 17. ............................................................................47
`Dependent claim 19. ............................................................................48
`
`- ii -
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`E.
`F.
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`

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`Petition for Inter Partes Review of U.S. Patent No. 6,518,668
`
`
`VI. Ground 2: Wang in combination with Hoinkis renders claims 18, 20, and 22
`obvious. ......................................................................................................... 50
`A. Overview of Hoinkis. ..........................................................................50
`B. Motivation to combine Wang and Hoinkis. ........................................51
`C.
`Dependent claim 18. ............................................................................53
`D. Dependent claim 20. ............................................................................53
`E.
`Dependent claim 22. ............................................................................56
`VII. General Plastics should not prevent institution. .......................................... 56
`VIII. Mandatory notices (37 C.F.R. §42.8(a)(1)). ................................................. 57
`IX. Conclusion. ................................................................................................... 59
`
`
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`

`
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`Petition for Inter Partes Review of U.S. Patent No. 6,518,668
`
`TABLE OF AUTHORITIES
`
`Cases
`
`Augustine Med., Inc. v. Gaymar Inds.,
`181 F.3d 1291 (Fed. Cir. 1999) ............................................................................16
`
`
`CRFD Research Inc. v. Matal,
`876 F.3d 1330 (Fed. Cir. 2017) ............................................................................46
`
`
`Cuozzo Speed Technologies, LLC v. Lee,
`136 S. Ct. 2131 (2016)..........................................................................................10
`
`
`Dynamic Drinkware, LLC v. Nat’l Graphics, Inc.,
`800 F.3d 1375 (Fed. Cir. 2015) ............................................................................16
`
`
`Eisai Co. Ltd. v. Dr. Reddy’s Labs., Ltd.,
`533 F.3d 1353 (Fed. Cir. 2008) ............................................................................46
`
`
`Eiselstein v. Frank,
`52 F.3d 1035 (Fed. Cir. 1995) ..............................................................................20
`
`
`In re Aslanian,
`590 F.2d 911 (C.C.P.A. 1979) ..............................................................................41
`
`
`KSR Int’l Co. v. Teleflex Inc.,
`127 S. Ct. 1727 (2007)..........................................................................................46
`
`
`Markman v. Westview Instruments, Inc.,
`52 F.3d 967 (Fed. Cir. 1995) ................................................................................13
`
`
`PlaSmart, Inc. v. Kappos,
`482 Fed. Appx. 568 (Fed. Cir. 2012) ...................................................................41
`
`
`PowerOasis, Inc. v. T-Mobile USA, Inc.,
`522 F.3d 1299 (Fed. Cir. 2008) ..................................................................... 17, 19
`
`
`Sinorgchem Co. et al. v. International Trade Commission,
`511 F.3d 1132 (Fed. Cir. 2007) ............................................................................13
`
`
`
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`- iv -
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 6,518,668
`
`
`Vas-Cath Inc. v. Mahurkar,
`935 F.2d 1555 (Fed. Cir. 1991) ............................................................... 16, 35, 40
`
`
`Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc.,
`200 F.3d 795 (Fed. Cir. 1999) ..............................................................................11
`
`
`Waldemar Link v. Osteonics Corp.,
`32 F.3d 556 (Fed. Cir. 1994) ................................................................................15
`
`
`Wang Labs., Inc. v. Toshiba Corp.,
`983 F.2d 858 (Fed. Cir. 1993) ..............................................................................16
`
`
`Statutes
`
`35 U.S.C. §102(a) ...................................................................................................... 3
`
`35 U.S.C. §102(b) ...................................................................................................... 3
`
`35 U.S.C. §102(e) ..................................................................................................2, 3
`
`35 U.S.C. §103 ........................................................................................................... 3
`
`35 U.S.C. §112 .........................................................................................................16
`
`35 U.S.C. §120 .........................................................................................................16
`
`35 U.S.C. §325(d) ....................................................................................................56
`
`
`Federal Regulations
`
`37 C.F.R. §42.10(a) ..................................................................................................57
`
`37 C.F.R. §42.104(a) .................................................................................................. 2
`
`37 C.F.R. §42.104(b) ................................................................................................. 2
`
`37 C.F.R. §42.8(a)(1) ...............................................................................................57
`
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`Petition for Inter Partes Review of U.S. Patent No. 6,518,668
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`
`
`37 C.F.R. §42.8(b)(3) ...............................................................................................57
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`- vi -
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`

`
`
`
`
`Exhibit
`1001
`1002
`
`1003
`1004
`1005
`1006
`
`1007
`1008
`1009
`1010
`
`1011
`1012
`
`1013
`1014
`
`1015
`
`1016
`
`1017
`
`1018
`
`1019
`1020
`
`1021
`1022
`
`Petition for Inter Partes Review of U.S. Patent No. 6,518,668
`
`EXHIBIT LIST
`
`Description
`U.S. Patent No. 6,518,668 to Cohen (“the ’668 patent”)
`Prosecution File History for Application No. 09/730,220 (“’668
`patent file history”)
`Declaration of Michael Thomas, Ph.D. (“Thomas Decl.”)
`Curriculum vitae of Michael Thomas, Ph.D.
`U.S. Patent No. 6,398,929 to Chiang et al. (“Chiang”)
`Grunow et al., “Study of Electrochemical Deposition of Copper and
`Microstructure Evolution in Fine Lines,” Proceedings of the
`Materials Research Society Symposium, January 1999 (“Grunow”)
`U.S. Patent No. 6,610,151 to Cohen (“the ’151 patent”)
`Intentionally Left Blank
`U.S. Patent No. 6,136,707 to Cohen (“the ’707 patent”)
`Reexamination File History for U.S. Patent No. 6,136,707 (“’707
`reexam”)
`U.S. Patent No. 6,228,759 to Wang et al. (“Wang”)
`Chen et al., “ECD Seed Layer for Inlaid Copper Metallization” The
`Electrochemical Society, September 1999 (“Chen”)
`U.S. Patent No. 6,146,517 to Hoinkis (“Hoinkis”)
`The New Oxford Dictionary of English, Oxford University Press,
`1998 (“Oxford Dictionary”)
`Plummer et al., Silicon VLSI Technology, Chapter 9 – Thin Film
`Deposition, Prentice-Hall Inc., 2000 (“Plummer”)
`Smith, Thin-Film Deposition, Chapter 7 – Chemical Vapor
`Deposition, McGraw-Hill, Inc., 1995 (“Smith”)
`P. Andricacos, “Copper On-Chip Interconnections, A Breakthrough
`in Electrodeposition to Make Better Chips,” The Electrochemical
`Society, Spring 1999 (“Andricacos”)
`Jackson et al., “Processing and Integration of Copper Interconnects,”
`Solid State Technology, The International Magazine for
`Semiconductor Manufacturing, March 1998. (“Jackson”)
`U.S. Patent 6,368,954 to Lopatin et al. (“Lopatin”)
`Kroger et al., “Properties of Copper Films Prepared by Chemical
`Vapor Deposition for Advanced Metallization of Microelectronic
`Devices,” Journal of the Electrochemical Society, 1999 (“Kroger”)
`U.S. Patent No. 6,126,806 to Uzoh (“Uzoh”)
`U.S. Patent No. 6,284,652 to Charneski et al. (“Charneski”)
`
`- vii -
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`

`

`
`
`Exhibit
`1023
`1024
`1025
`
`1026
`
`1027
`
`1028
`1029
`
`1030
`
`1031
`
`1032
`
`1033
`1034
`1035
`1036
`
`1037
`1038
`1039
`1040
`
`1041
`
`Petition for Inter Partes Review of U.S. Patent No. 6,518,668
`
`Description
`U.S. Patent No. 6,461,675 to Paranjpe et al. (“Paranjpe”)
`U.S. Patent No. 5,989,623 to Chen et al. (“Chen ’623”)
`Ryu et al., “Effect of Texture on the Electromigration of CVD
`Copper,” Proceedings of IEEE Int’l Reliability Physics Symposium
`1997, pp. 201-205 (“Ryu 1997”)
`Ryu et al., “Microstructure and Reliability of Copper Interconnects,”
`IEEE Transactions on Electron Devices, vol. 46, no. 6, June 1999
`(“Ryu 1999”)
`Wolf et al., Silicon Processing for the VLSI Era, Volume 1—Process
`Technology, Chapter 10 – Aluminum Thin Films and Physical Vapor
`Deposition in VLSI, Lattice Press, 1986 (“Wolf”)
`U.S. Patent No. 6,187,670 to Brown et al. (“Brown”)
`U.S. Patent Pub. Appl. No. 2002/0045345 to Hsiung et al.
`(“Hsiung”)
`G. Moore, “Cramming More Components onto Integrated Circuits,
`Proceedings of the IEEE, vol. 86, no. 1, January 1998 (“Moore”)
`The National Technology Roadmap for Semiconductors,
`Semiconductor Industry Association, 1997 (“1997 NTRS”)
`M. Thomas et al., “Chapter 10 - Overview of Interconnect” in Y.
`Nishi et al., (ed): “Handbook of Semiconductor Manufacturing
`Technologies,” Marcel Dekker, Inc., New York, 2000 (“Handbook”)
`U.S. Patent No. 6,297,155 to Simpson et al. (“Simpson”)
`U.S. Patent No. 6,977,220 to Marieb et al. (“Marieb”)
`U.S. Patent No. 6,242,349 to Nogami et al. (“Nogami”)
`C. Wang et al., “Binary Cu-Alloy Layers for Cu-Interconnections
`Reliability Improvement,” Proceedings of the IEEE 2001
`International Interconnect Technology Conference, June 2001, pp.
`86-88 (“Wang Article”)
`Exhibit 1037: U.S. Patent No. 6,069,068 to Rathore et al. (“Rathore”)
`U.S. Patent No. 6,562,715 to Chen et al. (“Chen ’715”)
`EP 0818817 to Satitpunwaycha (“Satitpunwaycha”)
`Tanaka et al., “Properties of titanium nitride film deposited by
`ionized metal plasma source,” Journal of Vacuum Science &
`Technology B: Microelectronics and Nanometer Structures
`Processing, Measurement, and Phenomena 17, 416 (1999)
`(“Tanaka”)
`U.S. Patent No. 6,183,614 to Fu (“Fu”)
`
`
`
`- viii -
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`

`

`
`
`Exhibit
`1042
`
`1043
`1044
`1045
`1046
`
`Petition for Inter Partes Review of U.S. Patent No. 6,518,668
`
`Description
`Prosecution File History of U.S. Patent Application No. 14/619,334
`(“’334 file history”)
`U.S. Patent No. 6,399,479 to Chen et al. (“Chen ’479”)
`Declaration of James L. Mullins, Ph.D.
`Declaration of Tom Ritzdorf
`Intentionally Left Blank
`
`
`
`- ix -
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`Petition for Inter Partes Review of U.S. Patent No. 6,518,668
`
`Introduction.
`
`
`I.
`
`Petitioner Taiwan Semiconductor Manufacturing Co., Ltd. (“TSMC”)
`
`petitions for inter partes review of claims 17–20 and 22 (“challenged claims”) of
`
`U.S. Patent No. 6,518,668 (Exhibit 1001, “’668 patent”). The challenged claims
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`recite well-known techniques for making interconnects of an integrated circuit
`
`(IC). The only purported novelty of Patent Owner’s interconnects is the deposition
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`of more than one seed layer using different deposition techniques when forming
`
`the interconnect. However, using more than one seed layer deposited using
`
`different deposition techniques was known or obvious prior to the ’668 patent. The
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`Board previously found claims that recited this feature unpatentable in a
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`reexamination filed against the first patent in the family of the ’668 patent, U.S.
`
`Patent No. 6,136,707. (Exhibit 1009.)
`
`The challenged claims of the ’668 patent recite only minor variations on the
`
`two-seed layer deposition that the Board previously found unpatentable. Namely,
`
`the challenged claims recite that the seed layers are “substantially conformal seed
`
`layer” and “substantially non-conformal seed layer,” terms that Patent Owner,
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`defines, for the first time, in the ’668 patent. But these limitations are also known
`
`or obvious. U.S. Patent No. 6,228,759 to Wang et al. (Exhibit 1011) disclose a
`
`multiple seed layer interconnect structure with seed layer thicknesses within the
`
`scope of the challenged claims. This Petition, supported by the Expert Declaration
`
`
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`- 1 -
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`

`Petition for Inter Partes Review of U.S. Patent No. 6,518,668
`
`
`of Dr. Michael Thomas, who has over three decades of experience in
`
`semiconductor interconnect design and fabrication, establishes that the challenged
`
`claims are unpatentable over the prior art. TSMC respectfully requests that the
`
`Board cancel the challenged claims.
`
`II. Grounds for standing (37 C.F.R. §42.104(a)).
`The undersigned and TSMC certify that the ’668 patent is available for inter
`
`partes review. TSMC certifies that it is not barred or estopped from requesting this
`
`inter partes review on the grounds identified herein.
`
`III.
`
`Identification of challenge (37 C.F.R. §42.104(b)).
`A. Citation of prior art.
`TSMC demonstrates in Section IV.E that the challenged claims of the ’668
`
`patent are not entitled to priority of U.S. Patent No. 6,610,151 (“’151 patent”) or
`
`U.S. Patent No. 6,136,707 (“’707 patent”). Therefore, the presumptive invention
`
`date of the ’668 patent is its December 4, 2000 filing date. In support of the
`
`grounds of unpatentability below, TSMC cites the following prior art references,
`
`each filed or published before December 4, 2000:
`
`U.S. Patent No. 6,228,759 to Wang et al. (“Wang”), provided as Exhibit
`
`1011, is prior art under at least 35 U.S.C. §102(e) because it was filed on May 2,
`
`2000.
`
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`- 2 -
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`

`
`
`Petition for Inter Partes Review of U.S. Patent No. 6,518,668
`
`“ECD Seed Layer for Inlaid Copper Metallization” to Chen et al.
`
`(“Chen”), provided as Exhibit 1012, is prior art under at least 35 U.S.C. §§102(a)
`
`and 102(b) because it was published prior to June 22, 1999.1,2
`
`U.S. Patent No. 6,146,517 to Hoinkis (“Hoinkis”), provided as Exhibit
`
`1013, is prior art under at least 35 U.S.C. §§102(a) and 102(e) because it was filed
`
`on May 19, 1999 and issued November 14, 2000.
`
`B. Statutory grounds for the challenge.
`TSMC requests review on the following grounds:
`
`• Wang in combination with Chen renders claims 17 and 19 obvious
`
`under 35 U.S.C. §103.
`
`• Wang in combination with Hoinkis renders claims 18, 20, and 22
`
`obvious under 35 U.S.C. §103.
`
`None of the cited prior art in the proposed grounds was applied in a rejection
`
`against the challenged claims.
`
`1 Dr. Mullins, a librarian with 44 years of experience, testifies that Chen is
`
`authentic (Exhibit 1044, ¶¶37-38, citing Appendix C1) and was publicly available
`
`on or before June 21, 1999 based on his review of Library of Congress
`
`documentation. (Id., ¶¶39-42, citing Appendix C2 and C3).
`
`2 Mr. Ritzdorf, a co-author of Chen, testifies that Chen was publicly
`
`available at least as of November 1999. (Exhibit 1045, ¶¶11-13).
`
`
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`Petition for Inter Partes Review of U.S. Patent No. 6,518,668
`
`
`IV. The ’668 patent.
`A. Background of technology.
`The ’668 patent generally relates to interconnect structures for
`
`
`
`semiconductor devices. (’668 patent, Abstract.) As recognized in the ’668 patent, a
`
`well-known method to form interconnect structures is the “damascene” process,
`
`introduced by IBM in the 1990s. (Exhibit 1003, Thomas Decl., ¶¶27-32; ’668
`
`patent, 1:26-32.) In a damascene process, a dielectric is deposited onto a
`
`semiconductor substrate to serve as an insulating underlayer. (Thomas Decl., ¶¶33-
`
`34.) The damascene process first forms openings (e.g., vias and/or trenches) in a
`
`dielectric layer and then fills those openings with one or more layers of conductive
`
`material.3 (Id.)
`
`In the first step of the damascene process, illustrated below, an opening is
`
`formed in the dielectric layer over an underlying layer. (Id., ¶¶35-36, Figure A.)
`
`
`3 The damascene process is described in the context of a “single damascene
`
`process,” in which a via or trench opening is formed in the dielectric layer and then
`
`filled with one or more layers of conductive material. (Thomas Decl., ¶37.)
`
`
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`

`
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`Petition for Inter Partes Review of U.S. Patent No. 6,518,668
`
`Example Opening
`
`In the second step, illustrated below, a barrier layer is deposited on the inside
`
`
`
`surfaces (sidewalls and bottom) of the opening as well as the top surfaces
`
`surrounding the opening (known as the “field”). (Id., ¶¶38-39, Figure C.) The
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`barrier layer serves to prevent metal (e.g., copper) from diffusing into the dielectric
`
`and underlying layers. (Id.)
`
`opening
`
`barrier layer
`
`dielectric layer
`
`underlying layer
`
`
`Example Barrier Layer over Dielectric Layer
`
`In the third step, illustrated below, one or more seed layers are deposited on
`
`the barrier layer. (Id., ¶¶40-41, Figure D.) The seed layer can be deposited by
`
`various well-known techniques including plating, physical vapor deposition
`
`(PVD), and/or chemical vapor deposition (CVD). (Id., ¶¶42-53.)
`
`
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`

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`Petition for Inter Partes Review of U.S. Patent No. 6,518,668
`
`opening
`
`seed layer
`barrier layer
`dielectric layer
`
`underlying layer
`
`
`
`Example Seed Layer over Barrier Layer
`
`In the fourth step, illustrated below, an electroplating process fills the
`
`opening with a conductive material (e.g., copper). (Id., ¶¶54-55, Figure E.) The
`
`conductive material plates are on the inside surfaces (sidewalls and bottom) of the
`
`opening as well as on the top surfaces surrounding the opening (the field) where
`
`the surfaces of the one or more seed layers are exposed. (Id.) A challenge in the
`
`electroplating process is to fill the opening without voids, which are areas depleted
`
`of the conductive material. (Id.)
`
`plated copper
`
`seed layer
`barrier layer
`dielectric layer
`
`underlying layer
`
`
`
`
`
`
`
`Example Electroplating Process
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`Petition for Inter Partes Review of U.S. Patent No. 6,518,668
`
`In the fifth step, illustrated below, excess plated metal, seed layer, and
`
`barrier layer material on the field of the opening, are polished away using, for
`
`example, a chemical mechanical polishing (“CMP”) technique. (Id., ¶56, Figure F.)
`
`final interconnect structure
`
`dielectric layer
`
`underlying layer
`
`
`
`Example Interconnect
`
`B. The ’668 patent purports to improve interconnect structures by
`depositing multiple seed layers on surfaces of interconnect openings.
`
`To achieve a void-free copper interconnect structure, according to the ’668
`
`patent, a seed layer should provide continuous coverage on the inside surfaces of
`
`an interconnect opening. (’668 patent, 3:35–39; Thomas Decl., ¶¶57-59.) At the
`
`same time, according to the ’668 patent, to ensure a uniform electroplating process
`
`across the wafer, the seed layer must be sufficiently thick on the field (i.e., the top
`
`surface of the wafer outside trenches and via openings). (’668 patent, 2:11–12,
`
`3:44–62; Thomas Decl., ¶¶57-59.) As the demand for smaller interconnect
`
`structures increases due to the demand for smaller ICs, these two factors—
`
`continuous seed layer coverage and sufficient seed layer thickness—pose
`
`
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`

`Petition for Inter Partes Review of U.S. Patent No. 6,518,668
`
`
`challenges in interconnect design and fabrication. (’668 patent, 3:32–62; Thomas
`
`Decl., ¶¶57-59.)
`
`The ’668 patent purports to address these challenges by providing an
`
`interconnect structure formed using a two seed layer deposition process. (Thomas
`
`Decl., ¶60.) However, using more than one seed layer deposited using different
`
`deposition techniques was known or obvious prior to the’668 patent.4
`
`In Figure 1, reproduced below with annotations, a barrier layer 18 (shown in
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`yellow) is first deposited over a wafer 10 having an insulating layer 12 patterned to
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`include an opening 16, such that barrier layer 18 covers the sidewalls and bottom
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`of opening 16 as well as field 14. (’668 patent, 5:48–54; Thomas Decl., ¶66.)
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`Following deposition of barrier layer 18, a first seed layer 20 (shown in red) is
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`deposited over sidewall and bottom surfaces of opening 16 as well as over field 14.
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`(’668 patent, 6:25–34; Thomas Decl., ¶67.) In the embodiment of Figure 1, the first
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`seed layer is “substantially conformal,” which the ’668 patent defines as “a layer
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`whose thickness on the sidewalls of an opening (at about mid-depth) is about 25-
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`4 The Board previously found claims reciting a method for forming a
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`metallic interconnect that deposited a first conformal seed layer by CVD and a
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`second non-conformal seed layer by PVD unpatentable in a reexamination filed
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`against the first patent in the family of the ’668 patent, U.S. Patent No. 6,136,707.
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`(Exhibit 1009.)
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`Petition for Inter Partes Review of U.S. Patent No. 6,518,668
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`100% of its thickness on the field.” (’668 patent, 5:15–18; Thomas Decl., ¶67.)
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`The “substantially conformal seed layer” can be “a material selected from Cu, Ag,
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`or alloys comprising one or more of these metals” and is “preferably deposited by
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`using a CVD technique.” (’668 patent, 6:26–29, 6:51–52; Thomas Decl., ¶67.)
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`Annotated Figure 1 of the ’668 Patent
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`
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`A second seed layer 22 (shown in green) is then deposited over the first
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`substantially conformal seed layer 20. (’668 patent, 6:34–42; Thomas Decl., ¶67.)
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`In the embodiment of Figure 1, the second seed layer is “substantially non-
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`conformal,” which the ’668 patent defines as “a layer whose thickness on the
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`sidewalls of an opening (at about mid-depth) is less than about 25% of its thickness
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`on the field.” (’668 patent, 5:18–22; Thomas Decl., ¶67.) The “substantially non-
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`conformal seed layer” can be “a material selected from Cu, Ag, or alloys
`
`comprising one or more of these metals” and is “preferably obtained using a PVD
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`technique.” (’668 patent, 6:26–29, 6:36–37, 6:51–52; Thomas Decl., ¶67.) After
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`Petition for Inter Partes Review of U.S. Patent No. 6,518,668
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`the deposition of both seed layers, the remainder of opening 16 is filled with a
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`metal using an electroplating process. (’668 patent, 7:46–52, 7:66–8:6; Thomas
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`Decl., ¶67.)
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`In other embodiments, the ’668 patent discloses that a third seed layer can be
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`deposited over or under the seed layer structures shown in Figure 1. (’668 patent,
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`11:26-33, 15:9-18, Thomas, ¶68.) For example, in referring to the two seed layer
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`structure in Figure 1 above, a “second deposited CVD seed layer” is formed over
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`substantially non-conformal seed layer 22 to form a three seed layer structure.
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`(’668 patent, 15:9-18.) Further, in referring to the two seed layer structure in
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`Figure 1 above, “a relatively thin (“Flash”) PVD seed layer” is formed under
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`substantially conformal seed layer 20 to form another three seed layer structure.
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`(’668 patent, 11:26-43.)
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`C. Claim construction.
`The claim terms should be given their plain meanings according to the
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`broadest reasonable interpretation in light of the specification.5 Cuozzo Speed
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`Technologies, LLC v. Lee, 136 S. Ct. 2131 (2016) (claims in an unexpired patent
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`must be given their broadest reasonable interpretation in light of the specification).
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`Except where noted below, TSMC does not believe that it is necessary for the
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`5 TSMC reserves the right to present different constructions in other forums
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`(e.g., a District Court) where a different claim construction standard applies.
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`Petition for Inter Partes Review of U.S. Patent No. 6,518,668
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`Board to expressly construe any terms for the purposes of this IPR proceeding. See
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`Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999)
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`(holding that “only those terms need be construed that are in controversy, and only
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`to the extent necessary to resolve the controversy,” and noting that “the stage at
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`which the claims are construed may vary with the issues, their complexity, the
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`potentially dispositive nature of the construction, and other considerations of the
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`particular case.”).
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`1. “seed layer”
`The term “seed layer” was a recognized term of art in semiconductor
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`fabrication at the time of the alleged invention of the challenged claims. Should the
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`Board determine that an express construction of this term would be helpful, a
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`POSITA as of the earliest possible priority date of the ’668 patent would have
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`understood the broadest reasonable interpretation of “seed layer” to refer to an
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`electrically conductive layer that facilitates growth of a conductive material.
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`(Thomas Decl., ¶69.)
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`2. “substantially conformal seed layer” / “substantially non-
`conformal seed layer”
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`Because Patent Owner acted as its own lexicographer, the broadest
`
`reasonable interpretation for the term “substantially conformal seed layer” is “a
`
`layer whose thickness on the sidewalls of an opening (at about mid-depth) is about
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`25-100% of its thickness on the field.” (Id., ¶70.) And, the broadest reasonable
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`Petition for Inter Partes Review of U.S. Patent No. 6,518,668
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`interpretation for the term “substantially non-conformal seed layer” is “a layer
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`whose thickness on the sidewalls of an opening (at about mid-depth) is less than
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`25% of its thickness on the field.” (Id., ¶71.)
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`Patent Owner explicitly defined these terms in the ’668 patent specification
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`and therefore acted as its own lexicographer. See MPHJ Technology Investments,
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`LLC v. Ricoh Americas Corp., 847 F.3d 1363, 1374 (Fed. Cir. 2017) (“To act as a
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`lexicographer, a patentee must ‘clearly set forth a definition of the disputed claim
`
`term’ and ‘clearly express an intent to redefine the term.’”) (citation omitted). The
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`Patent Owner definitively stated:
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`As defined herein6, a “substantially conformal seed layer” is a
`layer whose thickness on the sidewalls of an opening (at about
`mid-depth) is about 25-100% of its thickness on the field.
`
`(’668 patent, 5:15–18.)
`
`Similarly, a “substantially non-conformal seed layer” is defined
`herein as a layer whose thickness on the sidewalls of an opening
`(at about mid-depth) is less than about 25% of its thickness on the
`field.
`
`(Id., 5:18–22.)
`
`
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`By stating “[a]s defined herein” and “is defined herein as,” Patent Owner
`
`clearly expressed an intent to define “substantially conformal seed layer” and
`
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`6 All emphasis has been added herein, unless indicated otherwise.
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`“substantially non-conformal seed layer.” Markman v. Westview Instruments, Inc.,
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`52 F.3d 967, 980 (Fed. Cir. 1995) (“As we have often stated, a patentee is free to
`
`be his own lexicographer. The caveat is that any special definition given to a word
`
`must be clearly defined in the specification.”) (citations omitted).
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`Further, Patent Owner used quotation marks to offset the terms
`
`“substantially conformal seed layer” and “substantially non-conformal seed layer”
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`which is a strong indication that what follows is a definition. Sinorgchem Co. et al.
`
`v. International Trade Co