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`US 20040106234Al
`
`(19) United States
`(12) Patent Application Publication
`Sorg et al.
`
`(10) Pub. No.: US 2004/0106234 Al
`Jun. 3, 2004
`(43) Pub. Date:
`
`(54) ELECTRICAL LEADFRAMES, SURFACE
`MOUNTABLE SEMICONDUCTOR
`COMPONENTS, LEADFRAME STRIPS, AND
`THEIR METHOD OF MANUFACTURE
`
`(76)
`
`Inventors: Joerg-Erich Sorg, Regensburg (DE);
`Gertrud Kraeuter, Regensburg (DE)
`
`Correspondence Address:
`FISH & RICHARDSON P.C.
`3300 DAIN RAUSCHER PLAZA
`MINNEAPOLIS, MN 55402 (US)
`
`(21) Appl. No.:
`
`10/635,937
`
`(22) Filed:
`
`Aug. 5, 2003
`
`Related U.S. Application Data
`
`(60) Provisional application No. 60/401,273, filed on Aug.
`5, 2002.
`
`(30)
`
`Foreign Application Priority Data
`
`Feb. 17, 2003
`
`(DE) .................................. 10306557.1-33
`
`Publication Classification
`
`(51)
`
`Int. Cl.7 ..................................................... H0lL 21/44
`
`(52) U.S. Cl. .............................................................. 438/123
`
`(57)
`
`ABSTRACT
`
`The invention relates to a method for producing an electrical
`leadframe (10), in particular for a light-emitting diode
`component, having at least one first electrical connection
`conductor (2) and at least one second electrical connection
`conductor (3). The method includes a) production of a layer
`composite comprising an electrically insulating carrier layer
`(101) and an electrically conductive connection conductor
`layer (102), b) patterning of the carrier layer (101) in such
`a way that at least one contact-making window (7) toward
`the connection conductor layer (102) is produced in said
`carrier layer, and c) patterning of the connection conductor
`layer (102), in such a way that the first electrical connection
`conductor (2) and the second electrical connection conduc(cid:173)
`tor (3) are produced, at least one of which can be electrically
`connected through the contact-making window (7). The
`invention also relates to a leadframe strip having a connec(cid:173)
`tion conductor layer and a connection carrier layer, on which
`an array with a multiplicity of component regions is formed,
`the connection conductor layer being at least partly removed
`along separating lines between two adjacent component
`regions.
`
`1
`
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`11
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`9
`
`VIZIO Ex. 1024 Page 00001
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`

`

`Patent Application Publication
`
`Jun. 3, 2004 Sheet 1 of 6
`
`US 2004/0106234 Al
`
`FIG 1
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`FIG 2
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`VIZIO Ex. 1024 Page 00002
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`Patent Application Publication
`
`Jun. 3, 2004 Sheet 2 of 6
`
`US 2004/0106234 Al
`
`FIG 3A
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`VIZIO Ex. 1024 Page 00003
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`

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`Patent Application Publication
`
`Jun. 3, 2004 Sheet 3 of 6
`
`US 2004/0106234 Al
`
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`VIZIO Ex. 1024 Page 00004
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`

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`Patent Application Publication
`
`Jun. 3, 2004 Sheet 4 of 6
`
`US 2004/0106234 Al
`
`FIG SA
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`VIZIO Ex. 1024 Page 00005
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`

`

`Patent Application Publication
`
`Jun. 3, 2004 Sheet 5 of 6
`
`US 2004/0106234 Al
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`VIZIO Ex. 1024 Page 00006
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`

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`Patent Application Publication
`
`Jun. 3, 2004 Sheet 6 of 6
`
`US 2004/0106234 Al
`
`500
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`
`FIG 7
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`VIZIO Ex. 1024 Page 00007
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`

`

`US 2004/0106234 Al
`
`Jun.3,2004
`
`1
`
`ELECTRICAL LEADFRAMES, SURFACE
`MOUNTABLE SEMICONDUCTOR COMPONENTS,
`LEADFRAME STRIPS, AND THEIR METHOD OF
`MANUFACTURE
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`[0001] This application claims priority to U.S. Provisional
`Application Serial No. 60/401,273, filed on Aug. 5, 2003.
`
`TECHNICAL FIELD
`
`[0002] The invention relates to a method for producing an
`electrical leadframe, such as a leadframe for a surfacemount(cid:173)
`able semiconductor component having a semiconductor
`chip, at least two external electrical connections, which are
`electrically conductively connected to at least two electrical
`contacts of the semiconductor chip, and a chip encapsula(cid:173)
`tion. The invention also relates to a leadframe strip and a
`method for producing a surface-mountable semiconductor
`component.
`
`BACKGROUND
`
`[0003]
`In order to expand the areas of use and in order to
`reduce the production costs, attempts are made to produce
`semiconductor components in ever smaller structural sizes.
`By way of example, the backlighting of the keys of mobile
`telephones requires very small light-emitting diodes.
`[0004] Light-emitting diode housings with an installation
`area dimensioned as 0402 (corresponding to 0.5 mmxl.0
`mm) and a device height of 400 µm-600 µm have become
`available in the meantime. Such a housing is described in the
`data sheet from FAIRCHILD SEMICONDUCTOR® con(cid:173)
`cerning the QTLP690C-x design. The corresponding device
`concept is described in the document U.S. Pat. No. 4,843,
`280.
`[0005] A further reduction of the device height is desir(cid:173)
`able, but is extremely difficult with the conventionally
`available housing concepts.
`
`SUMMARY
`
`[0006] The present invention is based on the object of
`providing a concept for a surfacemountable semi-conductor
`component, in particular for surfacemountable miniature
`light-emitting diode and/or photodiode components, which
`permits the structural size, in particular the structural height,
`to be reduced more extensively.
`[0007]
`In one aspect, the invention is directed to a method
`for producing an electrical leadframe (10) for a light(cid:173)
`emitting diode component, the electrical leadframe having at
`least one first electrical connection conductor (2) and at least
`one second electrical connection conductor (3). The method
`includes producing a layer composite comprising an elec(cid:173)
`trically insulating carrier layer (101) and an electrically
`conductive connection conductor layer (102), patterning of
`the carrier layer (101) in such a way that a contact-making
`window (7) to the connection conductor layer (102) is
`produced in said carrier layer, and c) patterning of the
`connection conductor layer (102) in such a way that the first
`electrical connection conductor (2) and the second electrical
`connection conductor (3) are produced. At least one of first
`
`and second electrical connection conductors can be electri(cid:173)
`cally connected through the contact-making window (7).
`
`[0008]
`In another aspect, the invention is directed to a
`method for producing a surfacemountable semiconductor
`component having at least one semiconductor chip (1), at
`least two external electrical connection conductors (2, 3),
`which are connected to at least two electrical contacts ( 4, 5)
`of the semiconductor chip (1), and having a chip housing
`(11) having a connection carrier (9) and a chip encapsulation
`(6). The method includes applying an electrically insulating
`carrier layer (101) to an electrically conductive connection
`conductor layer (102), patterning at least one chip window
`(7) and at least one wire connection window (8) in the carrier
`layer (101), patterning the external electrical connection
`conductors (2,3) into the connection conductor layer (102),
`mounting the semiconductor chip (1) into the chip window
`(7), electrically connecting at least one electrical contact (5)
`of the semiconductor chip (1) to a connection conductor (3)
`by means of a bonding wire (50) through the wire connec(cid:173)
`tion window (8), placing the composite comprising pat(cid:173)
`terned connection conductor layer (102), patterned carrier
`layer (101), semiconductor chip (1) and bonding wire (50)
`into an injection mold, and encapsulating the semiconductor
`chip (1) including bonding wire (50) with an encapsulation
`material (6) by injection molding, which material is subse(cid:173)
`quently at least partly cured or incipiently cured.
`
`[0009]
`In another aspect, the invention is directed to a
`method for producing a surfacemountable semiconductor
`component having at least one semiconductor chip (1), at
`least two external electrical connection conductors (2, 3),
`which are connected to at least two electrical contacts ( 4, 5)
`of the semiconductor chip (1), and having a chip housing
`(11) having a connection carrier (9) and a chip encapsulation
`(6). The method includes applying an electrically insulating
`carrier layer (101) to an electrically conductive connection
`conductor layer (102), patterning at least one chip window
`(7) in the carrier layer (101 ), patterning the external elec(cid:173)
`trical connection conductors (2, 3) into the connection
`conductor layer (102) with the two connection conductors
`(2, 3) partly overlapping the chip window (7), mounting the
`semiconductor chip onto the external electrical connection
`conductors (2, 3) in the chip window (7) in such a way that
`a first contact ( 4) and a second contact (5) of the semicon(cid:173)
`ductor chip (1) bear on the first (2) and, respectively, on the
`second of the two connection conductors (3) and are elec(cid:173)
`trically connected thereto, placing the composite comprising
`patterned connection conductor layer (102), patterned car(cid:173)
`rier layer (101) and semiconductor chip (1) into an injection
`mold (500), and encapsulating the semiconductor chip (1)
`with an encapsulation material (6) by injection molding,
`which material is subsequently at least partly cured or
`incipiently cured.
`
`[0010]
`In another aspect, the invention is directed to a
`leadframe strip (200) having a connection conductor layer
`(102) and a carrier layer (101), on which an array (201) with
`a multiplicity of component regions (202) is formed, the
`connection conductor layer (101) being at least partly
`removed along separating lines (110) between adjacent
`component regions (202).
`
`[0011]
`In the case of the method, firstly a laminate having
`an electrically insulating carrier layer and an electrically
`conductive connection conductor layer is produced. This
`
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`

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`US 2004/0106234 Al
`
`Jun.3,2004
`
`2
`
`laminate may consist solely of these two layers. They may
`be connected to one another by means of an adhesive layer,
`for example, and may, moreover, be completely unpatterned.
`In a subsequent step, in each component section of the
`laminate, at least one contact-making window toward the
`connection conductor layer may be produced in the carrier
`layer and at least one first electrical connection track and at
`least one second electrical connection track may be formed
`in the connection conductor layer. At least one of the tracks
`may be electrically connected through the contact-making
`window.
`
`[0012] This electrical leadframe may be suitable for light(cid:173)
`emitting diode components having an extremely small struc(cid:173)
`tural height of the component housing in relation to the
`height of the light-emitting diode chip. This leadframe may
`enable effective heat dissipation from the light-emitting
`diode chip if the latter is mounted directly onto a connection
`track in a contact-making window of the carrier layer by
`means of a thermally conductive joining agent, such as
`conductive adhesive or metallic solder.
`
`[0013] The patterning of the carrier layer may take place
`before the patterning of the connection conductor layer.
`However, this sequence can also be reversed.
`
`[0014] The carrier layer may be a plastic layer that can be
`patterned by means of masking and etching techniques. In
`particular the carrier layer may be a plastic film, such as a
`polyimide film. The connection conductor layer is an elec(cid:173)
`trically conductive film that can be patterned by means of
`masking and etching techniques. In particular the conductor
`layer may be a metal film. The thicknesses of the carrier
`layer and of the connection conductor layer may be less than
`80 µm, and in particular may be between from and including
`30 µm and up to and including 60 µm.
`
`[0015] A first contact-making window, for example a chip
`mounting window, toward the first connection track, and a
`second contact-making window, for example a wire connec(cid:173)
`tion window, toward the second connection track, are
`formed in the carrier layer.
`
`[0016]
`In one embodiment of the method, the carrier layer
`initially preferably comprises a soluble plastic layer, at least
`in the regions to be patterned. This carrier layer is made
`insoluble, such as by incipient curing or curing, except for
`the areas of the contact-making windows and, if appropriate,
`other regions that are subsequently to be removed again.
`This means that in these regions it is then resistant to the
`solvent for the plastic layer. The contact-making windows
`and, if appropriate, other regions to be uncovered are
`subsequently etched free.
`
`[0017] For the patterning of the plastic layer, firstly a mask
`layer, in particular a photoresist layer, can be applied thereto.
`The photoresist layer can be patterned or applied in pat(cid:173)
`terned fashion in such a way that the regions of the contact(cid:173)
`making windows and other regions that are subsequently to
`be removed are covered by the mask layer. The plastic layer
`can be subsequently cured in the uncovered regions which
`are intended to remain on the connection conductor layer,
`before the photoresist layer and the underlying plastic layer
`are then removed from the connection conductor layer at
`least in the regions of the contact-making windows. The
`uncured plastic layer can be removed from the connection
`conductor layer by being dissolved.
`
`[0018]
`In another embodiment of the method, for the
`patterning of the plastic layer, firstly a photomask is posi(cid:173)
`tioned above or on said plastic layer, which photomask
`shades the regions of the contactmaking windows. The
`plastic layer is then incipiently cured or cured in unshaded
`regions which are intended to remain on the connection
`conductor layer. For this purpose, the plastic layer can
`preferably be cured by means of UV radiation. Material
`containing polyimide monomer may be suitable for this
`purpose. As an alternative, it is possible to use a plastic layer
`that can be cured by means of thermal radiation. The
`photomask layer is subsequently lifted off and the plastic
`layer is removed from the connection conductor layer in the
`regions of the contact-making windows. This can be done
`once again by means of wet-chemical dissolving. The use of
`a plasma incineration method is conceivable as an alterna(cid:173)
`tive.
`
`[0019] The connection conductor layer likewise can be
`patterned by means of a mask and a wet-chemical etching
`method. Such patterning methods for metal layers, for
`example, are known from printed circuit board technology
`and are suitable, in principle, in the present case. Therefore,
`they will not be explained in any further detail at this point.
`
`[0020] As a potential advantage, the patterning methods
`that have been outlined can be incorporated in a simple
`manner into existing production methods for semiconductor
`components and can even at least partly utilize already
`existing techniques that are often used in the production of
`semiconductor components.
`
`[0021]
`In a method for producing a leadframe strip having
`a multiplicity of component sections, a multiplicity of con(cid:173)
`tact-making windows and a multiplicity of electrical con(cid:173)
`nection tracks assigned to said contact-making windows are
`produced in a laminate strip, which can comprise a metal
`film as connection conductor layer and a polyimide film as
`carrier layer, by means of a method as described above. The
`contact making windows reach as far as onto the connection
`tracks. A respective group comprising contact-making win(cid:173)
`dow and assigned connection tracks is situated in a compo(cid:173)
`nent section within an array comprising a multiplicity of
`component sections arranged next to one another on the
`laminate strip.
`
`[0022]
`In one embodiment, the connection conductor layer
`is at least partly removed along separating lines between in
`each case two adjacent component regions. This measure
`can facilitate the severing of the laminate strip along the
`separating lines, which is done by sawing or stamping, by
`way of example.
`
`[0023] The method according to the invention can be
`suitable for producing surface-mountable semiconductor
`components having in each case at least one semiconductor
`chip, at least two external electrical connection conductors,
`which are connected to at least two electrical contacts of the
`semiconductor chip, and having a plastic housing which
`encapsulates the semiconductor chip.
`
`[0024]
`In this case, in a first embodiment, firstly an
`electrical insulating carrier layer is applied to an electrically
`conductive connection conductor layer. Afterward, at least
`one chip window and at least one wire connection window
`are formed in the carrier layer and at least two external
`electrical connection conductors are formed in the connec-
`
`VIZIO Ex. 1024 Page 00009
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`

`

`US 2004/0106234 Al
`
`Jun.3,2004
`
`3
`
`tion conductor layer. Later the semiconductor chip is
`mounted into the chip window and at least one electrical
`contact of the semiconductor chip is electrically connected
`to a connection conductor by means of a bonding wire
`through the wire connection window. The composite com(cid:173)
`prising patterned connection conductor layer, patterned car(cid:173)
`rier layer, semiconductor chip and bonding wire is then
`placed into an injection mold, in which the semiconductor
`chip including bonding wire is then encapsulated with an
`encapsulation material by injection molding, which material
`is subsequently at least partly incipiently cured or cured.
`
`[0025]
`In such a method for simultaneously producing a
`multiplicity of semiconductor components, arrays with in
`each case a multiplicity of component regions are produced
`in a laminate strip having a connection conductor layer and
`a carrier layer, in which arrays each component region has
`at least one chip window, at least one wire connection
`window and at least two external electrical connection
`conductors. A multiplicity of semiconductor chips are
`mounted into the multiplicity of chip windows. The electri(cid:173)
`cal contacts of the semiconductor chips are then connected
`to the external electrical connection conductors by means of
`bonding wires through the wire connection windows. The
`arrays are subsequently placed into an injection mold indi(cid:173)
`vidually or in groups one after the other, which injection
`mold has, for each array, a single cavity which spans all the
`component regions of the array and forms a void there
`essentially exclusively on the side of the semiconductor
`chips. Encapsulation material is then introduced into the
`cavity by injection molding and is at least partly cured there.
`The array is subsequently removed from the injection mold
`and singulated into mutually separate semiconductor com(cid:173)
`ponents by severing the encapsulation material, the carrier
`layer and, if still necessary, the connection conductor layer.
`
`[0026]
`In a second embodiment, likewise firstly an elec(cid:173)
`trically insulating carrier layer is applied to an electrically
`conductive connection conductor layer. Afterward, at least
`one chip window is formed in the carrier layer and at least
`two external electrical connection conductors are formed in
`the connection conductor layer, which connection conduc(cid:173)
`tors partly overlap the chip window. This structure is suit(cid:173)
`able for example for semiconductor chips in which at least
`two electrical contacts are arranged on the same side. Such
`a chip is mounted in the chip window with the contacts onto
`the external electrical connection conductors and electrically
`connected. This composite comprising patterned connection
`conductor layer, patterned carrier layer and semiconductor
`chip is subsequently placed into an injection mold, in which
`the semiconductor chip is then encapsulated with an encap(cid:173)
`sulation material by injection molding, which material is
`subsequently at least partly incipiently cured or cured.
`
`[0027]
`In such a method for simultaneously producing a
`multiplicity of semiconductor components, arrays with in
`each case a multiplicity of component regions are produced
`in a laminate strip having a connection conductor layer and
`a carrier layer, in which arrays each component region has
`at least one chip window and at least two external electrical
`connection conductors. In each case at least one semicon(cid:173)
`ductor chip is mounted into the chip windows as described
`above. The arrays are encapsulated and singulated in the
`same way as already described further above.
`
`[0028] The method according to the invention is especially
`suitable for producing light-emitting diode components in
`which light-emitting diode chips are mounted onto the
`leadframe.
`[0029]
`In a leadframe strip having a connection conductor
`layer (preferably made of a patterned metal film) and a
`carrier layer (preferably a patterned plastic film in particular
`made of polyimide material), on which an array with a
`multiplicity of component regions is formed, the connection
`conductor layer is at least partly removed along separating
`lines between two adjacent component regions. This can
`facilitate the severing of the leadframe after the encapsula(cid:173)
`tion of the array of semiconductor components.
`[0030] The contact-making windows enable particularly
`simple monitoring of the alignment of the chip mounting
`installation and the wire bonding installation. An impermis(cid:173)
`sibly large misalignment of the chip mounting installation
`and/or wire mounting installation can be rapidly identified
`because the semiconductor chips and/or connection wires do
`not adhere on the film after their mounting if they settle on
`the edge of the contact-making windows. This is all the more
`important, the smaller the design, because firstly the reli(cid:173)
`ability of the components is impaired by misalignment of the
`chip mounting all the more, the smaller the volume of the
`chip encapsulation, and secondly the quantity of rejects is
`very high in the event of misalignment that is not immedi(cid:173)
`ately identified, on account of the high packing density of
`the components and the associated large quantity of com(cid:173)
`ponents per unit length on a leadframe tape.
`[0031] The details of one or more embodiments of the
`invention are set forth in the accompanying drawings and
`the description below. Other features, objects, and advan(cid:173)
`tages of the invention will be apparent from the description
`and drawings, and from the claims.
`
`DESCRIPTION OF DRAWINGS
`[0032] FIG. 1 shows a diagrammatic sectional illustration
`of a first exemplary embodiment for a semiconductor com(cid:173)
`ponent produced by the method according to the invention;
`[0033] FIG. 2 shows a diagrammatic sectional illustration
`of a second exemplary embodiment for a semiconductor
`component produced by the method according to the inven(cid:173)
`tion;
`[0034] FIGS. 3a to 3/ show a diagrammatic illustration of
`a first exemplary embodiment for a method sequence
`according to the invention;
`[0035] FIGS. 4a to 4e show a diagrammatic illustration of
`a second exemplary embodiment for a method sequence
`according to the invention;
`[0036] FIGS. Sa and Sb show a diagrammatic plan view
`from below and a diagrammatic plan view from above,
`respectively, of a leadframe according to the invention;
`[0037] FIGS. 6a and 6b show a partial diagrammatic
`illustration of a plan view from above of a leadframe strip
`with encapsulated semiconductor chips and, respectively, a
`partial diagrammatic illustration of a plan view from below
`of the leadframe strip;
`[0038] FIG. 7 shows a partial diagrammatic illustration of
`a sectional view of an injection mold with a leadframe strip
`inserted; and
`
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`

`

`US 2004/0106234 Al
`
`Jun.3,2004
`
`4
`
`[0039] FIG. 8 shows a partial diagrammatic illustration of
`a sectional view of a leadframe strip with encapsulated
`semiconductor chips.
`
`[0040] Like reference symbols in the various drawings
`indicate like elements.
`
`DETAILED DESCRIPTION
`
`[0041] A method for producing a leadframe 10 for a
`surfacemountable semiconductor component in accordance
`with FIG. 1 or FIG. 2, which is a light-emitting semicon(cid:173)
`ductor component in the exemplary embodiment, quite
`generally has the following steps: a) production of a layer
`composite comprising an electrically insulating carrier layer
`101 (the carrier layer is preferably a plastic film comprising
`polyimide or a polyimide-containing material) and an elec(cid:173)
`layer 102
`trically conductive connection conductor
`( examples of suitable materials for this are copper and
`copper based alloys) (see FIGS. 3a and 4a); b) patterning of
`the carrier layer 101 by means of masking and etching, in
`such a way that a first contact-making window 7 and a
`second contact-making window 8 are formed in it, which
`windows lead to the later first connection conductor 2 and,
`respectively, to the second connection conductor 3 (see
`FIGS. 3b-3d and 4b-4c); and c) patterning of the connection
`conductor layer 102 by means of masking and etching, in
`such a way that the first electrical connection conductor 2
`and the second electrical connection conductor 3 are pro(cid:173)
`duced, which can be electrically connected through the first
`contact-making window 7 and, respectively, through the
`second contact-making window 8 (see FIGS. 3e-3/ and
`4d-4e).
`
`[0042] As an alternative, step c) may take place before
`step b ). The thickness of the connection carrier layer 101 lies
`between from and including 30 µm and up to and including
`60 µm. The same applies to the thickness of the connection
`conductor layer 102.
`
`[0043] The carrier layer 101, prior to patterning, at least in
`the regions to be patterned, is not yet cured and can be
`removed by means of a suitable solvent. Except for the areas
`of the contact-making windows 7 and 8 and, if appropriate,
`other regions that are subsequently to be removed, the
`carrier layer will be cured. The uncured regions of the carrier
`layer are subsequently removed.
`
`[0044] For the patterning of the plastic carrier layer 101,
`firstly a photoresist layer 103 is applied thereto (FIG. 3b),
`which photoresist layer is patterned by means of known
`methods in such a way that the regions 70 and 80 of the
`contact-making windows 7, 8 are covered by the photoresist
`layer 103 (FIG. 3c). The plastic layer is cured in the
`uncovered regions, preferably by means of UV radiation 105
`(FIG. 3c). The photoresist layer 103 and the underlying
`plastic layer are subsequently removed from the connection
`conductor layer 102 in the regions 70 and 80. Examples of
`suitable solvents for this purpose are IPA (isopropanol) and
`acetone.
`
`[0045] As an alternative, for the patterning of the plastic
`layer, firstly a photomask 104 is arranged above or on said
`plastic layer, which photomask shades the regions 70, 80 of
`the contact-making windows 7,8 (FIG. 4b). The plastic layer
`is then incipiently cured or cured, such as by means of UV
`radiation 105, in the regions which are intended to remain on
`
`the connection conductor layer 102 (FIG. 4b). The photo(cid:173)
`mask layer 104 is subsequently removed and the plastic
`layer is then etched from the connection conductor layer 102
`by means of a suitable solvent 106 in the regions 70, 80 of
`the contact-making windows 7, 8 (FIG. 4c).
`In a method for producing a leadframe strip 200
`[0046]
`having a multiplicity of component regions, at least one
`contact-making window 7 and at least two connection
`conductors 2, 3 are formed in each component region by
`means of one of the methods described above.
`[0047] Along separating lines 110 between in each case
`two adjacent component regions, the connection conductor
`layer preferably has recesses 111 and 112 in which the
`connection conductor layer is removed (FIGS. Sa and 6b).
`[0048]
`In an exemplary method for producing a surface(cid:173)
`mountable light-emitting component in accordance with
`FIG. 1 having at least one light-emitting diode or laser diode
`chip 1, at least two connection conductors 2, 3, which are
`connected to at least two electrical contacts 4, 5 of the
`semiconductor chip 1, and having a chip housing 11, which
`has a connection carrier 9 and a chip encapsulation 6,
`specifically: a) the carrier layer 101 is applied to the con(cid:173)
`nection conductor layer 102 and then at least one chip
`window 7 and at least one wire connection window 8 are
`patterned in the carrier layer 101 and the external electrical
`connection conductors 2, 3 are patterned in the connection
`conduction layer 102 (cf. FIGS. 3a-3f, 4a-4e and 6a-6b); b)
`the semiconductor chip 1 is mounted into the chip window
`7; c) at least one electrical contact 5 of the semiconductor
`chip 1 is electrically connected to a connection conductor 3
`through the wire connection window 8 by means of a
`bonding wire 50; d) the composite comprising patterned
`connection conductor layer 102, patterned carrier layer 101,
`semiconductor chip 1 and bonding wire 50 is placed into an
`injection mold; and e) the semiconductor chip 1 including
`bonding wire 50 is encapsulated with encapsulating material
`6 by injection molding, which material is subsequently at
`least partly cured.
`
`[0049] For the mass production of such components,
`arrays 201 with in each case a multiplicity of component
`regions 202 with in each case at least one chip window 7, at
`least one wire connection window 8 and at least two
`connection conductors 2, 3 are produced in a laminate strip
`comprising connection conductor layer 102 and carrier layer
`101 (cf. FIGS. 6a and 6b). After the mounting of semicon(cid:173)
`ductor chips 1 into the chip windows 7 and electrical
`connection of the semiconductor chips 1 to the connection
`conductors 2, 3, each array is placed into an injection mold
`500 (FIG. 7), in which a single cavity 501 which spans all
`the component regions 202 of the array 201 and forms a void
`there essentially exclusively on the side of the semiconduc(cid:173)
`tor chips 1 is provided for in each case an entire array 201.
`After the injection of encapsulation material 60 into the
`cavity 501 and the at least partial curing thereof, the array
`201 is removed from the injection mold 500 and singulated
`into mutually separate semiconductor components by sev(cid:173)
`ering the encapsulation material 60 and the connection
`carrier layer 101.
`
`[0050] An exemplary method for producing a surface(cid:173)
`mountable light-emitting component in accordance with
`FIG. 2 having at least one light-emitting diode or laser diode
`chip 1, at least two connection conductors 2, 3, which are
`
`VIZIO Ex. 1024 Page 00011
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`US 2004/0106234 Al
`
`Jun.3,2004
`
`5
`
`connected to at least two electrical contacts 4, 5 of the
`semiconductor chip 1, and having a chip housing 11, which
`has a connection carrier 9 and a chip encapsulation 6, differs
`from the method just described merely by the fact that each
`component region has only one chip window and no wire
`connection window, and that the chip 1 is mounted onto the
`connection conductors 2 and 3 in the chip window 7 in
`rotated fashion with its light-generating epitaxial layer fac(cid:173)
`ing toward said connection conductors. Both electrical con(cid:173)
`tacts 4 and 5 are situated on the same side of the chip 1. The
`contact 4 lies on the connection conductor 2 and the contact
`5 lies on the connection conductor 3.
`
`[0051] As mentioned above, the carrier layer can be incipi(cid:173)
`ently cured or cured preferably by means of UV radiation.
`As an alternative, it may be able to be incipiently cured or
`cured by means of thermal radiation. The carrier layer can
`comprise polyimide monomer.
`
`[0052] The method according to the invention is suitable
`for producing electromagnetic radiation-emitting and/or -re(cid:173)
`ceiving components having one or more electromagnetic
`radiation-emitting and/or -receiving semiconductor chips. It
`is suitable in particular for producing light-emitting diode
`components having a housing installation barrier with the
`dimensioning 0402 (corres