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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
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`SAMSUNG ELECTRONICS AMERICA, INC.,
`and ASUS COMPUTER INTERNATIONAL, INC.,
`
`v.
`
`JAMES GOODMAN,
`Patent Owner.
`____________
`
`Case IPR2017-02021
`Patent 6,243,315 B1
`____________
`
`Record of Oral Hearing
`Held: November 16, 2018
`____________
`
`
`
`
`Before BRIAN J. McNAMARA, PATRICK M. BOUCHER, and
`KIMBERLY McGRAW, Administrative Patent Judges.
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`IPR2017-02021
`Patent 6,243,315 B1
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`APPEARANCES:
`
`ON BEHALF OF THE PETITIONER:
`
`
`RYAN K. YAGURA, ESQUIRE
`O'Melveny & Myers, LLP
`400 South Hope Street
`18th Floor
`Los Angeles, California 90071
`(213) 430-6189
`
`
`
`ON BEHALF OF THE PATENT OWNER:
`
`
`DAVID FINK, ESQUIRE
`Fink & Johnson
`7519 Apache Plume
`Houston, Texas 77071
`(713) 729-4991
`
`ALSO PRESENT:
`
`CHRIS BURRELL
`Samsung Electronics
`
`
`
`
`The above-entitled matter came on for hearing on Friday, November
`
`16, 2018, commencing at 11:09 a.m., at the U.S. Patent and Trademark
`Office, 600 Dulany Street, Alexandria, Virginia.
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`P R O C E E D I N G S
`- - - - -
` JUDGE McNAMARA: Samsung Electronics America vs.
`Goodman, IPR2017-02021. Again, I'm Judge McNamara. Judges
`McGraw and Boucher are participating remotely. So again, I
`would remind everyone to use the microphone at the podium and
`to identify any demonstrative or document by page number so
`the remote judges can find it in the record.
` Beginning with Petitioner's counsel, would everybody
`please introduce themselves?
` MR. YAGURA: Good morning, Your Honors. My name is
`Ryan Yagura. I'm with O'Melveny & Myers, and with me is
`Chris Burrell, who is in-house counsel for Samsung
`Electronics.
` JUDGE McNAMARA: I'm sorry, could you pronounce your
`name again?
` MR. YAGURA: Yes, it's Ryan Yagura.
` JUDGE McNAMARA: Thank you. And Mr. Fink, are you
`going to introduce yourself for the record?
` MR. FINK: David Fink for the Patent Owner.
` MR. YAGURA: All right. In this case the parties have
`both agreed to 30 minutes per side, and we'll follow the same
`procedure that we did in the previous hearing. We'll begin
`with the Petitioner, then Patent Owner opposition.
`Petitioner can then reply with any amount of time he's
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`reserved, and the same for the Patent Owner in terms of a
`sur-reply. I presume we're all ready to begin?
` MR. YAGURA: Yes, Your Honor.
` JUDGE McNAMARA: And would you like me to alert you to
`any particular amount of time?
` MR. YAGURA: Yes, Your Honor. I'd like to reserve 10
`minutes for rebuttal, please.
` JUDGE McNAMARA: Okay.
` MR. YAGURA: Good morning. I'd like to start with a
`brief overview of the '315 patent, and then I thought I would
`go to proceed through the different grounds that Samsung has
`proffered. If the panel has any place you'd like me to focus
`my time, I'd like to use my time wisely, but otherwise I'll
`just go ahead through my prepared remarks and reserve 10
`minutes.
` We've already talked about this in the last
`presentation. We're talking about the '315 patent, which has
`a priority date of December 31st, 1999. The patent --
`turning to slide 5 -- has 20 claims, two of which are
`independent claims, 1 and 10.
` Based on the previous presentations, I won't spend a
`lot of time going through them, but I will say that I'm
`labeling claim 1, the three limitations that follow the
`preamble, as A, B, and C. And then for claim 10, I'll be
`labeling the six limitations that follow the preamble as A
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`through F.
` I thought that slide 7 might be helpful for Your
`Honors. It shows the dependencies of all the dependent
`claims on claims 1 and 10. Whereas HP's counsel was
`proceeding against claims 1 and 5 and then 10 and 16, we are
`proceeding against all 20 claims.
` So as Your Honors can see, after you get past the
`limitations of claims 1 and 10, the limitations are awfully
`parallel between them. You have limitations of a 72 PIN
`SIMM, a 144 PIN SODIMM, a 168 PIN DIMM, the memory device
`being a DRAM, and then the feature of a serial presence
`detect, all of which are incorporated in the JEDEC Standard
`JESD21-C, which was published in January of 1997 and is in
`the record as Exhibit 1006 and expressly represented as prior
`art in the background of the invention of the '315 patent.
` So starting with our first reference is Dell. And we
`believe Dell anticipates or renders obvious claims 1 and 5 of
`the '315 patent. Dell -- turning to slide 9 -- is an
`application filed on April 30th, 1999, as prior art under
`102(e), and the patent owner does not challenge the status of
`Dell as prior art.
` Just turning to claim 1 and starting with the first
`limitation A, we have a plurality of volatile solid state
`memory devices. Taking a look at Dell, Dell also reflects a
`set of solid state memory devices on slide 11, FIG. 1, bottom
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`right-hand corner, shows two banks. They are attached to
`address and control lines, which we show in green. And the
`memory system itself comports with the JEDEC Standard, which
`is 21-C, again, which provides for three different power down
`modes, one of which is the self-refresh mode. And that's at
`Dell, column 3, lines 56 to 60.
` Turning to limitation 1b, we have a control device for
`selectively isolating the memory devices from respective
`address lines and respective control lines. In Dell --
`turning to slide 13 -- shows a bus controller 34, and you can
`see there's a blue line that leaves the bus controller and
`goes to field effect transistor, FET 52. And that's
`responsible for turning on and off the gate of the field
`effect transistor. And when it does that, it detaches -- it
`either connects or electrically isolates the two banks of
`SDRAM from the address in control bus.
` Limitation 1c requires a memory access enable control
`device for determining when the memory system is not being
`accessed, and then for putting the system into this power
`down state. Dell -- turning to slide 15 -- shows a memory
`controller 28, which is coupled to the bus controller 34.
`And the memory controller 8 is responsible for monitoring and
`issuing commands to the memory devices to read and write
`information.
` So if we just take a look at slide 16, the background
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`of the invention for Dell, column 1, lines 40 to 45, say that
`there is a need for a system in which you can reduce power to
`individual banks of memory when the banks of memory are not
`being accessed.
` And the solution of Dell, which is shown in the bottom
`of slide 16, this is column 5, lines 49 to 57, explains that
`the memory controller issues commands and therefore
`determines the level of activity on the memory devices. And
`then it says, either the memory controller or the system bus
`controller may act on one or more portions of the memory to
`put them in reduced power mode. So while both of them are
`capable of doing that, we've chosen the memory controller 28
`to be the memory access enable control device because it is
`then connected to the system bus controller 34, which is part
`of the control device in the structure of the claims.
` When the bus controller issues a command to open FET
`50, 52, and 56, it then disconnects the memory controller 28
`from the SDRAM banks, as indicated on slide 17, which the
`very first passage is column 4, lines 11 through 16. And
`when those banks are open, the memory controller 34 can then
`place the memory banks into any one of the three JEDEC
`standardized power down modes that Dell referred to earlier.
`That's at column 4, lines 19 to 22. And then the last
`passage on slide 17 says that of those power down modes, a
`self-refresh mode is one of those that's used for prolonged
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`suspended activity.
` Referring now to claim 5. Claim 5 merely adds to
`claim 1 the fact that the memory devices are DRAMs, and Dell
`clearly discloses that, two banks of SDRAMs.
` Patent owner has raised two disputes with respect to
`Dell. The first is that the '315 patent, claim 1, requires
`that all the banks and memory devices be put into
`self-refresh mode in unison, and the second is that the '315
`patent requires that all of the control signals be
`electrically isolated from the memory devices. Those are the
`two arguments he's raised for claim 1 and also for claim 10.
` So turning to the first argument, there's nothing in
`the claim that actually requires that the memory banks be
`powered down in unison. What the claims say is that you have
`a plurality of memory devices and said memory devices be put
`into this power down state together. So that is at least two
`devices, based on the fact that it says a plurality.
` Clearly, Dell discloses the powering down of at least
`one bank at a time, which shows, by way of example, four
`memory devices in FIG. 1. But, of course, nothing would
`prohibit Dell from placing both memories -- both banks of
`memories into those power down states at the same time. So
`one, the claim doesn't require that you put all the memory
`devices down into the reduced power state in unison, only two
`devices. And Dell discloses it under either definition.
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` Second is whether -- and we spent a lot of time in the
`last hearing -- whether selectively electrically isolating
`requires electrically isolating certain address and control
`lines or all of the address and control lines.
` And I'll take Your Honors to slide 21, which shows
`FIG. 4 of the '315 patent. And I think Mr. Sheldon already
`presented on this, but the only teaching in the patent is
`that the control -- is that the control center 115 then
`electrically isolates the memory devices 105 from the control
`lines 122 and address lines 117. And if we look at FIG. 4,
`by way of example, which the numbers correspond to in this
`particular passage, you can see that the address bus is 117,
`control bus is 122 in yellow. And FIG. 4 does not refer to
`the RAS and WE control lines, which we've shown in red.
`There's no teaching that those lines would be isolated.
` If we turn to FIG. 3A, FIG. 3A actually shows one of
`the pin-outs of these devices. We could take a look and see
`that there are a number of control lines that come into
`there. We see OE, which I believe is output enable, WE,
`write enable, CAS and RAS, which are column address strobe
`and row address strobe. There's only one line of each coming
`into there, so the idea that there could be multiple lines of
`any of these doesn't seem plausible.
` And what this pin-out teaches us is two things. One
`is that if you take away the WE and RAS lines, which are
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`specifically called out in FIG. 4 as being separate, what
`that leaves is the output enable and the CAS lines as being
`the control signals. So the FIG. 4 in the corresponding
`paragraphs in the last slide, slide 21, would indicate that
`CAS and OE are the address -- or the control commands that
`are being isolated, whereas WE and RAS are not. And then we
`see there's a bunch of address lines.
` What Your Honors will notice -- will not notice on
`there is a clock signal. So as Mr. Sheldon said, all of the
`devices that are described in here are asynchronous devices.
`The pin-outs also would confirm that there are no clock or
`clock enable signals going to any of these chips.
` So jumping to slide 24, patent owner's argument that
`Dell allows the clock enable signal to reach the memory
`during self-refresh mode is irrelevant. There are absolutely
`no teachings in the '315 patent as to whether clock enable
`would be a control signal. And even if it were, and not just
`part of the timing signals that go throughout memory devices,
`there's no teaching that it would be one of the signals that
`would be on the control bus and that would be electrically
`isolated by the control device. What it does teach is that
`there are -- the pin-outs would show four control signals,
`only two of which are electrically isolated and two of which
`are not by the control device.
` Turning to claims 10 and 16. Our combination there is
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`Dell plus prior reference Abe. Abe was issued on December
`31st, 1996. So it's 102(a) and 102(b) prior art as well as
`102(e) prior art. Patent owner doesn't challenge the prior
`art status of Abe.
` Slide 27 shows the various limitations that are
`lettered 10a through 10f. Again, we've already talked about
`10a, which is the solid state memory devices with the address
`and control lines. Dell discloses that limitation. 10b is a
`computer system that includes a first electrical power
`source. If we take a look at Abe, Abe discloses on slide 29,
`FIG. 1, a main power supply 1 that connects to the DRAM and
`supplies a first power signal.
` 10c -- turning to slide 30 -- is the control device
`for monitoring the first voltage and determining when the
`first voltage drops below a predetermined voltage and then
`for selectively isolating the memory devices.
` If you turn to slide 31, Abe discloses power supply
`monitors 3 and 5, which monitors the voltage from the main
`power source. So when they drop low, the system will then
`convert to the auxiliary power supply 2. So power supply
`monitors 3 and 5 are the control devices that monitor the
`first power source. Then, we combine that with Dell, which
`Dell discloses selectively electrically isolating the control
`bus through the control bus 34 and FET 50 in the Dell
`reference.
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` Slide 32 shows claim 10d, which the limitation
`requires a second electrical power source. We turn to slide
`33, Abe FIG. 1 discloses an auxiliary power supply 2, which
`is a second power source.
` Turning to slide 34, we have 10e, which is the control
`device, which disconnects the first power source when it
`falls low and connects the second power source. And here the
`patent describes two diodes that either -- diodes 16 and 17,
`one of which would connect to main power supply 1. And when
`that falls too low, it's detected by the power supply
`monitors 3 and 5. The system would shift over to auxiliary
`power 2 through using these two diodes. That would be
`controlled by the control bus 34 in Dell.
` Last limitation of 10f, which is, the data is
`preserved by switching from one power source to the other
`power source, and the memory devices are isolated from errant
`control signals -- or errant signals. Turning to slide 37,
`Abe describes just that. The whole purpose of having the
`first and the second power sources is for supplying -- is for
`retaining information on the memory devices, should the first
`power source fail. And again, Dell discloses the reason we
`discussed before, the memory control bus and the FET
`switches, which electrically isolate the system -- the
`control bus from the memory devices.
` The combination -- going to slide 38. The combination
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`of Dell and Abe is straightforward. Both of the two
`references are not only in the field of memory devices with
`power down states that also use self-refresh mode as part of
`those power down states, but it's also applying the apparatus
`of both diagrams in exactly the way that one of ordinary
`skill in the art would know. And that's what Dr. Wolf says
`in his declaration. Dell again discloses a plurality of
`SDRAMs, which are found in claim 16.
` Turning to the remaining dependent claims. We combine
`Dell and the JEDEC 21-C Standard for claims 2 through 4 and 6
`through 9, and then Dell/Abe in the JEDEC Standard for 11 to
`15 and 17 to 20. And just jumping to a summary page on the
`left-hand side of the chart on slide 41, Your Honors, I've
`put the dependent claims on the right side. I've put the
`JEDEC pin-out that's being claimed in those independent -- in
`those dependent claims. And if you take a look at the JEDEC
`Standard, this is a standard that was published in January of
`1997.
` We have a declaration from John Kelly, who was, I
`believe, the president at the time. He says it was
`published, made available to members and to the general
`public in the form that we submitted it, which is about a
`780-something page document.
` Turning to slide 42, it's the reference to the module
`for the 144 PIN SDRAM -- SODIMM. This was a JEDEC Standard.
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`Slide 42 shows the 144 PIN SDRAM standard. Slide 43 shows
`the 168 PIN DRAM standard, and then slide 44 shows a
`reference to a serial presence detect. And then finally,
`slide 45 shows the 72 PIN SDRAM -- DRAM standard.
` Now, again, the '315 patent admits that this JEDEC
`Standard JESD21-C is prior art and existed at the time and,
`in fact, incorporated this standard by reference. Again,
`turning to slide 46, both the '315 patent and Dell both refer
`to the JEDEC standards. So it would have been obvious to
`combine both Dell and Abe with the JEDEC Standard at that
`time.
` So those are all the remarks I have prepared on Dell,
`Abe, and the JEDEC Standard. If the panel has any questions,
`I'd like to answer those, otherwise I'll go on to Ooishi and
`Palaniswami.
` JUDGE McGRAW: I just want to ask, where you say in
`FIG. 3A that only two lines are electrically isolated into
`art, where is that discussion in the papers?
` MR. YAGURA: In our petition or in the '315 patent,
`Your Honor?
` JUDGE McGRAW: We can start with the '315 patent, but
`I do want to know where that is in your papers as well.
` MR. YAGURA: Your Honor, I've turned to slide 21,
`which refers to the '315 patent at FIG. 4 and column 9, lines
`44 to 48. And in there, the patent only discloses that the
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`control center 115 electrically isolates the memory devices
`105 from the control lines 122 and the address lines 117. As
`Your Honor can see from FIG. 4, the address bus is labeled
`117 and the control bus is labeled 122.
` By implication, there is no statement about the RAS
`and the WE control lines, which don't bear those numbers,
`being isolated. So that's my support for only some of the
`lines are isolated but not others, according to the express
`teachings of the patent.
` JUDGE McGRAW: And what about your discussion of what
`is shown in FIG. 3A, which is on slide 22?
` MR. YAGURA: I don't recall if we referred to slide --
`to FIG. 3A in our moving papers. I think what we said in our
`moving papers is that we understood that parties in the HP
`matter had agreed to a construction. And in his response
`paper, Mr. Fink agreed that those constructions were the
`agreed upon constructions, and didn't contest those as being
`the broadest reasonable construction in this particular case.
` JUDGE McGRAW: How would you respond to Mr. Fink's
`assertion that was made in the previous case that would also
`apply here, that a person of ordinary skill in the art would
`understand that the RAS and WE control lines are on the
`control bus, and therefore are electrically isolated by the
`control device?
` MR. YAGURA: Yes, Your Honor. The patent itself
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`expressly teaches that the RAS and the WE control lines are
`not on the control bus, which is labeled 122 in the figure,
`so I think anybody looking at this diagram would not assume
`that there were two RAS and WE lines. That would seem to
`defy almost any rule of circuit design that I'm aware of.
` The second is if you take a look at all the prior art
`references that have been cited in each of these cases, both
`the HP case and the Samsung case as well as the accompanying
`ASUS case, all the prior art references only show one of
`each. So there would be one CAS, one RAS, one WE, and one
`output enable as well as one clock, which isn't disclosed in
`the '315 patent, but is disclosed in all of the prior art
`references.
` So I don't think it would be reasonable for anybody to
`assume that you would have two RAS and WE lines on -- in FIG.
`4, two on the control bus and then two more below it. There
`would be really no reason for that. It would be redundant.
` JUDGE McGRAW: And how about with regard to FIG. 1?
` MR. YAGURA: I believe the answer is the same. I will
`-- I think I used FIG. 4 as our ground. Let me just grab it.
`So taking a look at FIG. 1 of Exhibit 1001, FIG. 1 shows
`control bus 28 and address bus 17 going to the address and
`control center. It also shows separately the RAS and WE
`control lines, which are labeled 26 and 28, which now go to
`the memory access enable control 30 and then to the address
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`control lines.
` So when the patent states that the control bus -- that
`the electrical isolation occurs only with respect to the
`control bus and the address bus, it's referring to whatever
`signals are on control bus 22, but not the RAS and the WE
`control lines, which are labeled 26 and 28. And the reason I
`brought up FIG. 3A in my discussion is just to show Your
`Honors that there are -- there's only one of each of those
`lines, as you would expect in any of the figures in the '315
`patent.
` But the point of FIG. 3A, it shows that when FIG. 1
`says that there are separate RAS and WE lines and then a
`control bus, the pin-out of FIG. 3A shows that the RAS and
`the WE only come in once and the CAS and output enable only
`come in once. Two of those lines must therefore be coming
`from the control bus, and two of those lines are labeled
`separately in FIG. 1 and in FIG. 4, for that matter.
` JUDGE McNAMARA: Counsel, just to let you know, you're
`entering your rebuttal time.
` MR. YAGURA: Okay.
` JUDGE McGRAW: Sorry.
` JUDGE McNAMARA: Oh, not at all.
` MR. YAGURA: And then, Your Honor, in our petition
`it's addressed. On pages 13 through 22 of our petition is
`our section on Dell. And our section on claim construction
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`IPR2017-02021
`Patent 6,243,315 B1
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`electrically isolating is found on pages 10 and 11 of our
`petition.
` JUDGE McGRAW: Thank you.
` MR. YAGURA: If I could turn briefly to Ooishi and
`Palaniswami -- and I'll be jumping to slide 47. And again,
`starting with slide 48, Ooishi is prior art. The application
`was filed June 2nd, 1999. Palaniswami, on slide 49, is prior
`art, based on the application filed January 21st, 1997. The
`Patent Owner does not contest either as prior art.
` Taking a look at claim 1a, you can see that Ooishi
`shows on slide 51 that there are a bank of memory devices in
`green, that they are connected to control and address lines
`on the left-hand side of the figure -- FIG. 1, and that
`they're capable of being put into self-refresh mode, which is
`box SRC in the center of the diagram.
` Limitation 1b -- if we jump to slide 53 -- here, what
`Ooishi describes is that there's circuitry 400. And when it
`defines circuitry 400, it's all the boxes that are listed
`there in yellow. And so when the system goes into
`self-refresh mode, all of these circuits in yellow here are
`powered down, which means that no signals go between any of
`the -- any of the control or address lines on the left-hand
`side of FIG. 1 of Ooishi to any of the memory devices on the
`right-hand side. They are electrically isolated.
` Beyond that, if we were to combine Palaniswami -- if
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`IPR2017-02021
`Patent 6,243,315 B1
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`we were to combine Ooishi with Palaniswami, Palaniswami
`teaches an actual isolation mechanism labeled as 20. That's
`between a digital signal processor, or what they called a
`logic unit in Ooishi, and the DRAM on the right side of
`Palaniswami FIG. 2, which is also the DRAM on the right side
`of Ooishi's.
` So one of ordinary skill in the art, as Dr. Wolf
`testified in his declaration, which again goes unrebutted,
`said that it would be obvious to one of ordinary skill in the
`art to insert the isolation mechanism 20 of Palaniswami into
`FIG. 1 of Ooishi, and put it between the logic unit, which
`is, for example, a DSP as in Palaniswami, and the memory
`devices.
` The Patent Owner just -- the only argument the Patent
`Owner raises with respect to Ooishi and Palaniswami is that
`there are -- the gate would be floating. These devices would
`be floating if they were powered down, but again, the claims
`only require electrical isolation, not physical isolation.
`And even if that were true, Palaniswami teaches both.
` And 1c, the memory enable access device, that is --
`turning to slide 57 -- that is the mode decoder, number 2.
`The mode decoder, as taught by Ooishi, receives a CKA signal
`of low or L. And when it receives that, it goes ahead and
`places the system into a low power mode.
` So if we were to control -- if we were to combine
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`IPR2017-02021
`Patent 6,243,315 B1
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`Ooishi and Palaniswami, the mode decoder would either place
`all the circuitry 400, which was shown in yellow in a prior
`slide, into power down mode, and/or it could also put -- it
`could also trigger the isolation mechanism 20 in blue on
`slide 58 that would come from Palaniswami. And Ooishi
`teaches that the whole purpose of all this is that current
`consumption during the self-refresh mode can be reduced.
` Turning to slide 29 quickly, Palaniswami also
`discloses that the memory devices are DRAM, as does Ooishi.
`And again unrebutted, Dr. Wolf said it would be obvious to
`one of ordinary skill in the art to combine these two
`together as shown in slide 60.
` Turning to slide 61, claim 10. This is just a road
`map, for the sake of time, Your Honors. Ooishi or
`Palaniswami show the plurality of the solid state memory
`devices with the control lines. Abe discloses claim 10b,
`which is the first power source. Again, Abe and Palaniswami
`disclose the power supply monitors and the isolation
`mechanism.
` D is -- claim 10d is the second electrical power
`source, which is disclosed by Abe.
` Claim 10e is the control device for disconnecting the
`power source, which we also saw on Abe, which are the diodes
`16 and 17 from Abe's figures.
` And finally, 10f is the auxiliary power supply of Abe,
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`IPR2017-02021
`Patent 6,243,315 B1
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`plus, again, reference to the isolation mechanism of
`Palaniswami, which is isolation mechanism 20. And again, as
`for claim 16, claim 16 -- all of the references show that the
`memory is DRAM.
` Sorry that was quick, but I'd like to try to reserve
`my five minutes.
` JUDGE McNAMARA: You have three.
` MR. YAGURA: Three. Thank you, Your Honor.
` MR. FINK: Again, I want to thank the Board and my
`colleague for cooperating with my needs and having this
`hearing at this time -- in this period of time. I appreciate
`that very much.
` JUDGE McNAMARA: I'll also alert you when you have
`five minutes left.
` MR. FINK: Standard five minutes. And I want to
`mention again that when the Board initiated this IPR, they
`made a point of saying, our factual findings inclusions in
`this stage of the proceedings, including claim construction,
`are preliminary and based on the evidentiary record developed
`so far. This is not a final decision as to patentability of
`claims which -- for which the IPR is instituted. Our final
`decision will be based upon a fully developed record.
` And in the conclusions the Board made a point of
`saying, at this stage of the proceedings, the Board has made
`-- has not made a final determination of patentability of any
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`IPR2017-02021
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`challenged claim or any underlying factual and legal issues,
`including claim construction. Because there is not in this
`presentation, but in the Reply Brief, a reference suggesting
`that the Board has already made a determination. They know
`they're not, but I want to put it in the record anyway.
` The issue has been brought up again about expert
`opinion, and as you probably noted through this presentation
`and also the Reply Brief for Samsung, the attorney refers to
`various portions of the patents and lines, and that's
`acceptable. The fact that every now and then he brings in an
`expert doesn't make what he said less important.
` And it's a matter of economics. My client, he's what
`you would say in San Francisco, a nerd. He's an inventor,
`not a rich guy. And he's made a couple of inventions, and he
`doesn't have the money to support the high power expert that
`might be appropriate here.
` The early part of the Samsung -- I must say that I
`really appreciate this opportunity to respond to the Reply
`Brief and the position of Samsung. Early in Samsung's Reply
`Brief, they stressed that the Goodman is -- well, I'll quote
`what he says. Goodman's chief and most frequent
`mischaracterization of the '315 patent claims continues to be
`that they require memory to be electrically isolated from
`all, emphasis in the original, control signals. And they go
`on to say, the '315 claims do not require total, and that's
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`IPR2017-02021
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`in the original, and isolation.
` And the point has been made here, with respect to FIG.
`1, just as in the case of HP, that the RAS, read address, and
`the WE, write enable controlled lines, 26 and 28, do not
`appear to be isolated during the power down. And this is
`stressed by both HP and Samsung.
` But where is the expert opinion? They both have
`experts. Why hasn't -- if they feel very confidently about
`this, why haven't they had a statement from their experts
`saying this is the case? The answer is simple, because it's
`not the case.
` The RAS and the WE are used in two ways. One, as
`shown in FIG. 1, to go to the memory access enable control,
`to tell the memory access enable control, which is part of
`claim 1. There's no activity. The memory is not being
`accessed. Okay, you can start the process of going to power
`down. It's not shown going into the memory because it's part
`of the bundle. This is a part
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