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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
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`TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,
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`Petitioner,
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`v.
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`GODO KAISHA IP BRIDGE 1,
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`Patent Owner.
`____________
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`IPR2017-01841a
`Patent 7,893,501 B2
`____________
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`Record of Oral Hearing
`Held: September 6, 2018
`____________
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`
`
`Before JUSTIN T. ARBES, JENNIFER MEYER CHAGNON, and
`MELISSA A. HAAPALA, Administrative Patent Judges.
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`
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`a Case IPR2017-01842 has been consolidated with this proceeding.
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`IPR2017-01841
`Patent 7,893,501 B2
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`DAVID CAVANAUGH, ESQUIRE
`Wilmer Cutler Pickering & Hale
`1875 Pennsylvania Avenue, N.W.
`Washington, DC 20006
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`APPEARANCES:
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`ON BEHALF OF THE PETITIONR:
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`ON BEHALF OF THE PATENT OWNER:
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`RICHARD GIUNTA, ESQUIRE
`Wolf Greenfield
`600 Atlantic Avenue
`Suite 2300
`Boston, MA 02210
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`The above-entitled matter came on for hearing on Thursday,
`September 6, 2018, commencing at 1 p.m., at the U.S. Patent and Trademark
`Office, 600 Dulany Street, Alexandria, Virginia, before Julie Souza, Notary
`Public.
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`JUDGE CHAGNON: Please be seated. Good afternoon everyone. I
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`am Judge Chagnon and Judge Arbes is joining us here in the room, and we
`also have Judge Haapala joining us remotely on the screen over there.
`Today we will be having the final hearings for IPR2017-01841 and
`IPR2017-01843, both related to U.S. patent 7,893,501 and involving
`Petitioner Taiwan Semiconductor Manufacturing Company, Ltd., and Patent
`Owner Godo Kaisha IP Bridge 1.
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`We'll start today with the hearing for IPR2017-01841 and I'll note that
`case IPR2017-01842 has been consolidated with that case. After the first
`hearing we'll have a short break and then we'll proceed to the second hearing
`for today. Counsel, can I just have you go ahead and step to the microphone
`and introduce yourselves, and let us know who will be presenting today.
`Let's start with Petitioner.
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`MR. CAVANAUGH: Sure. Good afternoon, Your Honor. I'm Dave
`Cavanaugh, I'm with Wilmer Hale representing Taiwan Semiconductor.
`With me is Mike Smith, also from Wilmer Hale and Scott Bertulli, also from
`Wilmer Hale.
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`JUDGE CHAGNON: Thank you.
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`MR. GIUNTA: Good afternoon, Your Honors. I'm Rich Giunta from
`Wolf Greenfield for the Patent Owner IP Bridge. With me is Gerry
`Hrycyszyn and Josh Miller. I'm going to argue the 841 case and Mr.
`Hrycyszyn is going to argue the 843 case.
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`JUDGE CHAGNON: Thank you so much, and just a reminder during
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`your presentations today because Judge Haapala is not joining us here in the
`room she is not able to see the screen, so please just make sure to identify
`the slide number when you're referring to demonstratives so she can follow
`along.
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`Per our Trial Hearing Order each party has 60 minutes today to
`present arguments for this first hearing. Petitioner will present first followed
`by Patent Owner and Petitioner you may reserve up to 30 minutes of time
`for rebuttal of any issues raised during Patent Owner's presentation and
`Patent Owner may reserve up to ten minutes to address Petitioner's rebuttal
`at the end. And we also just ask that the parties not interrupt each other
`during the presentations today. If you have any objections you may address
`them during your own presentations and if something comes up during the
`final presentation, please let me know at the end of that. Do you have any
`questions before we get started?
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`MR. GIUNTA: No, Your Honor.
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`MR. CAVANAUGH: No, Your Honor.
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`JUDGE CHAGNON: All right, great. So go ahead whenever you're
`ready. Did you want me to set the clock to reserve any time for you?
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`MR. CAVANAUGH: Yes, Your Honor. I'd like to reserve 15
`minutes for rebuttal.
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`JUDGE CHAGNON: Fifteen minutes? Okay. Whenever you're set
`I'll go ahead and start the clock for you.
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`MR. CAVANAUGH: Thank you, Your Honor. Good afternoon.
`May it please the Board. The issues today in these proceedings boil down to
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`a few simple points or issues. The challenged patent, which I'll shorten to
`the 501 patent, was issued after many rejections by the original examiner
`because the Applicant added a single limitation at the end of the independent
`claim. The examiner in the Notice of Allowance said that the claim was
`allowed because the references then in front of the examiner didn't present a
`teaching for that last limitation that was added to gain allowance and the
`Patent Owner doesn't dispute that the last limitation is in the prior art,
`indeed, the prior art that is currently in this particular proceeding. It disputes
`the presence of a limitation that was in the independent claim from the
`beginning of prosecution and during the repeated rejections and the
`limitation disputed by the Patent Owner in this proceeding is not the same as
`what the examiner provided in the reasons for allowance.
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`The petition in the 1841 and 1842 IPRs presented a reference,
`Igarashi, and the petition carefully identified the elements in the reference
`and the limitations of the claim. But this wasn't an anticipation ground
`though. Igarashi was combined with Woerlee and together the references
`render obvious the challenged claims.
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`The presence of all the limitations of the challenged claims in the
`prior art combination is not or cannot be in substantial dispute. The issues
`boil down to whether the combination discloses a feature which is common
`in all transistors called an active region that is recited in the independent
`claim and in order to address the issues, if we can go to slide 2, I'd like to
`talk a little bit about the patent technology as a background, an overview of
`the 501 patent, describe a little bit about the prior art and then address some
`issues that are undisputed between the parties and a little bit about the
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`obviousness of the claims as kind of an introduction to some of the issues
`raised by the Patent Owner in their papers.
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`So moving to the technology background. I've put on slide 4 a few
`elements which are common to transistors and just as a way of maybe table
`setting some of the common elements that are going to be discussed today
`and have been presented in the papers, and I'm sure Your Honors are well
`familiar with many of these elements because they are pretty standard for
`transistor type technology.
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`MISFET technology is kind of a super set of what many electrical
`engineers understand as MOSFET type transistors so what we're talking
`about is a general kind of class of transistors that is largely undisputed by the
`parties are basic elements of a transistor. For the reference of the Board
`there is a gate which is in orange. There's a gate insulating film which is in
`red on the right hand side of slide 4 and then there is source and drain
`regions which are illustrated in green and, as Your Honors know, in the
`operation of a transistor the source and drain regions have a channel which is
`kind of calibrated based on the amount of doping in a transistor during
`manufacture.
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`Then another element that I'll raise, just introduce, is the side walls on
`the gate electrode and those are in purple. There's also a shallow trench
`isolation region which bounds the transistor, and we'll talk about all those
`elements in the course of the 501 patent and the prior art that's been applied
`in this proceeding.
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`So moving to slide 5 which I mentioned in my introduction that one of
`the issues that the Patent Owners raised is the presence of whether there is
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`the presence of an active region in the prior art that we've identified in the
`grounds, and I want to kind of start with what we presented in our petition
`just like the idea of an active region or the concept of an active region or the
`presence of an active region is quite ubiquitous in the art. In fact our expert
`in his opening declaration said transistors have active regions. Without an
`active region there is really no transistor. It doesn't work that way.
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`But from a standpoint of what we presented as some treatises or some
`textbooks, the active regions, now on slide 5, the active regions between the
`silicon oxide layers where transistors will be built are called the active
`regions of the substrate, clearly identifying a particular region associated
`with the transistors and the second reference Rabaey and says essentially the
`same thing.
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`So with that as background, I'd like to introduce the 501 patent in
`terms of like some of the limitations of the claim, how they're represented in
`the patent. So what I have on slide 7 here is kind of figure 1 of the 501
`patent and we've identified in various colors the claim limitations and we
`start with, I'll just go through the colored. The gate insulating film, the gate
`electrode which is in orange, the source and drain region which is in green,
`and there is a silicon nitride film which is in blue, and all of these are
`described and characterized in the 501 patent. I also will talk about the
`active region 1A and the Patent Owner kind of describes some of the
`characteristics of the active region. Clearly 1A is represented in the 501
`patent as one would expect a transistor to have.
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`So we can move to the next slide. I mentioned also at my opening
`that the last limitation which is the protruding gate limitation, as Your
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`Honors are aware, was added to the claim as an amendment during
`prosecution and in fact the examiner allowed the claim because of the added
`limitation of a protruding gate. The patent applicant at the time, in order to
`gain allowance, identified figures 1 and 4A as corresponding to the
`protruding gate. There is no disclosure in the 501 patent with regard to the
`protruding gate and there's no benefit that's described. In fact, the Patent
`Owner in the 1843 proceeding reaches back to Igarashi to explain the
`benefits of what the protruding gate would provide, but I'll get to that in a
`few minutes. So in looking at this, the correspondence between figure 1 and
`the challenged claim 1 is important for Your Honors to recognize that the
`disclosure, the support of the claim is found in figure 1.
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`So we can go to the next slide. Here on slide 9 I've presented the
`limitations of the claim and I'm not going to spend too much time because
`I'm sure Your Honors are well aware of the various limitations of the claim,
`but for this proceeding we'll focus on the first few lines of the claim, the
`MISFET includes an active region made of a semiconductor substrate.
`Again, that limitation was present in the claim throughout prosecution,
`throughout various rejections, until the last limitation was added, and
`speaking of the last limitation the gate electrode is the last limitation
`protrudes upwards from a surface level of parts of the silicon nitride film and
`that itself is the heightened, kind of the fact the gate protrudes above the
`surface of that silicon nitride film.
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`Perhaps you can go to the next slide. So on slide 11 I've identified the
`various components of the claim in the prior art. Figure 12 is what we've
`provided. It describes many of the features of the claim. Explicitly there's a
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`gate insulating film in red, there's a gate electrode in orange, and there's
`source and drain regions in green and the gate electrode which is orange
`protrudes above the silicon nitride film in 8, and so we see that quite clearly
`in the figure 12 that's illustrated on slide 11.
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`So go to the next slide. There can't be a substantial dispute that
`Igarashi discloses an active region. Now the Patent Owner makes a more
`specific allegation, but the active region which is present in all transistors is
`explicitly provided in paragraph 68 of Igarashi where it describes a
`semiconductor substrate 1, talks about element isolation is performed by two
`well-known methods, LOCOS and the trench method, and then ion
`implantation and a reading from paragraph 68 of Igarashi, ion implantation
`is performed to the active element region. So clearly there's an explicit
`disclosure that in Igarashi about an active region. Igarashi, this particular
`portion in paragraph 68 is associated with Igarashi figure 1. It is our
`contention that because the semiconductor substrate 1 is common in both
`illustrations and this is a very common term for what's present in all
`transistors that there can be little doubt that figure 12 would also have an
`active region, but we'll talk about that throughout this presentation.
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`We can go to the next slide. As I mentioned also at my opening this is
`not an anticipation ground, this is an obviousness ground to the extent that
`there would be a question about whether there was an active region in figure
`12, we combined it with Woerlee and Woerlee has an express teaching of
`insulating regions which are in the semiconductor body 1 and define an
`active region. So it's our contention that with the disclosure in Igarashi, with
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`the understanding of one skilled in the art combined with what Woerlee
`teaches that the claimed elements are met.
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`So I'd like to spend a moment about what we believe are undisputed
`issues and issues that the trial itself has perhaps clarified or has allowed.
`There's no dispute that Igarashi discloses the allegedly novel protruding
`gate. I mean here -- now on slide 15 -- the comparison between the gate
`electrode being above the surface 8A is clear as it is with figure 12 of
`Igarashi where the gate electrode 3A is above the surface 8. So that, to our
`understanding, is a pretty clear representation of a protruding gate but I think
`we can also rely on the Patent Owner as accepting that that is a protruding
`gate because in the 1843 POPR they provide it, and this is at page 32 of their
`POPR, they talk about the protruding gate and causing the electrode to
`protrude above the silicon nitride film which is precisely what the
`characterization is in the claim. Indeed, Igarashi teaches this explicitly and
`we highlighted that, and this is the Patent Owner's recognition that the
`protruding gate is a part of Igarashi and certainly not novel to the inventor of
`the 501 patent.
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`Next slide. Another what we believe to be an undisputed issue is that
`except for the active region, the Patent Owner really doesn't dispute the
`presence of all the other limitations of the claim and I would note also for
`the record that in the 1843 proceeding, the Patent Owner does not dispute
`that the primary reference Misra has that active region. The final thing that
`I'd like to say with regard to some undisputed issues would be that the Patent
`Owner doesn't challenge that the Woerlee, Igarashi references would be
`combined by someone skilled in the art.
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`Next slide. So I'd like to just -- and I'll go through the obviousness of
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`the claims and I know I've already previewed some of these slides so I'm
`going to kind of go through them quickly -- but if we go to the next slide,
`again we're talking about the MISFET includes the active region made of a
`semiconductor substrate.
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`If we go to slide 20, and clearly we have a disclosure of an active
`region associated with the device that's described in Igarashi and that's what
`we've described. Next slide.
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`JUDGE ARBES: Counsel, before you move to the next slide.
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`MR. CAVANAUGH: Sure.
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`JUDGE ARBES: Is it your position there is one active region or two
`active regions?
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`MR. CAVANAUGH: Our position, and I'm glad you've asked that
`question, there is one active region. There is some lack of clarity about the
`testimony and I can talk about that if Your Honor would like now or later,
`but if your question is whether there's an active region associated with that
`despite some lack of clarity in the questions where our expert has come out
`cleanly and consistently is that there is one active region and it's between
`those STI elements.
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`JUDGE ARBES: Okay. And just to clarify that, I see a lot of colored
`versions of the figure 12 of Igarashi in your papers that very specifically say
`what the different regions of the claim are. What I don't see in your papers
`is a colored or other delineated figure to show us exactly where the active
`region is. Is it your position that the active region is that entire area 1
`between the two STIs that are added?
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`MR. CAVANAUGH: For this rendering, yes. I mean like there
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`would one active region and the STI, what Dr. Shanfield has testified
`consistently and extensively is that an active region is bound by isolation
`and because, in Dr. Shanfield's expert opinion, someone would understand
`that figure 12 is disclosing at some point to someone skilled in the art there's
`going to be an isolation region and the active region would be below those
`transistors defined by those isolation regions.
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`JUDGE ARBES: Okay. So in your view then, do you agree that that
`active region as you've described it corresponds to two transistors, not one,
`two?
`MR. CAVANAUGH: We believe that the active region here
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`corresponds to two transistors as illustrated here, and now what Dr.
`Shanfield has said there may be more going aside. He can't tell because of
`the way the drawing is but here there is an active region and that is going,
`clearly testified and the question I think that the Patent Owner raises is
`whether or not there needs to be a one-to-one correspondence between the
`active region and the transistor, and the transistor that includes an active
`region made of semiconductor substrate is fully met by that.
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`Now there happened to be two transistors that also have an active
`region formed from the semiconductor substrate, if I can use the claim
`language, and it's our position that fully satisfies the claim and how do we
`know that? We know that because if we were to just put our hand over one
`of those transistors it would meet all the limitations of what the Patent
`Owner says there should be in a transistor, an active region bounded by
`silicon trench isolation or some isolation regions and the active region just
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`doesn't magically disappear if you add another transistor and I'll talk about
`that a little bit later on in the presentation also but that's --
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`JUDGE ARBES: Just to be clear, I believe you said that this active
`region as you've described it corresponds to at least two transistors. So if we
`agree with Patent Owner that the claims do require a one-to-one
`correspondence between the MISFET and the active region, your contention
`fails, correct?
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`MR. CAVANAUGH: I don't believe that it corresponds to a
`one-to-one. We've taken the position otherwise.
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`JUDGE ARBES: If it does –
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`MR. CAVANAUGH: But let's say hypothetically that you were to
`say that, I think there are two responses to that. The first one is that from a
`perspective of what Igarashi is showing and what Woerlee is showing, you
`know, to the extent that there's a lack of clarity about that one-to-one
`correspondence, if that is the way the Board would interpret the claim that
`that's fully disclosed in Woerlee.
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`So the question, if it is a question about where the active region is, or
`if it's bounded by isolation or if in your articulation there needs to be a
`one-to-one correspondence, we believe that that is kind of legally erroneous.
`But we have a combination of references and to the extent that there is a
`question about the presence of an active region so defined, Woerlee
`describes that.
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`JUDGE ARBES: But I thought it was your position that the only
`modification you are making to figure 12 then is to add the STIs on both
`sides in the figure showing on slide 20 -- that figure 12 has the protruding
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`limitation in your view and we add the two STIs on the side and that gets us
`the full claim. That's your position. You're not relying on the single
`transistor embodiment of Woerlee, right?
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`MR. CAVANAUGH: We believe that a one-to-one correspondence is
`a misarticulation of the requirement of the claim.
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`JUDGE ARBES: I understand that.
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`MR. CAVANAUGH: Full stop.
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`JUDGE ARBES: But assuming for the moment that we agree with
`Patent Owner.
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`MR. CAVANAUGH: Right. And we have moved through this
`proceeding with the recognition that those two transistors share a common
`isolation region and so from a --
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`JUDGE ARBES: Active region?
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`MR. CAVANAUGH: I'm sorry, active region. I apologize. And so
`to Your Honor's question, there is -- if you were to consider a one-to-one
`correspondence, I would have to kind of review how we characterize those
`two transistors of Igarashi. But what I will say is that just simply adding a
`transistor, and we've asked Dr. Glew that question. If you add a transistor to
`an active region so it's two transistors, does that make it not an active region
`and he couldn't opine on that.
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`JUDGE ARBES: Well the question is not whether it makes it not an
`active region but whether it meets the limitation of the claim, right? The
`claim says the MISFET includes an active region made of a semiconductor
`substrate. That's what we're looking for in the prior art, not an active region
`in general, which clearly was known.
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`MR. CAVANAUGH: Right.
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`JUDGE ARBES: We're looking for this specific limitation.
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`MR. CAVANAUGH: Right. I understand that and I think that I can
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`do a couple of different things with regard to that particular limitation and I
`think I want to move to another portion of the presentation which actually
`responds to the Patent Owner's argument because they've moved a little bit
`from how they interpreted the claims and I think we want to go to -- there's
`two questions, Judge Arbes, that I'm hearing in your question. One is a
`claim construction question and then the second is how the prior art meets
`that claim either so construed or how it meets it as we construe it, so I'm
`going to try to answer those in parallel but I'll kind of flip from our
`proposed, what we think is the correct construction to what the Patent
`Owner, how the Patent Owner has construed it and how we believe that's
`inconsistent with how the term should be construed.
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`So if we go to slide -- why don't we start with slide 29 and then go
`from there, and here we asked Dr. Glew recognizing that the Patent Owner
`has taken the position both in the POPR and we believe the Board correctly
`rejected that position, what was the basis for that one-to-one
`correspondence? Is it based on the language of the claim includes, so the
`MISFET includes an active region made of a semiconductor substrate and
`here their expert, Dr. Glew, indicates that includes is kind of the normal
`open ended construction that one would have. That if there's nothing about
`the word includes that would require that that MISFET have an active region
`and that no other -- it can't be shared by any other person or any other
`MISFET. So we asked him, includes can't be the basis for a one-to-one
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`correspondence and then maybe go to the next slide. But we did ask him
`about what components of the active region would be because if their
`position is that figure 12 doesn't disclose an active region but if it has all the
`components of what an active region would be, that suggests strongly that it
`would be an active region regardless of whether there's one or two
`transistors and we asked what are the components of an active region, and he
`would say it includes -- and this is slide 30 -- it would include at least the
`source channel and drain regions for a typical transistor which is exactly
`what's in figure 12.
`
`And then if we go to the next slide. We cited some textbooks as I
`mentioned in the early part of this presentation and in our petition, but the
`textbooks cited are confirming that transistors are built in active regions.
`Now it doesn't answer the question because the question wasn't precisely put
`to the textbook in order to get it but it is at least consistent with what our
`position is.
`
`If we go to the next slide. And one of the things that we did with our
`reply and the Patent Owner has challenged some of the arguments that we've
`made as new arguments, and I'll address that in a moment, but I want to
`continue with the active region. So the Patent Owner said it was nonsensical
`to have two transistors with a single active region but what we did with our
`reply was to provide a reference that clearly showed two transistors
`associated with an active region, and that's Agata and that's on slide 32, 10a
`and 10b are transistors and element 2 which is highlighted in blue is the
`active region.
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`JUDGE ARBES: Counsel, just going back to the claim language.
`
`Doesn't the word includes and how it's used in claim 1 imply that there is
`that one-to-one correspondence between the MISFET and the active region?
`The active region is for this MISFET, not another one. Doesn't the word
`includes and how it's used there imply that in some sense?
`
`MR. CAVANAUGH: I don't think so, Your Honor, and here's why.
`MISFET includes an active region but it's not clear whether or not that
`active region would be exclusive to that MISFET which is the Patent
`Owner's position, or that that active region could be kind of applied in other
`transistors, and the various elements whether or not the silicon nitride film is
`associated with a particular MISFET or kind of overarching, overlaid across
`several MISFETs. I mean where I think Your Honor, where I disagree with
`the perspective that includes is suggesting a narrow construction is that
`MISFET includes an active region. It's not saying that the active region
`must be specifically identified with that MISFET, it just means there must be
`a MISFET exclusively identified with that MISFET. It just says that there
`must be an active region associated with that MISFET.
`
`JUDGE ARBES: What about the specification of the 501 patent? In
`interpreting claim 1 we should look to the specification, in particular to
`figures 1 and 4A that the applicants pointed to during prosecution. Those
`embodiments at least have the one-to-one correspondence, right?
`
`MR. CAVANAUGH: That's correct. I agree with that.
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`JUDGE ARBES: And are there any embodiments disclosed in the
`specification that don't have the one-to-one correspondence?
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`MR. CAVANAUGH: I'm not sure I can answer your question
`
`specifically. I'm not aware of one right now but there may be, but I do think
`it's important to recognize that the Fed. Circuit, our reviewing court in this
`Board, is pretty clear that we're not to adopt a construction that is from the
`specification based on kind of interpreting either some characteristic in this
`case or language from the specification into the claim.
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`JUDGE ARBES: One more question about the specification.
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`MR. CAVANAUGH: Sure.
`
`JUDGE ARBES: Figure 1 in particular includes two labels at the top
`of the figure for the formation regions, Rn and Rp, so we're talking about
`two transistors there that have these formation regions that I believe is
`talking collectively about the device as a whole. So it has a one-to-one
`correspondence but then the active region and the MISFET there, and the
`active region is bound by the isolation regions, does that not support Patent
`Owner's interpretation?
`
`MR. CAVANAUGH: I think it is not inconsistent with the Patent
`Owner's interpretation but it's not supportive and it certainly doesn't counsel
`that somehow what's illustrated in the claim should be kind of the
`interpretative tool to how the words of the claim should be interpreted.
`
`JUDGE HAAPALA: Counsel, I think the question is we do have to
`have our interpretations consistent with the specification and so is there -- all
`the embodiments disclosed have one active region and so is bounded by the
`isolation region, would it be inconsistent of us to interpret the claim to
`permit two -- one active region shared by two transistors?
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`MR. CAVANAUGH: Would it be inconsistent? You know, I think
`
`that the fact that an illustration corresponds to a claim is consistent. They
`have said the interpretation of claim 1 is supported by figure 1 and they've
`said that in the file history. I think it is importing a limitation from the
`specification, particularly the illustration, to say that the word includes
`which their expert agrees is broad and it should be more broadly construed
`and use that as a basis to say because it's in figure 1 or figure 4A that
`somehow the Patent Owner was specifically kind of characterizing the claim
`or the invention in a particular way. Recall that that limitation had been
`present during prosecution all the time the examiner was rejecting it and no
`one made that one-to-one correspondence argument during prosecution and
`the examiner kind of repeatedly rejected the claims. So --
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`JUDGE HAAPALA: Okay. I'm going to interrupt you, I see your
`point but right now we have to decide whether the -- what's before us in the
`petition. We can't really look back into what the examiner was looking at
`unless you present that in your petition.
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`MR. CAVANAUGH: Sure.
`
`JUDGE HAAPALA: I understand your point about the examiner, you
`know, that during prosecution it appears the examiner focused on the last
`limitation but what we need to decide today is whether the grounds you
`assert render the claim unpatentable or obvious. So I think the question is
`when we go to the claim construction, again, I understand what you're
`saying that we don't want to import limitations into the claim, but if you
`could just look to figure 1 and figure 4 and say that has to be that way with
`the entire specification? Perhaps and I understand you haven't conceded that
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`point, but if the entire specification only shows a one-to-one
`correspondence, would it be inconsistent of us to then say it's okay to have a
`region shared by two transistors?
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`MR. CAVANAUGH: I think I understand your questi
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