asy United States
`a2) Patent Application Publication co) Pub. No.: US 2002/0006032 Al
`(43) Pub. Date: Jan. 17, 2002
`
`Karabatsos
`
`US 20020006032A1
`
`(54) LOW-PROFILE REGISTERED DIMM
`
`Publication Classification
`
`(76)
`
`Inventor: Chris Karabatsos, Kingston, NY (US)
`
`(51) UN, C17 iceccccscssssssssssntsssneenstnesesse HOSK 7/02
`(52) US. Ch.
`coecssosesssssssnstnsssssentnesstnenssstses 361/760
`
`(57)
`
`ABSTRACT
`
`Lexington, MA 02420 (US)
`
`(21) Appl. No.:
`
`09/758,791
`
`(22)
`
`Filed:
`
`Jan. 11, 2001
`
`Related U.S. Application Data
`
`Correspondence Address:
`Mark P. White
`Suite 103
`A lowprofile, registered DIMM hasaheight of about 1.2
`57 Bedford Street
`inches, and a width of about 5.25 inches. This reduced size
`is accomplished by arranging the SDRAMsinto a Icft group
`and a right group within a single row, with a space between
`the groups into which all other major components are
`disposed.
`In addition,
`the pad extensions beyond the
`SDRAM pinsare maintained at about 0.1 mm,the footprints
`of the pads to accept the SDRAMsare a minimum of 11.76
`mm, as measured by the lengthwise distance from thefirst
`pad in a footprint to the pad furthest away, and the space
`between adjacent pads is between 0.127 mm and 0.750 mm.
`
`(63) Non-provisional of provisional
`60/206,287, filed on May 23, 2000.
`
`application No.
`
`
`
`1
`
`KINGSTON 1003
`
`KINGSTON 1003
`
`

`

`Patent Application Publication
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`Jan. 17, 2002 Sheet 1 of 9
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`Patent Application Publication
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`

`US 2002/0006032 A1
`
`Jan. 17, 2002
`
`LOW-PROFILE REGISTERED DIMM
`
`{0001] This application claims priority based on Provi-
`sional Application No. 60/206,287, filed on May 23, 2000.
`
`BACKGROUND OF THE INVENTION
`
`[0002]
`
`1. Field of the Invention
`
`invention relates to a low-profile
`[0003] The present
`DIMM memory board for use in personal computers, and
`more specifically, to such a memory board providing a high
`density of memory chips in a board configuration approxi-
`mately 1.2 inches in height.
`
`[0004]
`
`2. Description Relative to the Prior Art
`
`random-access
`their
`[0005] Modem computers have
`memory (RAM)configured as separate memory modules,
`formed of a plurality of individual memory PC boards, with
`memory chips mounted thereon. These memory modules
`include SIMMS(Single In-line Memory Modules), which
`were initially designed as 30 pin, 8 bit wide assemblies
`which mated with a suitable 30 pin female socket. Soon
`however increasing computer memory demands saw the
`introduction of a memory module extender which permitted
`single 30 pin SIMM socketsto receive a plurality of 30 pin
`SIMMs.
`
`[0006] As memory requirements became more demand-
`ing, 64 bit Dual
`In-line Memory Modules, hereinafter
`referred to as DIMMswere designed and incorporated into
`personal computers, requiring 168 pin sockets.
`
`[0007] The continuing development of new memory mod-
`ules has highlighted the continuing increase in the amount of
`RAM needed in the modem computer, as programs running
`on these computers require more and more memory to
`operate. As an example, the newer versions of Microsoft’s
`Windows® operating systems requires up to 128 Mbytes of
`RAM to operate efficiently.
`
`the incorporation of multi-media
`{0008] Furthermore,
`functions
`into modern software means that computer
`memory must operate at higher and higher speeds. As a
`result, the computer industry is faced with every increasing
`pressures to produce memory modules including more and
`more memory, in smaller and smaller packages.
`
`[0009] The standards for computer memoriesare currently
`maintained by The JEDEC® Solid State Technology Asso-
`ciation, once known as the Joint Electron Device Engineer-
`ing Council. JEDEC is the semiconductor engineering stan-
`dardization body of the Electronic Industries Alliance (EIA),
`a trade association that represents all areas of the electronics
`industry. More information on this organization appears on
`its WEBsite at http:/Awwwyjedec.org.
`
`JEDECstandardsare currently used in conjunction
`[0010]
`with the following configurations of DIMMS:
`
`a) MO160-B-72 Pin Dual-In-Line Memory
`(0011]
`Module (DIMM) Family with 1.27 mm Contact
`Centers.
`
`c)MO177-A-200 Pin Small Outline Dual-In-
`[0013]
`Line Memory Module (DIMM) Family, 0.65 mm
`Pitch. MO179-A-278 Pin Dual-In-Line Memory
`module (DIMM) Family with 1.00 Lead Centers.
`
`d)M0O190-C-144 Pin Small Outline Dual-In-
`[0014]
`Line Memory Module (DIMM) Family 0.8 mm Lead
`Centers. Item
`
`©) MO191-A-160 Pin Dual-In-Line Memory
`[0015]
`Module (DIMM) Family, 1.27 mm Lead Centers.
`
`f) M0O206-A-184 Pin DDR Dual-In-Line
`[0016]
`Memory Module (DIMM)Family, 1.27 mm Contact
`Centers.
`
`g) MO214-A-144 Pin Micro Dual-In-Line
`[0017]
`Memory Module (DIMM), 0.50 mmPitch.
`
`h) MO224-A-200 Pin DDR Small Outline
`[0018]
`Dual-In-Line Memory Module (SODIMM)Family,
`0.60 mm Contact Centers. Item 11.14-043.
`
`i) MO227-A-232 Pin DDR SDRAM DIMM
`[0019]
`Family, 1.00 mm Pitch.
`
`[0020] All of the above DIMMs, when using registers
`and/or PLLs, have profiles of 1.5 inches or greater. The
`unavailability of DIMMs with lower profiles has had a
`serious, negative effect on many computer designs.
`
`[0021] As an example, a common system standard for
`servers has a rack-mounted enclosure, with an external
`cabinet height of 1.75 inches. Manufacturers of these sys-
`tems includes Network Engines,Inc., of Canton, Mass., and
`their “Roadster LX” is an representative example of such
`systems. This configuration became an industry standard
`prior to the appearance of the DIMM as a memorystandard.
`
`In orderto fit the currently-available DIMMsinto
`[0022]
`these cabinets, the manufacturers have had to take extraor-
`dinary steps, including slanting the DIMM sockets at 224%
`degrees. Slanting the sockets in this way causes maintenance
`and accessability problems, and takes up an inordinate
`amount of space within the cabinet.
`
`[0023] DIMMSare currently generally populated with
`SDRAM chipsof a configuration as shown in FIG.6. This
`SDRAM has 66 pin, with a width d4, of 11.76 mm from end
`of pin to end of pin, as shown, and a body width d5 of 10.16
`mm. FIG. 4A shows the top side of a DIMM module
`manufactured by Intel®. The specifications for this module
`are shown in the table provided as Appendix A. Byreferring
`to FIG. 4A, it is seen that the top face of the module is
`populated not only by SDRAMs2, but also by some
`additional chips 5, mounted sideways below the SDRAMs
`on the face. Similarly, the back face of the same module, as
`shownin FIG.4B, could contains additional chips, although
`these are not shown in the figure. The non-SDRAM chips on
`both faces of this prior art DIMM require that the multilayer
`board be at least 1.5 inches in height. FIG. 2A shows the
`front side of this Intel DIMM, while FIG. 2B showsthe back
`side. The height A of this DIMM is 1.7 inches.
`
`b) MO167-C-128 Pin Dual-In-Line memory
`[0012]
`Module (DIMM) Family, 1.27 mm Lead Centers.
`MO172-D-112 & 200 Pin Dual-In-Line Memory
`Module (DIMM)Family, 1.27 mm Pitch.
`
`[0024] The specifications for a different prior art DIMM,
`manufactured by IBM®, appear attached hereto as Appen-
`dix B. Referring now to Appendix B, the heightof all of the
`DIMMsin this family 1.7 inches.
`
`11
`11
`
`

`

`US 2002/0006032 A1
`
`Jan. 17, 2002
`
`[0025] A review of the priorart of all the major manufac-
`turers fails to show any DIMMswith an overall height of
`less than 1.5 inches, despite the obvious need expresses by
`the industry.
`
`[0026] The current invention, however, provides a DIMM
`memory module in a 168, 184, and 200-pin , low profile
`configuration, with a height of only 1.2 inches, therefore
`solving the height problem which the industry has long
`sought to remedy.
`
`SUMMARYOF THE INVENTION
`
`It is a general object of the present invention to
`[0027]
`provide a low profile DIMM with a height of between 1.125
`and 1.250 inches, while still maintaining the memory capac-
`ity, speed, and performance of the higher-profile DIMMs.It
`is a specific object of this invention to provide techniques
`allowing the reduction in profile of memory boards, and of
`similar electronic boards.
`
`In accordance with one aspect of the invention, a
`[0028]
`low-profile DIMM includes two or more printed circuit
`boards, bonded together to form a single multilayer board,
`having two sides, said board having a height of approxi-
`mately 1.2 inches, and a width of approximately 5.25 inches.
`The invention includes a number of SDRAM chips, and a
`number of other components, so that, on each side of the
`multilayer board the SDRAM chipsare arranged in a single
`rowseparated into a left group and a right group with a space
`between the groups, and whereall the other components of
`significantsize are disposed in the space between the groups.
`
`In accordance with a second aspect of the inven-
`[0029]
`tion, the left group consists of 5 SDRAM chips,and the right
`group contains 4 SDRAM chips.
`
`In accordance with a third aspect of the invention,
`[0030]
`, the left group consists of 4 SDRAM chips, and the right
`group contains 5 SDRAM chips.
`
`In accordance with a fourth aspect of the invention,
`(0031]
`each of the SDRAM chips has a number of pins, and the
`DIMMfurther includes a number of SDRAM mounting
`areas, each having two rows, each row having a multiplicity
`of pads, each pad electrically connected to one of the pins of
`a corresponding SDRAM chip, and cach pad having an
`extension beyond the corresponding pin of about 0.1 mm.
`The maximum distance allowed between the end of the pad
`in one row to the end of the corresponding pad in the other
`row in a mounting area is about 11.76 mm.
`
`In accordance with a fifth aspect of the invention,
`[0032]
`the space between adjacent pads is between 0.127 mm and
`0.750 mm.
`
`In accordance with a sixth aspect of the invention,
`[0033]
`the DIMM includes a Register chip, where the Register chip
`has a major axis,
`the DIMM has a major axis, and each
`SDRAM chip has a body and a major axis, and where the
`register chip is oriented with its major axis parallel to the
`major axis of the DIMM, and each SDRAM chip has it
`major axis oriented perpendicular to the major axis of the
`DIMM.
`
`In accordance with a seventh aspect of the inven-
`[0034]
`tion, the additional components include a numberof decou-
`pling capacitors, where each decoupling capacitor
`is
`mounted to the DIMM in proximity to the SDRAM pin
`
`closest to an end of the SDRAM,andless than or equal to
`0.7 mm from the body of the SDRAM.
`
`In accordance with a final aspect of the invention,
`[0035]
`the low-profile DIMM,includes two or more printed circuit
`boards, bonded together to form a single multilayer board,
`having two sides,
`the board having a height of approxi-
`mately 1.2 inches, and a width of approximately 5.25 inches.
`On eachside of the board is mounted a number of SDRAM
`
`chips, each having a major axis, arranged in a single row,
`and all save one having its major axis perpendicular to the
`major axis of the multilayer board. The row hasa left group
`comprising 4 SDRAMS, anda right group of 4 SDRAMS
`with a space between the groups. The remaining SDRAM is
`mounted in the space between the groups, its major axis
`perpendicular to the major axis of the DIMM. The board also
`contains a number of other components, mounted on both
`sides of the multilayer board, andall these other components
`of significant size are mounted in the space betweentheleft
`and right groups.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0036] These, and further featuresof the invention, may be
`better understood with reference to the accompanying speci-
`fication and drawings depicting the preferred embodiment,
`in which:
`
`(0037] FIG. 1A depicts a front elevation view the front
`face of the DIMM with components mounted, in the 5-4
`configuration.
`
`[0038] FIG. 1B depicts a front elevation view the front
`face of the DIMM with components mounted, in the 4-5
`configuration.
`
`[0039] FIG. 1A depicts a front elevation view the front
`face of the DIMM with components mounted, in the 4-4
`configuration.
`
`[0040] FIG. 2A depicts the front elevation view of a
`two-sided DIMM memory board of the prior art, without
`components mounted.
`
`[0041] FIG. 2B depicts a back side elevation view of a
`two-sided DIMM memoryofthe prior art, without compo-
`nents mounted.
`
`[0042] FIG. 3 depicts top face of the printed circuit
`features of the current DIMM memory board without the
`components mounted.
`
`[0043] FIG. 4A depicts a prior art DIMM configuration,
`top side.
`
`[0044] FIG. 4B depicts a prior art DIMM configuration,
`bottom side.
`
`[0045] FIG. 5A depicts a cross-sectional view of two
`adjacent SDRAMs mounted on the PC board.
`
`[0046] FIG. 5B depicts a close-up view of the pin and pad
`on the left-hand side of FIG. 5A.
`
`[0047] FIG. 6 depicts a exemplary SDRAM chip, show-
`ing pin spacing.
`
`12
`12
`
`

`

`US 2002/0006032 A1
`
`Jan. 17, 2002
`
`DEFINITIONS
`
`In the following disclosure the definitions below
`[0048]
`will be used:
`
`a) PC board: the multi-layer board on which
`[0049]
`the SDRAM memorychips, register chips, and other
`components are mounted.
`
`b) Module, or Memory Module: the PC board
`[0050]
`with the components mounted thereon.
`
`this term is used inter-
`c) Memory Chips:
`[0051]
`changeably with, or in combination with, the term
`SDRAM,whichrefers to a particular memory chip.
`
`DESCRIPTION OF TITE PREPERRED
`EMBODIMENTS
`
`invention is a
`[0052] This embodiment of the current
`configuration of a DIMM memory module which has a high
`density of memory chips on both sides of the board, pro-
`viding a high memorycapacity, with a board dimension of
`approximately 1.2 inches in height, by a width of approxi-
`mately 5.25 inches. Using the techniques and configurations
`described herein, the current invention provides memory
`capacity up to 1 GBytes, according to the current technology
`in memory chips.
`
`[0053] The ability to configure the DIMM into a PC
`(printed circuit) board only 1.2 inches in height depends
`upon using several different techniques in combination.
`
`First, the SDRAM memory chips are mounted in a
`[0054]
`single row with their major axis perpendicular to the major
`axis of the PC board. The row of SDRAMsis divided into
`
`a left half group and a right half group, with a space between
`them. The other major components, in this case semicon-
`ductor chips, are mounted in the space betweenthe left half
`and right half groups. Thus,the limitation in height of the PC
`board becomes,in effect, the length of the SDRAM,with a
`margin above and below the SDRAM row for mounting,
`edge connector, etc.
`
`[0055] A second technique for reducing the size of the
`module involves restricting the size of the pad upon which
`the SDRAMs are mounted, and restricting the space
`between adjacent pads.
`
`COMPONENT MOUNTING
`
`[0056] FIG. 1A depicts the front face of a two-sided
`DIMM memory board of the current
`invention without
`components mounted. Referring to this figure, the overall
`length D1 is 5.25 inches, while the overall height A is 1.2
`inches. This height is significantly smaller than the JEDEC
`standard for this configuration, which is between 1.5 and 1.7
`inches. FIG. 1A has 5 SDRAMs mountedto theleft of the
`central gap, or space, and 4 SDRAMsto therightof the gap.
`The gap is seen as containing the Register chip 6, and the
`PLL (phase-locked loop) chip, 8. This configuration in
`referred to hereinafter as the 5-4 configuration.
`
`[0057] FIG. 1B depicts a variation of this same configu-
`ration, with 4 SDRAMs mountedto the left of the gap, and
`5 SDRAMsto the right. The configuration of FIG. 1B is
`referred to hereinafter as the 4-5 configuration.
`
`[0058] FIG. 1C depicts a second variation, referred to as
`the 4-1-4 configuration. In this configuration, the gap con-
`
`tains an SDRAM,although rotated so that the major axis of
`the SDRAM isparallel to the major axis of the module, with
`the Register chip and PLL chip below the SDRAM in the
`central gap.
`
`[0059] Regardless of which of these variations is used, it
`is still necessary to have 9 SDRAMsoneither side of the
`module, in order to provide the required memory capacity
`for the current application. The overall module size is the
`same for all three variations described above.
`
`[0060] Still referring to FIGS. 1A, 1B, and 1C,it is seen
`that the area on which components may be mounted extends
`overthe entire height of the board at the top of the board, and
`is only slightly less at the bottom. The comb of connector
`contacts at the bottom of the module contains 184 contact
`
`fingers, and is designed to mate with a 184-pin edge con-
`nector.
`
`[0061] Referring now to FIGS. 1A, 1B, and 1C, the back
`face of the board is essentially the mirror image ofthe front
`face, with the exception of the Register chip and PLL chip,
`which only appear on oneside.
`
`[0062] Although not shown in these figures, the DIMM
`PC board is a multilayer board, typically having six layers.
`The surface layers, as shown in FIG. 3 (the top layer),
`contain the connections to the components mounted on the
`surfaces. Directly beneath the surface layers are the ground
`plane, beneath one surface, and the Vcc (power) plane on the
`other surface. And in the center, between the ground and Vec
`planes, are the signal printed wires, and the clock printed
`wires, Communications between layers is done by meansof
`feed-throughs, whichare plated-through holes to make good
`electrical connections between the layers.
`
`In the figures described above, in a line above the
`[0063]
`SDRAM chips appear a number of decoupling capacitors 4,
`which have their long axes parallel to the major axis of the
`DIMMboard, further reducing the size of the component
`area. Each decoupling capacitor is mounted to the DIMM in
`proximity to the SDRAM pin closest to an end of the
`SDRAM,andless than or equal to 0.7 mm from the body of
`the SDRAM.
`
`in the 5-4
`[0064] The board itself is shown in FIG. 3,
`configuration. The left group of 5 SDRAMsis mounted on
`the five SDRAM mounting areas 23 as shown in FIG.3.
`Shown in this figure are the bus wires, which electrically
`attach the same pad numberof each SDRAM mounting area
`in the left group with every other pad of the same number:
`that is, pad no. “n” of the left-most SDRAM in the group is
`attached to pad no. “n” of the next-to-left-most SDRAM
`mounting, area in the group, etc. This figure further shows
`that each printed bus wire in the left group has a feed through
`24 located in the middle of the middle SDRAM mounting
`area. Each feed through connects with a printed wire on the
`back of the surface layer or on another layer of the multi-
`layer board.
`
`[0065] Referring again to FIGS. 1A and 1B,it is noted
`that
`the SDRAMs 2 are mounted with their major axis
`perpendicular to the major axis of the PC board. There are
`only small margins above and below the SDRAMs.Only the
`decoupling capacitors 4 appear above the SDRAMs, and
`these are mounted with their major axis parallel to the major
`axis of the PC board, so that the amount of space required
`for their mounting is minimized. A number of small com-
`
`13
`13
`
`

`

`US 2002/0006032 A1
`
`Jan. 17, 2002
`
`ponents are mounted below the SDRAMsin FIGS. 1A,1B,
`and 1C. The major components are mounted in the gap
`between the left group of SDRAMsand the right group.
`
`[0066] The configuration shown in FIGS.1A, 1B, and 1C
`is a departure from the prior art,
`in which the major
`components were mounted below the bottom of
`the
`SDRAMs,thus requiring additional height of the PC board
`to accommodate them.
`
`[0067] Regardless of the configuration used, whether 5-4,
`4-5, or 4-1-4, the principle governing the configurationis the
`same: first, all, or all but one, of the SDRAMsare mounted
`in a single row, with a gap in the center, and at least four
`SDRAMson each side of the gap; next, the height of the
`boardis substantially the dimension of the major axis ofthe
`SDRAM;with all other components of any significant size
`mounted in the gap; andfinally, the components mounted on
`the margins of the board are oriented with their major axis
`parallel to the major axis of the module.
`CONFIGURATION OF THE SDRAM
`MOUNTING PADS
`
`able to reduce the height of the DIMM module to approxi-
`mately 1.2 inches. As has been mentioned, however, these
`techniques may be used separately to advantage in other
`printed circuit applications.
`
`[0074] While the invention has been described with ref-
`erence to specific embodiments,
`it will be apparent
`that
`improvements and modifications may be made within the
`purviewof the invention without departing from the scope
`of the invention defined in the appended claims.
`I claim:
`
`1. A low-profile DIMM, comprising:
`
`(a) two or more printed circuit boards, bonded together to
`form a single multilayer board, having twosides, said
`board having a height of approximately 1.2 inches, and
`a width of approximately 5.25 inches; and
`
`(b) on each side, a multiplicity of SDRAM chips, each
`having a major axis; and
`
`(c) a multiplicity of other components, mounted on both
`sides of said multilayer board,
`
`[0068] A-second major consideration in the configuration
`and wherein, on each side of the multilayer board the
`of the memory moduleis the layout of the pads. Referring
`SDRAM chipsare arranged in a single row,all their
`now to FIG. 5A, a cross-sectional view of two adjacent
`major axis perpendicular to the major axis of the
`SDRAMs mounted on the PC board is shown. A left
`multilayer board, said row further comprisingaleft
`SDRAM 42is attached to pad 48, affixed ta PC board 46, by
`group and a right group with a space between the
`means of pin 55. A right SDRAM 44is attached to pad 50,
`groups, and wherein all the other components of
`also affixed to the PC board, via pin 56.
`significant size are mounted in the space between the
`left and right groups.
`2. The DIMM ofclaim 1, wherein the left group further
`comprises 5 SDRAM chips, and wherein the right group
`further comprises 4 SDRAM chips.
`3. The DIMM ofclaim 1, wherein the left group further
`comprises 4 SDRAM chips, and wherein the right group
`further comprises 5 SDRAM chips.
`4. The DIMM ofclaims 1, 2 or 3, wherein each of the
`SDRAM chips further comprises a plurality of pins, the
`DIMMfurther comprising a multiplicity of SDRAM mount-
`ing areas, each comprising two rows, each row further
`comprising a plurality of pads, each pad electrically con-
`nected to one of the pins of a corresponding SDRAM chip,
`each such pad having an extension beyond the correspond-
`ing pin of about 0.1 mm after said pins are soldered to said
`pads.
`5. The DIMM of claim 4, wherein the space between
`adjacent pads is between 0.127 mm and 0.750 mm.
`6. The DIMM ofclaim 1, wherein the space between
`adjacent pads is between 0.127 mm and 0.750 mm.
`7. The DIMM of claim 6, wherein the left group further
`comprises 5 SDRAM chips, and wherein the right group
`further comprises 4 SDRAM chips.
`8. The DIMM of claim 6, wherein the left group further
`comprises 4 SDRAM chips, and wherein the right group
`further comprises 5 SDRAM chips.
`9. The DIMM ofclaims 6, 7 or 8, wherein each of the
`SDRAM chips further comprises a plurality of pins, the
`DIMMfurther comprising a multiplicity of SDRAM mount-
`ing areas, each comprising two rows, each row further
`comprising a plurality of pads, each pad electrically con-
`nected to one of the pins of a corresponding SDRAM chip,
`each such pad having an extension beyond the correspond-
`ing pin of about 0.1 mm after said pins are soldered to said
`pads.
`
`In the current invention, the distance from the end
`[0069]
`of SDRAM pin 55 to the end of the corresponding pad 48,
`shownas d1 in FIG.5, is about 0.1 mm, after soldering of
`the multilayer board has been completed. The space between
`adjacent pads, shownin FIG.5 as d2, is between 0.127 mm
`to 0.750 mm.
`
`[0070] The reasonfor the restriction of the first dimension
`may be seen by referring to FIG. 5B, showing a close-up
`view of the left-most pad of FIG. 5A. This view showsthe
`connection between the pin 55 and the pad 48 after solder-
`ing. A solder bump 57 is shownin this figure, exaggerated
`for emphasis. The existence of this bump can prevent stress
`on the underlying joint exerted by the pin, which would
`makingthe joint subject to cracking and other stress failures.
`If the distance dl becomes too small, or goes negative, there
`is the risk of joint failure due to stresses. So the dimension
`used here for distance d1 must be maintained at a minimum
`of 0.1 mm.
`
`[0071] Also shown in this drawing is dimension d2, the
`space between adjacent pads. It is necessary to make this
`space as small as possible, but to still leave enough room
`between adjacent pads to avoid the danger of shorting. The
`optimum dimension for this inter-pad distance has been
`found to be 0.7 mm. Other, smaller dimensions are also
`acceptable, with the smallest allowable dimension being
`0.127 mm.
`
`the length of the
`[0072] Referring now to FIG. 4B,
`“footprint” of the SDRAM, that is, distance between the first
`and last pad, as measured lengthwise along the SDRAM
`mounting area, and shown in FIG.4B as dimension d3,is
`a minimum of 11.76 mm.
`
`It has been found necessary to incorporate a com-
`[0073]
`bination ofall the techniques described herein in order to be
`
`14
`14
`
`

`

`US 2002/0006032 A1
`
`Jan. 17, 2002
`
`areas, each comprising two rows, each row further compris-
`ing a plurality of pads, each pad electrically connected to
`oneof the pins of a corresponding SDRAM chip, each such
`pad having an extension beyond the corresponding pin of
`about 0.1 mm minimum after said pins are soldered to said
`pads.
`17. The DIMMofclaim 13, wherein each of the SDRAM
`chips further comprises a plurality of pins,
`the DIMM
`further comprising a multiplicity of SDRAM mounting
`areas, each comprising two rows, each row further compris-
`ing a plurality of pads, each pad electrically connected to
`ne of the pins of a corresponding SDRAM chip, each such
`pad having an extension beyond the corresponding pin of
`about 0.1 mm minimum after said pins are soldered to said
`pads.
`18. The DIMM ofclaim 16, further comprising a Register
`chip having a major axis, and wherein the register chip is
`mounted with its major axis parallel to the major axis of the
`DIMM.
`
`°
`
`19. The DIMM of claim 18, further comprising a PLL
`chip having a major axis, and wherein the PLL chip is
`mounted with its major axis parallel to the major axis of the
`DIMM.
`20. The DIMM of claims 13, 14 or 17 wherein the
`additional components further comprise a plurality of decou-
`pling capacitors each having a major axis, and wherein each
`decoupling capacitor is mounted, with its major axis parallel
`to the major axis of the DIMM,in proximity to the SDRAM
`pin closes to an end of said SDRAM,andless than or equal
`to 0.7 mm from the body of the SDRAM.
`21. The DIMM ofclaim 15 wherein the additional com-
`
`ponents further comprise a plurality of decoupling capaci-
`tors each having a major axis, and wherein each decoupling
`capacitor is mounted, with its major axis parallel to the
`major axis of the DIMM,in proximity to the SDRAM pin
`closes to an end of said SDRAM, and less than or equal to
`0.7 mmfrom the body of the SDRAM.
`22. The DIMM of claim 16, wherein the additional
`components further comprise a plurality of decoupling
`capacitors each having a major axis, and wherein each
`decoupling capacitor is mounted, with its major axis parallel
`to the major axis of the DIMM,in proximity to the SDRAM
`pin closes to an end of said SDRAM,andless than or equal
`to 0.7 mm from the body of the SDRAM.
`*
`*
`*
`*
`*
`
`10. ‘the DIMM ofclaim 9, further comprising a Register
`chip having a major axis, and wherein the register chip is
`mounted with its major axis parallel to the major axis of the
`DIMM.
`
`11. The DIMM ofclaim 10, further comprising a PLT. chip
`having a major axis, and wherein the PLL chip is mounted
`with its major axis parallel to the major axis of the DIMM.
`12. The DIMMofclaims 1, 2, 3, 6, 7 or 8 wherein the
`additional components further comprisea plurality of decou-
`pling capacitors each having a major axis, and wherein each
`decoupling capacitor is mounted, with its major axis parallel
`to the major axis of the DIMM,in proximity to the SDRAM
`pin closes to an end of said SDRAM,andless than or equal
`to 0.7 mm from the body of the SDRAM.
`13. A low-profile DIMM, comprising:
`
`(a) two or more printed circuit boards, bonded together to
`form a single multilayer board, having two sides, said
`board having a height of approximately 1.2 inches, and
`a width of approximately 5.25 inches; and
`
`(b) on each side, a multiplicity of SDRAM chips, each
`having a major axis, arranged in a single row,all save
`one having its major axis perpendicular to the major
`axis of the multilayer board, said row further compris-
`ing a left group comprising 4 SDRAMS, anda right
`group comprising 4 SDRAMSwith a space between
`the groups, and wherein the remaining SDRAM is
`mountedin the space between the groups, its major axis
`perpendicular to the major axis of the DIMM; and
`
`a multiplicity of other components, mounted on both sides
`of said multilayer board, all the other components of
`significant size are mounted in the space between the
`left and right groups.
`14. The DIMMofclaim 13, wherein each of the SDRAM
`chips further comprises a plurality of pins,
`the DIMM
`further comprising a multiplicity of SDRAM mounting
`areas, each comprising two rows, each row further compris-
`ing a plurality of pads, each pad electrically connected to
`one of the pins of a corresponding SDRAM chip, each such
`pad having an extension beyond the correspondingpin of 0.1
`mm minimum after said pins are soldered to said pads.
`15. The DIMM of claim 13 or 14, wherein the space
`between adjacent pads is between 0.127 mm and 0.750 mm.
`16. The DIMMofclaims 15, wherein each of the SDRAM
`chips further comprises a plurality of pins,
`the DIMM
`further comprising a multiplicity of SDRAM mounting
`
`15
`15
`
`