UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`KINGSTON TECHNOLOGY COMPANY, INC.,
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`Petitioner
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`v.
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`POLARIS INNOVATIONS LTD.,
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`Patent Owner
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`
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`
`
`Case No. IPR2016-01622
`Patent 6,850,414
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`
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`
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`PETITION FOR INTER PARTES REVIEW OF
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`U.S. PATENT NO. 6,850,414
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`
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`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`1
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`Polaris Innovations Ltd. Exhibit 2008
`Kingston v. Polaris, IPR2017-00974
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`TABLE OF CONTENTS
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`Page
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`INTRODUCTION AND RELIEF REQUESTED ......................................... 1 
`I. 
`GROUNDS FOR STANDING ...................................................................... 1 
`II. 
`III.  MANDATORY NOTICES ............................................................................ 1 
`IV.  BACKGROUND ............................................................................................ 2 
`A. 
`Description of the ’414 Patent ............................................................. 2 
`B. 
`Prosecution History .............................................................................. 5 
`C. 
`Person of Ordinary Skill in the Art ...................................................... 5 
`D. 
`State of the Art ..................................................................................... 6 
`CLAIM CONSTRUCTION ........................................................................... 7 
`“Error Correction Chip” ....................................................................... 7 
`A. 
`VI.  PROPOSED GROUNDS OF UNPATENTABILITY ................................... 8 
`A. 
`Summary of Grounds of Rejection ...................................................... 8 
`B. 
`Prior Art Offered for the Present Unpatentability Challenges ............ 9 
`VII.  THE PRIOR ART RENDERS OBVIOUS CLAIMS 1–8 OF THE ’414
`PATENT ......................................................................................................... 9 
`Claims 1–8 Are Rendered Obvious by Simpson alone or in view of
`the Intel Specification ........................................................................ 10 
`Summary of Simpson ......................................................................... 10 
`Eligibility of Simpson As Prior Art ................................................... 12 
`Summary of the Intel Specification ................................................... 12 
`Eligibility of the Intel Specification as Prior Art ............................... 13 
`The Proposed Combination of Simpson and the Intel Specification . 13 
`Claim 1 ............................................................................................... 16 
`Claim 2 ............................................................................................... 28 
`Claim 3 ............................................................................................... 31 
`
`1. 
`2. 
`3. 
`4. 
`5. 
`6. 
`7. 
`8. 
`
`V. 
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`A. 
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`9. 
`10. 
`11. 
`12. 
`13. 
`B. 
`
`Claim 4 ............................................................................................... 35 
`Claim 5 ............................................................................................... 38 
`Claim 6 ............................................................................................... 39 
`Claim 7 ............................................................................................... 39 
`Claim 8 ............................................................................................... 41 
`Claims 1-8 are Rendered Obvious by The Intel Specification Alone.
` ............................................................................................................ 43 
`Reasonable Expectation of Success ................................................... 44 
`Claim 1 ............................................................................................... 44 
`Claim 2 ............................................................................................... 53 
`Claim 3 ............................................................................................... 54 
`Claim 4 ............................................................................................... 58 
`Claim 5 ............................................................................................... 60 
`Claim 6 ............................................................................................... 61 
`Claim 7 ............................................................................................... 61 
`Claim 8 ............................................................................................... 62 
`Claims 1–8 Are Rendered Obvious by the Intel Specification alone or
`in view of Simpson. ........................................................................... 64 
`VIII.  CONCLUSION ............................................................................................ 65 
`
`1. 
`2. 
`3. 
`4. 
`5. 
`6. 
`7. 
`8. 
`9. 
`C. 
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`EXHIBIT LIST
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`Description
`
`Exhibit
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`
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`1001 U.S. Patent 6,850,414 to Benisek (’414 patent)
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`1002 UK Patent Application GB 2 289 573 A to Simpson
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`1003
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`PC SDRAM Unbuffered DIMM Specification, Version 1.0
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`1004 U.S. Patent Application Publication No. 2002/0196612 to Gall
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`1005
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`PC133 SDRAM Registered DIMM Design Specification
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`1006 Declaration of Professor Vivek Subramanian (“Subramanian”)
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`1007
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`ʼ414 Patent File History
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`1008
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`File History for U.S. Patent No. 6,332,183
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`1009 District Court Complaint
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`1010
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`Professor Vivek Subramanian’s Curriculum Vitae
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`iii
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`Polaris Innovations Ltd. Exhibit 2008
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`I.
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`INTRODUCTION AND RELIEF REQUESTED
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`Kingston Technology Company, Inc. (“Petitioner”) hereby petitions for
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`institution of inter partes review of all claims of U.S. Patent No. 6,850,414 (the
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`“’414 Patent”) (Ex. 1001). The ’414 Patent issued on February 1, 2005. Polaris
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`Innovations Limited (“Patent Owner”) is the assignee of record with the United
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`States Patent & Trademark Office (“USPTO”). Petitioner respectfully requests
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`cancellation of claims 1-8 of the ’414 Patent on the grounds of unpatentability
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`herein. The prior art and other evidence offered with this Petition—which were not
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`before the USPTO during original prosecution—establish that all elements in the
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`challenged claims of the ’414 Patent were well known prior to the earliest alleged
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`priority date, and that the claimed methods and systems recited in the ’414 Patent
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`are invalid as obvious under 35 U.S.C. § 103.
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`II. GROUNDS FOR STANDING
`Petitioner certifies that the ’414 Patent is available for review under 35 U.S.C.
`
`§ 311(c) and that Petitioner is not estopped from requesting an inter partes review
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`challenging claims 1-8 on the grounds identified herein.
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`III. MANDATORY NOTICES
`Real Party in Interest: Petitioner Kingston Technology Company, Inc.
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`Related Matters: The Patent Owner alleges infringement of the ’414 Patent
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`in the parallel litigation styled Polaris Innovations Ltd. v. Kingston Tech. Co., Inc.,
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`Case No. 8:16-cv-300 (C.D. Cal.), filed February 19, 2016 (“Co-Pending District
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`Court Action”). Petitioner was served with the complaint in that litigation on
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`February 25, 2016. Ex. 1009.
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`Designation of Counsel: Petitioner designates the following Lead and Back-
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`up Counsel. Concurrently filed with this Petition is a Power of Attorney per 37
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`C.F.R. § 42.10(b). Service via hand-delivery may be made at the postal mailing
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`address below. Petitioner consents to electronic service by e-mail.
`
`Lead Counsel
`David Hoffman (Reg. No. 54,174)
`3200 RBC Plaza
`60 South Sixth Street
`Minneapolis, MN 55402
`Tel: (512) 472-8154
`Fax: (202) 783-2331
`IPR37307-0007IP1@fr.com
`
`Back-Up Counsel
`Martha Hopkins (Reg. No. 46,277)
`Law Offices of S.J. Christine Yang
`17220 Newhope St., Suites 101-102
`Fountain Valley, CA 92708
`Tel: (714) 641-4022
`Fax: (714) 641-2082
`IPR@sjclawpc.com
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`
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`Payment of Fees (37 C.F.R. § 42.103): Petitioner authorizes the Patent and
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`Trademark Office to charge Deposit Account No. 06-1050 for the petition fee and
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`for any other required fees.
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`IV. BACKGROUND
`A. Description of the ’414 Patent
`The ’414 Patent relates to a printed circuit board that has at least nine
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`identically designed, integrated semiconductor memories with housings that are
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`arranged to reduce the height of the printed circuit board. Ex. 1001, 2:45-3:10; Ex.
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`1006 at ¶20. The specification discloses that one of the at least nine semiconductor
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`memories be allocated for error correction and arranged vertically on the printed
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`circuit board, such that the error correction chip determines the maximum height of
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`the printed circuit board, while the other semiconductor memories are arranged
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`horizontally. Ex. 1001, 3:11-27, 6:1-4; Ex. 1006 at ¶20.
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`The purported invention here “is achieved by virtue of the fact that, in the case
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`of the printed circuit board of the generic type, the housings of the identically
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`designed semiconductor memories, other than the error correction chip, are arranged
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`on the printed circuit board in a manner such that they are oriented with their longer
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`dimension parallel to the contact strip.” Ex. 1001, 3:4-10. Accordingly, this allows
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`“a certain, albeit small, narrowing of the printed circuit board.” Ex. 1001, 3:44-46.
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`However, as seen in Figs. 1A (front side) and 1B (rear side) of the ’414 Patent,
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`the prior art discloses a printed circuit board with all semiconductor memories 4
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`arranged vertically, including the error correction chip 5, such that the sole purported
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`improvement claimed in the ’414 Patent is a simple 90-degree rotation of the
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`memory chip orientation found in the prior art. See Ex. 1001, Figs. 1A and 1B; Ex.
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`1006 at ¶22. In contrast, Figs. 2 and 3 illustrate the purportedly inventive printed
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`circuit board, disclosed by the ’414 Patent, with an error correction chip 5 arranged
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`vertically and remaining semiconductor memories 4 arranged horizontally, as
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`opposed to vertically as in the prior art. Ex. 1001, Figs. 2 and 3; Ex. 1006 at ¶22.
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`FIG. 2 shows the front side of an
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`inventive printed circuit board.
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`FIG. 1A shows the front side of a
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`conventional printed circuit board.
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`FIG. 1B shows the rear side of the
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`FIG. 3 shows the rear side of the printed
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`conventional printed circuit board.
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`circuit board shown in FIG. 2.
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`The specification discloses that the prior art design of Figs. 1A and 1B
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`predetermines the size of the printed circuit board because two resistors “must be
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`arranged between one semiconductor memory 4 and the contact strip 2, because the
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`upper limit for the length of the leads of the resistors from the contact strip 2 permits
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`no other arrangement.” Ex. 1001, 5:59-6:4.
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`On the other hand, the specification explains that by arranging the
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`semiconductor modules horizontally, there is “no need for any resistors” between
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`the housing and the contact strip, and thus “the actual printed circuit board height is
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`determined only by the error correction chip 4b that is brought up to the contact strip
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`2.” Ex. 1001, 6:19-39. Accordingly, this small “reduction of the printed circuit
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`board height enables incorporation into even flatter elements of e.g. network
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`computers.” Ex. 1001, 6:47-49; Ex. 1006 at ¶24.
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`Prosecution History
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`B.
`On July 2, 2002, the ’414 Patent was filed as Application No. 10/187,763 (“the
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`’763 Application”) entitled “Electronic Printed Circuit Board Having a Plurality of
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`Identically Designed, Housing-Encapsulated Semiconductor Memories.” Ex. 1007.
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`A foreign German application, to which the ’414 patent claims priority, was filed on
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`July 2, 2001. Ex. 1001.
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`As with the issued patent, the ’763 Application contained eight claims. Ex.
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`1007. On September 15, 2004, a Notice of Allowance and Fees issued. Id. The
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`Notice of Allowance discussed only seven references. Id. And, at least two of those
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`references—Kasatani and Michael—disclosed nearly every limitation according to
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`the examiner—but missing were an error correction chip and horizontal positioning,
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`respectively. Id. Both of which are obvious design choices that the examiner failed
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`to recognize. The eight claims remained unchanged from the original application.
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`Id. The examiner did not address obviousness under 35 U.S.C. § 103. Id.
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`Person of Ordinary Skill in the Art
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`C.
`A person of ordinary skill in the art as of the time of the ’414 Patent would
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`have a Bachelor’s degree in Electrical Engineering and at least 2 years’ experience
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`working in the field of semiconductor memory design. Ex. 1006, Subramanian Decl.
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`at ¶17.
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`State of the Art
`
`D.
`By the early 2000’s, design choices for the orientation of memory chips on
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`printed circuit boards were well known to those of ordinary skill in the art, at least
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`because of industry standards. Ex. 1006, Subramanian Decl. at ¶19. For example,
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`by 1995, Simpson recognized that “several variations of the basic design [of printed
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`circuit boards] had been implemented by others to provide different organisations
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`[sic] of memory with a standardised [sic] connection specification so that modules
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`of the same type from one vendor can be freely interchanged with those from
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`another.” Ex. 1002, Simpson 2:10-15.
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`By 1999, JEDEC1, as well as companies like Intel, had detailed the exact
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`dimensional design constraints from which a printed circuit board could, and should,
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`be designed, to allow interchangeability across devices and companies. See, e.g.,
`
`Ex. 1003, Intel Specification. Those of ordinary skill in the art thus recognized that,
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`
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`1 JEDEC stands for the “Joint Electron Device Engineering Council.” JEDEC is a
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`recognized standard setting body within the industry. Specifically, the JEDEC
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`memory standards are the specifications for semiconductor memory circuits and
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`similar storage devices promulgated by JEDEC.
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`within specified design dimensions and tolerances, memory modules and/or error
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`correction devices could be interchanged in only a limited number of ways within
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`the constraints set forth by the industry standards. Ex. 1006, Subramanian Decl. at
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`¶19.
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`Thus there is nothing novel or nonobvious about the simple re-arrangement
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`of memory chips on a memory module as disclosed and claimed in the ’414 Patent.
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`Id., generally.
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`V. CLAIM CONSTRUCTION
`In the PTO, a claim in an unexpired patent receives its broadest reasonable
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`interpretation (“BRI”) in light of the specification—i.e., a claim term gets its plain
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`meaning unless it is inconsistent with the specification. See 37 C.F.R. § 42.100(b);
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`Cuozzo Speed Techs., LLC v. Lee, 136 S. Ct. 2131, 2142 (2016). The BRI standard
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`is different from the claim construction standard applied in litigation. Id. Kingston
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`submits, for purposes of this IPR only, that the broadest reasonable interpretation
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`should govern the meaning of the claim terms and provides the following specific
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`construction.
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`“Error Correction Chip”
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`A.
`The specification of the ’414 Patent does not specifically define the term
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`“error correction,” as recited in the claims of the ’414 Patent. However, the
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`specification does explain that the error correction chip “checks the correctness of
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`the data before the data are passed on.” Ex. 1001 at 7:2-5. It further describes that
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`“the reason for this arrangement is that one of the semiconductor memories is used
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`as an error correction chip in order to perform error checking on data that will be
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`stored in the rest of the semiconductor memories or that will be read from the
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`memories.” Ex. 1001 at 1:51-54. There is no further description in the ’414 Patent
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`as to how the error correction chip would correct errors beyond error checking. The
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`remainder of the description of the error correction chip is directed to its location
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`and physical orientation. The use of the term within the claim itself provides no
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`additional guidance.
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`Accordingly, based on the specification, one or ordinary skill in the art would
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`understand the “error correction chip” to mean “a chip that is able to perform at least
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`error checking on data stored in other semiconductor memories.” See Subramanian
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`Decl., Ex. 1006 at ¶¶25-26.
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`VI. PROPOSED GROUNDS OF UNPATENTABILITY
`A.
`Summary of Grounds of Rejection
`The following chart demonstrates the grounds of rejection and the prior art
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`applied against the challenged claims. With the present grounds of obviousness and
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`the evidence submitted herein, Petitioner has established a reasonable likelihood that
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`it will prevail in establishing unpatentability of claims 1–8 and requests institution
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`of inter partes review and cancellation of these claims.
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`Ground 1: § 103 in view of Simpson
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`Renders claims 1-8 obvious
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`under §103(a)
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`Ground 2: § 103 in view of Simpson
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`Renders claims 1-8 obvious
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`combined with Intel Specification
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`under §103(a)
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`Ground 3: § 103 in view of Intel
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`Renders claims 1-8 obvious
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`Specification
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`under §103(a)
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`
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`Prior Art Offered for the Present Unpatentability Challenges
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`B.
`The present petition states invalidity grounds under 35 U.S.C. § 103 using the
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`following patents and printed publication prior art:
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` UK Patent Application GB 2 289 573 A to Simpson (“Simpson,” Ex.
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`1002), published on November 22, 1995, filed on May 19, 1995; this
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`reference is prior art under pre-AIA 35 U.S.C. § 102(a).
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` Intel: PC SDRAM Unbuffered DIMM Specification Revision 1.0 (“Intel
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`Specification,” Ex. 1003), Copyright Dated 1997, published in February
`
`of 1998; this reference is prior art under pre-AIA 35 U.S.C. § 102(a).
`
`VII. THE PRIOR ART RENDERS OBVIOUS CLAIMS 1–8 OF THE ’414
`PATENT
`
`The discussion below identifies each challenged claim and where the prior art
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`teaches or suggests each portion of the claim, as well as where each portion of the
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`claim is further analyzed in the Subramanian Decl., Ex. 1006, and why a person of
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`ordinary skill would be motivated to modify the base reference as outlined in the
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`relevant obviousness combinations.
`
`A. Claims 1–8 Are Rendered Obvious by Simpson alone or in view of
`the Intel Specification
`1.
`Simpson teaches a memory module that “allows the user to customize the
`
`Summary of Simpson
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`module at the point of use rather than having to use the module configured during
`
`its manufacture.” Ex. 1002, Simpson, 7:8-10. Figs. 1 and 3 below illustrate a first
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`face and a second face, respectively, of the preferred embodiment of the invention
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`and design of a printed circuit board. As is depicted, both Figs. 1 and 3 include nine
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`identical memory chips, which eight in parallel and one in a vertical arrangement.
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`In Simpson, the printed circuit board 2 has a connection terminal 10 for
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`
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`insertion into a module receptacle. Ex. 1002, Simpson, 10:21-28. The printed circuit
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`board 2 also has memory devices 12A-12H on one face of the printed circuit board
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`2 that are electrically and mechanically connected. Ex. 1002, Simpson, 10:1-5, Fig.
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`2. Both faces include sockets 14A-J to add additional memory or logic devices as
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`needed. Ex. 1002, Simpson, 10:5-12, Fig. 3. Additional memory devices 18A-H
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`can be added using sockets 14C-J. Ex. 1002, Simpson, 10:21-30.
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`Further, parity memory devices 16 are situated on both faces of the printed
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`circuit board. Ex. 1002, Simpson, 10:32-11:13. Fig. 1 illustrates the parity memory
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`device 16A—parity memory checking being a form of error correction—arranged
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`perpendicular to the connection terminal 10 (i.e. contact strip). Ex. 1002, Simpson,
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`Fig. 1. And, also as illustrated in Fig. 1, the long sides of sockets 14C-H are arranged
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`parallel to the connection terminal 10 (i.e. contact strip). Id. Simpson appreciates
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`that any devices can be added or replaced by sockets as long as the module has a
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`sufficient amount of memory devices to function. Ex. 1002, Simpson, 8:5-11.
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`Eligibility of Simpson As Prior Art
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`2.
`Simpson is eligible to serve as prior art for the ’414 Patent under 35 U.S.C.
`
`§ 102(a) and §102(b). Simpson was published on November 22, 1995 in the United
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`Kingdom, at least five years before the priority date of the ’414 Patent. See Ex.
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`1002, Simpson. Moreover, Simpson was not cited by the USPTO or considered by
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`the Examiner during prosecution of the ’414 Patent. See Ex. 1007.
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`Summary of the Intel Specification
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`3.
`The Intel Specification describes “the electrical and mechanical requirements
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`for 168-pin, 3.3 volt, 64-bit and 72-bit wide, 4 clock, unbuffered Synchronous
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`DRAM Dual In-Line Memory Modules (SDRAM DIMMs).” Ex. 1003, Intel
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`Specification at 7. The document “focuses on six-layer double-sided assembly PCB
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`designs.” Id. The Intel Specification recognizes that it “largely follows the JEDEC
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`defined 168-pin unbuffered SDRAM DIMM as of JEDEC committee meeting of
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`December 1996.” Id.
`
`Though the Intel Specification is directed to a double-sided six-layer design,
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`the document specifically recognizes that the same “PCB designs will also work for
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`single sided population with or without stuffing the ECC [error correcting code]
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`Devices.” Id. at 9. Importantly, the Intel Specification details the exact mechanical,
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`physical design ranges for the printed circuit board thus giving the “specific
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`dimensions and tolerances for a 168-pin DIMM.” Id. at 11.
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`The Intel Specification thus provides a specific example of a physical
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`structure that a person of ordinary skill would have understood and likely adhered
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`to at the time of the priority date of the ’414 Patent. See Ex. 1006, Subramanian
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`Decl. at ¶¶33-36.
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`Eligibility of the Intel Specification as Prior Art
`
`4.
`The Intel Specification is eligible to serve as prior art for the ’414 Patent under
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`35 U.S.C. § 102(a) and §102(b). The Intel Specification has a copyright year of
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`1997. See Ex. 1003, Intel Specification at 2. A revision date of February 1998 is
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`listed on the face of the document. Id. at 1. The document was publicly distributed
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`through the Intel Developer’s Website at http://developer.intel.com. See id. at 7.
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`Additionally, the Intel Specification was cited and considered by an examiner during
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`the prosecution of an unrelated patent. See Ex. 1008, File History for U.S. Patent
`
`No. 6,332,183 (signed by the examiner as considered on March 30, 2000). The Intel
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`Specification was not cited by the USPTO or considered by the Examiner during the
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`prosecution of the ’414 Patent. See Ex. 1007.
`
`5.
`
`The Proposed Combination of Simpson and the Intel
`Specification
`
`Petitioner contends that Simpson, alone, renders claims 1-8 of the ’414 Patent
`
`obvious. To the extent the Board disagrees, however, the proposed combination of
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`Simpson and the Intel Specification teaches all of the limitations of claims 1-8,
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`rendering them obvious.
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`It would have been obvious to modify the printed circuit board and memory
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`module design of Simpson to incorporate the constraints disclosed in the Intel
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`Specification. In the resulting design, Simpson would be constrained and adapted
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`to comply with the design specifications—specifically the physical dimensions—
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`described in the Intel Specification. As described below, one of ordinary skill in the
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`art at the priority date of the ’414 Patent would have been motivated to modify
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`Simpson based on the design dimensions of the Intel Specification and would have
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`had a reasonable expectation of success when doing so. See Ex. 1006, Subramanian
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`Decl. ¶¶37-41. Petitioner provides further details about the proposed combination
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`of Simpson and the Intel Specification, as appropriate, in the sections that follow.
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`a)
`As Dr. Subramanian explains in his declaration, the mechanical design
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`Reasons to Combine
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`constraints of the market for printed circuit boards matured in the years leading up
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`to the priority date of the ’414 Patent. See Ex. 1006, Subramanian Decl. at ¶¶37-41.
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`Thus, those skilled in the art understood how to implement the design of a circuit
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`board within the physical constraints of the standards at the time. Id. As discussed
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`above, Simpson is an example of a printed circuit board design circa 1995. Ex. 1002,
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`Simpson. Further, the Intel Specification outlines the mechanical design and
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`tolerance constraints at the turn of the millennium. Ex. 1003, Intel Specification.
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`One of ordinary skill in the art would recognize that modifying Simpson to comply
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`with the physical constraints supplied by the Intel Specification would be a way to
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`modernize Simpson to work with current motherboards and contemporary
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`technology. Id. Thus, the motivation to combine the references is obvious on its
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`face because the Intel Specification describes the modern standards for printed
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`circuit board designs such as those described in Simpson. Id.
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`b) Reasonable Expectation of Success
`As Dr. Subramanian explains in his declaration, the standards for printed
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`circuit boards in the market had already matured and normalized as the 2000’s
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`approached, and as a result, one of ordinary skill in the art would have had a
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`reasonable expectation of being able to successfully modernize Simpson to comply
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`with the electrical and mechanical requirements laid out in the Intel Specification.
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`Id. Indeed, Simpson itself recognizes that “a wiring configuration can easily be
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`designed by a person skilled in the art.” Ex. 1002, Simpson, 10:27-30. Thus, those
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`skilled in the art would have recognized that the modifications to Simpson in light
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`of the Intel Specification would not have posed technical difficulties. Ex. 1006,
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`Subramanian Decl. at ¶38.
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`Simply applying standards to the design of Simpson was within the
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`knowledge of a person of ordinary skill by the priority date of the ’414 Patent. Thus,
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`one of ordinary skill in the art would have had a reasonable expectation of success
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`in modifying Simpson to reflect the design standards of the Intel Specification. Ex.
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`1006, Subramanian Decl. at ¶¶37-41.
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`6.
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`Claim 1
`a)
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`“An electronic printed circuit board configuration,
`comprising:”
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`Simpson alone discloses “an electronic printed circuit board configuration.”
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`Specifically, Simpson grants that “[t]raditionally the memory of a computer system
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`has been designed using individual memory devices mounted on a PCB (Printed
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`Circuit Board) arranged in such a way as to give the required storage size and
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`configuration.” Ex. 1002, Simpson, 1:10-13. Further, Simpson acknowledges that
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`“[k]nown memory modules consist of a PCB containing a plurality of memory
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`devices and associated decoupling components wired to a connector for coupling to
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`the computer system.” Id. at 2:17-20. Annotated Figure 1 of Simpson depicts an
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`electronic printed circuit board at element 2.
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`The invention of Simpson relates to a specifically designed memory module,
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`
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`which, according to the specification, includes a printed circuit board. Id. at 4:28-
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`5:5; Figs. 1-3. Thus, Simpson teaches “an electronic printed circuit board
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`configuration.” Ex. 1006, Subramanian Decl., at ¶¶42-43.
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`b)
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`“An electronic printed circuit board having a contact
`strip for insertion into another electronic unit; and”
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`Simpson discloses a “memory module 2 comprising a substrate 4 having a
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`first major face 6 and a second major face 8. Along one long edge of the substrate
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`4 is a connector terminal strip 10[.]” Ex. 1002, Simpson, 9:8-13; Figs. 1-3. The
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`connector terminal strip 10 plugs into a module receptacle to enable operation of the
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`memory module. Ex. 1002, Simpson, 9:8-16; 10:21-30; 12:10-14; Figs. 1-3.
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`Annotated Figure 1 of Simpson depicts a contact strip at element 10 to insert into an
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`electronic unit.
`
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`The connector terminal strip 10 of Simpson is simply another description for
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`
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`a “contact strip” as disclosed by the ’414 Patent. Ex. 1006, Subramanian Decl. at
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`¶¶44-45; compare Ex. 1001 Fig. 3, element 2 with Ex. 1002, element 10. Thus,
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`Simpson teaches “an electronic printed circuit board having a contact strip for
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`insertion into another electronic unit.” Id.
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`c)
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`“A memory module having at least nine identically
`designed integrated semiconductor memories;”
`As shown in Figure 1, on a single side, Simpson discloses a base module 2
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`that “consists of an array of [nine] memory devices 12A-12H[.]” Ex. 1002,
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`Simpson, 9:18-20; Fig. 1. Module 2 of Simpson also includes a ninth semiconductor
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`memory 16A on that same side. Ex. 1002, 10:14-25 (referring to each of the chips
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`12A-12H and 16A as memory devices). Those of ordinary skill in the art would
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`understand that the memory device 16A is identical to each of memory devices 12A-
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`12H. Ex. 1006, Subramanian Decl. at ¶48; see also Ex. 1002 at 22-28 (referring to
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`power and signals collectively for all of the memory devices) and 12:10-14
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`(describing common capacitors used to supply power to each of the memory
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`devices).
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`However, the claims of the ’414 Patent are not limited to having chips on a
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`single side of the PCB. Simpson makes clear that “memory devices 12 may be
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`mounted on both sides of the module 2.” Ex. 1002, Simpson, 13:7-12. In fact, the
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`illustrated embodiments of Simpson envision empty sockets 14C-14J populated with
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`memory devices 18A-18H plugged in for added memory. Ex. 1002, Simpson,
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`10: