US0074.14312B2
`
`(12) United States Patent
`Nguyen et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7.414,312 B2
`Aug. 19, 2008
`
`(54) MEMORY-MODULE BOARD LAYOUT FOR
`USE WITH MEMORY CHIPS OF DIFFERENT
`DATA WIDTHS
`(75) Inventors: Henry H. D. Nguyen, Fountain Valley,
`CA (US); Mark Burlington, Aliso
`Viejo, CA (US)
`(73) Assignee: Kingston Technology Corp., Fountain
`Valley, CA (US)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 569 days.
`(21) Appl. No.: 10/908,718
`(22) Filed:
`May 24, 2005
`
`(*) Notice:
`
`(65)
`
`Prior Publication Data
`|US 2006/0267,172 A1
`Nov. 30, 2006
`
`(51) Int. Cl.
`(2006.01)
`H0 IL 23/34
`(2006.01)
`H05R 7/0?)
`(2006.01)
`GIIC 5/06
`(52) U.S. Cl. ............... 257/724; 257/786; 257/E23.141:
`361/760; 361/784; 361/803; 365/63
`(58) Field of Classification Search ....................... None
`See application file for complete search history.
`References Cited
`
`(56)
`
`|U.S. PATENT DOCUMENTS
`
`4,884,237 A 11/1989 Mueller et al. ................ 365/63
`5,754,408 A *
`5/1998 Derouiche ......
`... 361/773
`6,038,132 A * 3/2000 Tokunaga et al. ........... 361/760
`6,542,393 B1
`4/2003 Chu et al. ..................... 365/51
`6,614,664 B2
`9/2003 Lee .............
`... 361/784
`6,751,113 B2
`6/2004 Bhakta et al. ................. 365/63
`
`1/2005 Benisek et al. .............. 361/760
`6,839,241 B2
`6,891,729 B2 * 5/2005 Ko et al. ........
`... 361/736
`7,224,595 B2 * 5/2007 Dreps et al. ................... 365/63
`7,337,522 B2 * 3/2008 Engle et al. ....
`... 29/564.1
`7,356,737 B2 * 4/2008 Cowell et al. ................. 71.4/42
`2002/0133665 A1
`9/2002 Mailloux et al. ..
`... 711/105
`2003/0067063 A1
`4/2003 Muff et al. ........
`... 257/678
`9/2004 Perego et al ......
`2004/0186956 A1
`... 711/115
`11/2004 Perego et al. .....
`2004/0221 106 A1
`... 711/115
`... 257/200
`2004/0256638 A1 12/2004 Perego et al. .....
`-
`2/2005 Pauley et al. ................... 711/1
`2005/0044302 A1
`FOREIGN PATENT DOCUMENTS
`
`JP
`07022727 A + 1/1995
`* cited by examiner
`Primary Examiner—Alonzo Chambliss
`(74) Attorney, Agent, or Firm—gPatent LLC; Stuart J.
`Auvinen
`
`(57)
`
`ABSTRACT
`
`A memory module substrate printed-circuit board (PCB) has
`multi-type footprints and an edge connector formating with a
`memory module socket on a motherboard. Two or more kinds
`of dynamic-random-access memory (DRAM) chips with dif
`ferent data I/O widths can be soldered to solder pads around
`the multi-type footprints. When x4 DRAM chips with 4 data
`I/O pins are soldered over the multi-type footprints, the
`memory module has a rank-select signal that drives chip
`select inputs to all DRAM chips. When x8 DRAM chips with
`8 data I/O pins are soldered over the multi-type footprints, the
`memory module has two rank-select signals. One rank-select
`drives chip-select inputs to front-side DRAM chips while the
`second rank-select drives chip-select inputs to back-side
`DRAM chips. Wiring traces on the PCB cross-over data
`nibbles between the solder pads and the connector to allow
`two x4 chips to drive a byte driven by only one x8 chip.
`
`20 Claims, 7 Drawing Sheets
`
`
`
`
`
`FOOTPRINT
`X4 OR x8
`
`52
`
`CONNECTOR
`
`MOTHER
`-BOARD
`
`CONNECTOR
`34
`
`MOTHER
`-BOARD
`
`32
`
`
`
`
`
`
`
`DD 37
`
`1
`
`Polaris Innovations Ltd. Exhibit 2002
`Kingston v. Polaris, IPR2017-00974
`
`

`

`U.S. Patent
`
`Aug. 19, 2008
`
`Sheet 1 of 7
`
`US 7,414,312 B2
`
`
`
`2
`
`Polaris Innovations Ltd. Exhibit 2002
`Kingston v. Polaris, IPR2017-00974
`
`

`

`3
`
`Polaris Innovations Ltd. Exhibit 2002
`Kingston v. Polaris, IPR2017-00974
`
`

`

`U.S. Patent
`
`Aug. 19, 2008
`
`Sheet 3 of 7
`
`US 7.414,312 B2
`
`FRONT SIDE 1
`
`CONNECTOR
`
`34
`
`MOTHER
`-BOARD
`
`75i
`
`
`
`BACK SIDE 2
`
`CONNECTOR
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`MOTHER
`-BOARD
`D4
`D5
`D6
`D7 RANK2
`D0 (AXX=1)
`D1
`D2
`D3
`
`4
`
`Polaris Innovations Ltd. Exhibit 2002
`Kingston v. Polaris, IPR2017-00974
`
`

`

`U.S. Patent
`
`Aug. 19, 2008
`
`Sheet 4 of 7
`
`US 7.414,312 B2
`
`
`
`
`
`BACK SIDE 2
`
`CONNECTOR
`
`MOTHER
`
`RANK 1
`(AXX=0)
`
`MOTHER
`
`D4
`D5
`D6
`D7
`
`32
`
`RANK 1
`(AXX=0)
`
`
`
`
`
`5
`
`Polaris Innovations Ltd. Exhibit 2002
`Kingston v. Polaris, IPR2017-00974
`
`

`

`U.S. Patent
`
`Aug. 19, 2008
`
`Sheet 5 of 7
`
`US 7.414,312 B2
`
`20
`
`FOOTPRINT
`X4 OR X8
`
`
`
`20
`mº-
`
`CONNECTOR
`
`MOTHER
`-BOARD
`
`DO
`D1
`D2
`
`D6
`D7
`
`D0 ==
`D1
`D2
`D3
`D4
`D5
`D6
`D7
`
`CONNECTOR
`
`
`
`
`
`32
`
`MOTHER
`-BOARD
`D4
`D5
`D6
`D7
`D0
`D1
`D2
`D3
`
`D6
`
`DO
`
`
`
`
`
`
`
`
`
`
`
`
`
`FIG. 5
`
`6
`
`Polaris Innovations Ltd. Exhibit 2002
`Kingston v. Polaris, IPR2017-00974
`
`

`

`U.S. Patent
`
`Aug. 19, 2008
`
`Sheet 6 of 7
`
`US 7.414,312 B2
`
`JUMPERS FORX8, 2 RANKS
`
`
`
`CONNECTOR
`34
`
`FRONT SIDE 1
`
`MOD_RSO
`
`MOD_RS1
`
`MOD CEN1
`
`MOD CEN2
`
`MOD STB1
`
`72
`
`74
`
`76
`
`77
`
`78
`
`79
`
`BACK SIDE 2
`
`7
`
`Polaris Innovations Ltd. Exhibit 2002
`Kingston v. Polaris, IPR2017-00974
`
`

`

`U.S. Patent
`
`Aug. 19, 2008
`
`Sheet 7 of 7
`
`US 7.414,312 B2
`
`JUMPERS FORX4, 1 RANK
`
`
`
`CONNECTOR
`34
`
`FRONT SIDE 1
`
`MOD_RSO
`
`MOD_RS1
`
`MOD CEN1
`
`MOD CEN2
`
`MOD_STB1
`
`MOD_STB2
`
`72
`
`74
`
`76
`
`77
`
`78
`
`79
`
`BACK SIDE 2
`
`8
`
`Polaris Innovations Ltd. Exhibit 2002
`Kingston v. Polaris, IPR2017-00974
`
`

`

`US 7,414,312 B2
`
`1
`MEMORY-MODULE BOARD LAYOUT FOR
`USE WITH MEMORY CHIPS OF DIFFERENT
`DATA WIDTHS
`
`FIELD OF THE INVENTION
`
`This invention relates to memory modules, and more par
`ticularly to board layouts of memory modules supporting
`memory chips of varying data widths.
`
`BACKGROUND OF THE INVENTION
`
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`
`Many types of electronics systems contain memory. A
`common, low-cost memory is dynamic-random-access
`memory (DRAM). Rather than sell individual DRAM chips,
`such chips are often pre-assembled into modules that can be
`inserted into sockets in a wide variety of systems. Such
`memory modules have gained enormous popularity in recent
`years. Most personal computers (PC’s) are shipped with
`sockets for memory modules so the PC user can later add
`additional modules, increasing the memory capacity of the
`PC. High-volume production and competition have driven
`module costs down dramatically, benefiting the PC buyer.
`Memory modules are made in many different sizes and
`capacities, such as older 30-pin and 72-pin single-inline
`memory modules (SIMMs) and newer 168-pin, 184-pin, and
`240-pin dual inline memory modules (DIMMs). The “pins”
`were originally pins extending from the module’s edge, but
`now most modules are leadless, having metal contact pads or
`leads. The modules are small in size, being about 3-5 inches
`long and about an inch to an inch and a half in height.
`The modules contain a small printed-circuit board sub
`strate, typically a multi-layer board with alternating lami
`nated layers of fiberglass insulation and foil or metal inter
`connect layers. Surface mounted components such as DRAM
`35
`chips and capacitors are soldered onto one or both surfaces of
`the substrate.
`FIGS. 1A-B show a double-sided memory module.
`Memory module 20 contains a substrate such as a multi-layer
`printed-circuit board (PCB) with surface-mounted DRAM
`40
`chips 22 mounted to the front surface or side of the substrate,
`as shown in FIG. 1A, while more DRAM chips 26 are
`mounted to the back side or surface of the substrate as shown
`in FIG. 1B. Metal contact pads 12 are positioned along the
`bottom edge of the module on both front and back surfaces.
`Metal contact pads 12 mate with pads on a module socket to
`electrically connect the module to a PC’s motherboard. Holes
`16 and notches are present on some kinds of modules to
`ensure that the module is correctly positioned in the socket.
`Capacitors 14 or other discrete components are surface
`mounted on the substrate to filter noise from DRAM chips 22,
`26.
`Flash memory 24 is an electrically-erasable programmable
`read-only memory (EEPROM) that can be programmed by
`the manufacturer. Configuration information about the
`memory is often written to flash memory 24. Such configu
`ration information may include the memory depth and width,
`locations of bad memory cells, speed of the memory, the type
`of memory, a manufacturing week code, critical timing
`parameters such as clock rate, CAS (column address select)
`latency, and any proprietary information. Flash memory 24 is
`known in one embodiment as a serial-presence detect (SPD)
`memory. During boot-up, the PC checks for “serial presence”
`on its memory bus. If a serial presence is detected, the PC
`reads the stored memory configuration through the serial line.
`Once programmed, flash memory 24 can be read by a PC on
`boot-up to determine the kind of memory installed in the PC.
`
`45
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`50
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`2
`A manufacturer may produce several different kinds of
`memory modules for sale. For example, one kind of memory
`module may contain ×4 DRAM chips that are 4 data bits wide,
`while a second kind of memory module may contain x8
`DRAM chips that are 8 bits wide. Some customers may order
`memory modules with the x8 DRAM chips, while other
`customers order memory modules with x4 DRAM chips.
`Predicting the exact product mix of ×4 and x8 chip modules
`can be difficult, and incorrectly predicting the product mix
`may lead to increased inventory cost or delayed or lost sales.
`What is desired is a memory module substrate board that
`can support either ×4 or x8 DRAM chips. A memory module
`board that can have DRAM chips of varying data widths
`mounted thereon is desirable. A single memory module PCB
`that can be used to manufacture several kinds of memory
`modules is desirable.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIGS. 1A-B show a double-sided memory module.
`FIG. 2A is a schematic of a memory module with one rank
`of x4 DRAM chips.
`FIG.2B is a schematic of a memory module with two ranks
`of x8 DRAM chips.
`FIG. 3 shows ×8 DRAM chips mounted to front and back
`sides of a multi-type memory module.
`FIG. 4 shows ×4 DRAM chips mounted to front and back
`sides of a multi-type memory module.
`FIG. 5 shows multi-type footprints that can have either ×4
`or ×8 DRAM chips mounted thereon for the multi-type
`memory module.
`FIG. 6 shows switch or jumpers set for a multi-type
`memory module populated with x8 DRAM chips.
`FIG. 7 shows switch or jumpers set for a multi-type
`memory module populated with x4 DRAM chips.
`
`DETAILED DESCRIPTION
`
`The present invention relates to an improvement in
`memory modules. The following description is presented to
`enable one of ordinary skill in the art to make and use the
`invention as provided in the context of a particular application
`and its requirements. Various modifications to the preferred
`embodiment will be apparent to those with skill in the art, and
`the general principles defined herein may be applied to other
`embodiments. Therefore, the present invention is not
`intended to be limited to the particular embodiments shown
`and described, but is to be accorded the widest scope consis
`tent with the principles and novel features herein disclosed.
`The inventors have discovered that a universal memory
`module printed-circuit board (PCB) layout may be used for
`different types of memory modules. In particular, a multi
`type layout for a PCB can be used for building memory
`modules that use either ×4 or ×8 DRAM chips. A single
`footprint on the PCB layout can have either a ×4 or a x8
`DRAM chip mounted to it. When x4 DRAM chips are
`mounted on the multi-type footprints, one type of memory
`module is constructed, while when x8 DRAM chips are
`mounted on the multi-type footprints, a second type of
`memory module is constructed. Thus two or more types of
`memory modules can be constructed from the same module
`PCB. Using a multi-type memory module board can allow for
`reduced inventory costs as the same PCB can be used to
`construct two or more types of memory modules.
`Various sizes (data depths and widths) of memory modules
`can be produced using different types of DRAM chips. The
`number of DRAM chips in a module depends on the capacity
`
`9
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`Polaris Innovations Ltd. Exhibit 2002
`Kingston v. Polaris, IPR2017-00974
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`

`US 7,414,312 B2
`
`10
`
`3
`and data-width of the DRAM chips and the size of the
`memory module. For example, a memory module con
`structed from 64 Mega-bitx4-bit-output (64Mx4) DRAM
`chips needs 16 of these 4-bit-wide DRAM chips to fill a 64-bit
`bus. The module has a capacity of 512 Megabytes (MB).
`When x8 DRAM chips are used, only eight x8 DRAM chips
`are needed for the 64-bit bus.
`The DRAM chips in a memory module can be arranged
`into more than one bank or rank. For example, using x4
`DRAM chips, a two-rank memory module with a total capac
`ity of 1024 MB can have two ranks of 16 DRAM chips per
`rank, using 64Mx4 chips.
`FIG. 2A is a schematic of a memory module with one rank
`of x4 DRAM chips. DRAM chips 52 on side 1, and DRAM
`chips 56 on side 2 form a single rank. To drive 64 external data
`15
`bits, a total of 16 DRAM chips 52, 56 are needed on the two
`sides of the module substrate. When 128Mx4 DRAM chips
`are used, the module contains 1024 MB.
`Most signals are shared by all DRAM chips on both sides.
`For example, control signals such as address strobes, write
`enable, clocks, etc. and address lines are connected to all
`DRAM chips on both sides on the memory module. Data lines
`are each shared by one chip on the module. Data lines D0-D3
`are driven by a first DRAM chip 52 on the first side, while data
`lines D4-D7 are driven by a first DRAM chip 56 on the second
`side. Likewise, data lines D8-D11 are driven by a second
`DRAM chip 52 on the first side, while data lines D12-D15 are
`driven by a second DRAM chip 56 on the second side.
`Since there is only one rank on the memory module, only
`one rank selectis needed for the memory module. Rank select
`RS1 is connected to chip-select inputs for all DRAM chips
`52, 56 on both sides of the memory module. When the chip
`select (RS1) is not activated, the control signals are ignored
`by the DRAM chips. The data lines are not driven by the
`non-selected rank of DRAM chips to prevent data conflicts.
`Switch 30 is set to connect the first rank-select input to the
`memory module, RS1, to the chip-select inputs to DRAM
`chips 56 on the second side. The second rank-select input to
`the module, RS2, is disconnected by switch 30. Switch 30
`could be a switch or could be a jumper that is set during
`manufacture.
`FIG.2B is a schematic of a memory module with two ranks
`of x8 DRAM chips. DRAM chips 22 form a first rank on side
`1, while DRAM chips 26 form a second rank on side 2. A total
`of 8 DRAM chips 22 are in the first rank, while another 8
`45
`DRAM chips 26 form the second rank. When 64Mx8 DRAM
`chips are used, each rank contains 512 MB.
`Most signals are shared by all DRAM chips in both ranks.
`For example, control signals such as address strobes, write
`enable, clocks, etc. and address lines are connected to all
`DRAM chips in both ranks on the memory module. Data lines
`are each shared by one chip in each of the ranks. Data lines
`D0-D7 are shared by a first DRAM chip 22 in the first rank
`and by a first DRAM chip 26 in the second rank. Likewise,
`data lines D8-D15 are shared by a second one of DRAM chips
`22, 26.
`The ranks are selected by chip-selector rank-select signals.
`Only one rank select is activated at a time for the memory
`module. Rankselect RS1 activates DRAM chips 22 in the first
`rank, while rank select RS2 selects DRAM chips 26 in the
`second rank. When the rank’s chip select is not activated, the
`control signals are ignored by DRAM chips in the rank. The
`data lines are not driven by the non-selected rank of DRAM
`chips to prevent data conflicts.
`The first rank-select input to the memory module, RS1, is
`connected to the chip-select inputs to DRAM chips 22 in the
`first rank. Switch 30 is set to connect the second rank-select
`
`55
`
`4
`input to the memory module, RS2, to the chip-select inputs to
`DRAM chips 26 in the second rank. Switch 30 could be a
`switch or could be a jumper that is set during manufacture.
`While the memory module has 16 DRAM chips in both
`FIGS. 2A, 2B, the module uses ×4 chips in a single rank in
`FIG. 2A, but uses ×8 chips organized into two ranks in FIG.
`2B. Using switch 30 to connect or disconnect the second
`rank-select input RS2, both configurations may be supported.
`When the PCB containing the DRAM chips has a layout with
`multi-type footprints, modules with both the configurations
`of FIG. 2A and FIG. 2B can be constructed from the same
`PCB.
`FIG. 3 shows ×8 DRAM chips mounted to front and back
`sides of a multi-type memory module. Memory module 20 is
`formed from a PCB substrate that has multi-type footprints on
`the front side that DRAM chips 22 are mounted to, and other
`multi-type footprints on the back side that DRAM chips 26
`are mounted to.
`DRAM chips 22, 26 are ×8 chips and have 8 data I/O pins
`D0-D7. During assembly, solder paste is applied over the
`surface of the PCB, and pins, leads, solder balls, or other
`solder-connectors of DRAM chips 22, 26 are aligned to sol
`der pads 36, 36 on the PCB. Heat is applied to reflow the
`solder paste, forming a solder connection from the pins of
`DRAM chips 22, 26 to solder pads 36, 36". Other solder pads
`36, 36' (not shown) are present for other signals and for power
`and ground to DRAM chips 22, 26.
`Wiring traces on the PCB connect solder pads 36, 36' to
`pads on connector 34. Connector 34 has pads that align to and
`electrically connect to pads in a socket on motherboard 32.
`These traces may have various shapes and may bend around
`and cross over other traces using vias to other layers. How
`ever, the location of signals on connector 34 is typically
`pre-defined by a memory-module standard, and traces must
`be routed from solder pads 36, 36' to these pre-defined pad
`locations in connector 34. For ease of illustration, these traces
`are shown as straight lines in the Figures, but are usually
`much more complex.
`Since DRAM chips 22, 26 are ×8 DRAMs, each has 8 data
`I/O pins D0-D7 which are connected to one of the 8 bytes of
`the 64-bit data bus in connector 34. Just the first of DRAM
`chips 22, 26 to the first data byte are shown.
`For DRAM chip 22 on the front side, the data I/O D0-D7
`from solder pads 36 can connect to data lines D0-D7 on
`connector 34 and to motherboard 32. Front-side DRAM chips
`22 are in rank 1. Back-side DRAM chips 26 are in rank 2.
`Both ranks use the same data and address lines on connector
`34, but an extra address bit AXX is used by the memory
`controlleron motherboard 32 to select the first or second rank.
`This address bit AXX is not applied to DRAM chips 22, 26.
`For DRAM chip 26 on the back side, the data I/O D0-D7
`from solder pads 36' also can connect to data lines D0-D7 on
`connector 34 and to motherboard 32. However the upper and
`lower nibbles are crossed-over. D0-D3 from DRAM chip 26
`and solder pads 36' connect to D4-D7 of connector 34. Like
`wise, D4-D7 from DRAM chip 26 and solder pads 36 con
`nect to D0-D3 of connector 34. This crossing over of the
`nibbles supports use of ×4 chips (FIG. 4). Similar nibble
`cross-overs occur for other DRAM chips 26 on the back side,
`while front-side DRAM chips 22 do not have their data
`nibbles crossed over.
`FIG. 4 shows ×4 DRAM chips mounted to front and back
`sides of a multi-type memory module. DRAM chips 52, 56
`are ×4 chips and have 4 data I/O pins D0-D3. DRAM chips
`52, 56 are mounted to the same multi-type footprints on the
`layout of the PCB substrate of memory module 20 that the x8
`DRAM chips were mounted to in FIG. 3.
`
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`Polaris Innovations Ltd. Exhibit 2002
`Kingston v. Polaris, IPR2017-00974
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`US 7,414,312 B2
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`5
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`5
`DRAM chips 52, 56 have the same dimensions and number
`of pins as the x8 DRAM chips. Thus ×4 DRAM chips can be
`mounted to the same multi-type footprints as the x8 DRAMs.
`The four additional data I/O D4-D7 on ×8 DRAMs corre
`spond to no-connect (N/C) pins in ×4 DRAMS. The no
`connect pins have a physical pin or package lead, but the lead
`does not connect to internal circuitry on the DRAM die inside
`the package. The N/C pins are thus electrical opens but are
`still soldered to solder pads 36, 36'.
`Since DRAM chips 52, 56 are ×4 DRAMs, each has 4 data
`I/O pins D0-D3, which are connected to one of the 16 half
`bytes (nibbles) of the 64-bit data bus in connector 34. Just the
`first of DRAM chips 52,56 to the first data byte are shown.All
`16 DRAM chips 52, 56 are in the same (first) rank.
`For DRAM chip 52 on the front side, the data I/O pins
`D0-D3 soldered to solder pads 36 connect to data lines D0-D3
`on connector 34 and to motherboard 32. The four N/C pins
`from DRAM chip 52 are soldered to solder pads 36 that
`connect to data lines D4-D7 on connector 34.
`For DRAM chip 56 on the back side, the data I/O pins
`D0-D3 are soldered to solder pads 36' that connect to data
`lines D4-D7 on connector 34 and to motherboard 32. The
`upper and lower nibbles are crossed-over. D0-D3 from
`DRAM chip 56 and solder pads 36 connect to D4-D7 of
`connector 34. Likewise, the four no-connect pins from
`25
`DRAM chip 56 and solder pads 36' D4-D7 connect to D0-D3
`of connector 34.
`This crossing over of the nibbles supports use of ×4 chips.
`Front-side DRAM chip 52 drives the lower nibble (D0-D3),
`while back-side DRAM chip 56 drives the upper nibble (D4
`30
`D7). Other pairs of front and back-side DRAM chips also
`drive upper and lower nibbles of other data bytes in the 64-bit
`data output on connector 34.
`The four N/C pins from DRAM chip 52 are soldered to
`solder pads 36 that connect to data lines D4-D7 on connector
`34. The four N/C pins from back-side DRAM chip 56 are
`soldered to solderpads 36' that connect to data lines D0-D3 on
`connector 34. Thus connector pads D0-D3 are connected by
`wiring traces on memory module 20 to solderpads 36 for pins
`D0-D3 offront-side DRAM chip 52, and to solderpads 36 for
`the 4 N/C pins of back-side DRAM chip 56. Since the N/C
`pins on DRAM chip 56 are opens, only one DRAM chip 52
`drives these four pins, although both DRAM chips 52, 56 are
`soldered to these four data lines.
`Likewise, connector pads D4-D7 are connected by wiring
`traces on memory module 20 to solder pads 36' for pins
`D0-D3 of back-side DRAM chip 56, and to solder pads 36 for
`the 4 N/C pins of front-side DRAM chip 52. Since the N/C
`pins on DRAM chip 52 are opens, only one DRAM chip 56
`drives these four pins, although both DRAM chips 52, 56 are
`soldered to these four data lines.
`While data-line pads D0-D7 on connector 34 are shown in
`FIGS. 3-5 on both front and back sides to show connection by
`wiring traces to solder pads 36, 36', each data line has only
`one connectorpad in connector 34, which is on either the front
`or back side, not both sides as shown. The order and exact
`location within connector 34 of the data lines depends on the
`memory module specification and is not as shown in the
`simplified drawings. Other signals such as module rank-se
`lects and strobes also appear on only one of the sides of
`connector 34, unless two connector pads are used.
`FIG. 5 shows multi-type footprints that can have either ×4
`or ×8 DRAM chips mounted thereon for the multi-type
`memory module. The front side of the PCB for memory
`module 20 has eight multi-type footprints 62, while the back
`side of the PCB has eight more multi-type footprints 64.
`Multi-type footprints 62 are surrounded by solder pads 36 in
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`an arrangement corresponding to lead locations on a DRAM
`chip. The DRAM chip soldered to solderpads 36 can be either
`×8 DRAM chip 22 or x4 DRAM chip 52.
`On the back side, multi-type footprints 64 are surrounded
`by solder pads 36' in an arrangement or layout corresponding
`to lead locations on a DRAM chip. The DRAM chip soldered
`to solder pads 36' can be either ×8 DRAM chip 26 or ×4
`DRAM chip 56.
`The four data I/O pins from multi-type footprint 62 are
`connected by wiring traces to data lines D0-D3 of connector
`34. The four N/C pins are connected by traces to data lines
`D4-D7 of connector 34. For back-side multi-type footprint
`64, the four data I/O pins D0-D3 are crossed-over and con
`nected by wiring traces to data lines D4-D7 of connector 34.
`The four N/C pins are crossed-over and connected by traces to
`data lines D0-D3 of connector 34. Other multi-type footprints
`62, 64 connect to other bytes in data lines D0-D63 in a similar
`fashion.
`FIG. 6 shows switch or jumpers set for a multi-type
`memory module populated with x8 DRAM chips. Connector
`34 also has connector pads for control signals, such as module
`rank-select 0 (MOD_RS0) and module rank-select 1
`(MOD_RS1), which select the first or second ranks when the
`memory module contains two ranks.
`When memory module 20 is populated with x8 DRAM
`chips 22, 26, RS0 connector pad 72 is routed by wiring traces
`on memory module 20 to the chip-select (CS) inputs offront
`side DRAM chips 22. RS1 connector pad 74 is routed through
`switch 30 and wiring traces on memory module 20 to the
`chip-select (CS) inputs of back-side DRAM chips 26. Thus
`first-rank front-side DRAM chips 22 are activated when RS0
`is activated, while second-rank back-side DRAM chips 26 are
`activated when RS1 is activated.
`Other control signals in connector 34 include module
`clock-enable inputs MOD CEN1 and MOD CEN2. CEN1
`connector pad 76 is routed by wiring traces on memory mod
`ule 20 to the clock-enable (CKEN) inputs of front-side
`DRAM chips 22. CEN2 connector pad 77 is routed through
`switch 80 and wiring traces on memory module 20 to the
`clock-enable (CKEN) inputs of back-side DRAM chips 26.
`Thus first-rank front-side DRAM chips 22 have clocks
`enabled when CEN1 is activated, while second-rank back
`side DRAM chips 26 have their clocks enabled when CEN2 is
`activated. When clocks are not enabled, DRAM chips 22, 26
`are in a stand-by mode and draw reduced power. Clocks
`typically are enabled before chips can be selected for access
`by chip-select signals.
`Still other control signals in connector 34 include module
`strobe inputs MOD STB1 and MOD STB2. There are 8
`MOD STB1 inputs in connector 34 and 8 MOD STB2
`inputs in connector 34. First strobe connector pads 78 are
`separately routed by wiring traces on memory module 20 to
`the data strobe (DS) inputs of the 8 front-side DRAM chips 22
`and through switch 82 to the data strobe (DS) inputs of back
`side DRAM chips 26. Switches 82, 84 are each 8 bits wide.
`Data strobes are activated to enable data to be driven or read
`from the data lines.
`The 8 second strobe connector pads 79 are routed by wiring
`traces on memory module 20 and by 8-bit-wide switch 84 to
`the 8 data mask (DM) inputs of the 8 front-side DRAM chips
`22 and to the 8 data mask (DM) inputs of 8 back-side DRAM
`chips 26. Each second strobe connector pad 79 is routed to a
`pair of one front-side DRAM chip 22 and one back-side
`DRAM chip 26. Data mask is activated to mask portions of
`the data being read or written, such as masking one of the 8
`bytes of the 64-bit data on the data lines on connector 34.
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`11
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`Polaris Innovations Ltd. Exhibit 2002
`Kingston v. Polaris, IPR2017-00974
`
`

`

`US 7,414,312 B2
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`7
`The memory controller on the motherboard determines the
`functionality of memory module 20 during an initialization
`routine. ASPDEEPROM on memory module 20 is read by an
`initialization routine for the memory controller. The details of
`the module type in the SPD EEPROM indicate the functions
`of the module strobes. For example, the module type may
`indicate that two ranks of ×8 DRAM chips are used, so the
`two rank selects need to be generated. Also, the SPD configu
`ration information may indicate that all chips have both a data
`strobe and a data mask input. The initialization routine can
`enable the memory controller to generate these data strobe
`and data mask signals during memory accesses to this
`memory module.
`Switches 30, 80, 82, 84 can be switches such as dual-inline
`package (DIP) switches, or can be jumpers such as discrete
`wires or solder bridges that bridge over a gap between two
`solder pads that form the switch. The jumper can be made
`from metal and be zero-ohms or have a very low resistance.
`FIG. 7 shows switch or jumpers set for a multi-type
`memory module populated with x4 DRAM chips. When
`20
`memory module 20 is populated with x4 DRAM chips 52,56,
`RS0 connector pad 72 is routed by wiring traces on memory
`module 20 to the chip-select (CS) inputs offront-side DRAM
`chips 52. RSO connector pad 72 is also routed through switch
`30 and wiring traces on memory module 20 to the chip-select
`(CS) inputs of back-side DRAM chips 56. Thus chip-select
`inputs for all DRAM chips 52, 56 are driven by the first rank
`select input, RS0. RS1 connector pad 74 is not used and is
`disconnected by switch 30.
`Since there is only one rank, only one clock-enable input is
`used for memory module 20. CEN1 connector pad 76 is
`routed by wiring traces on memory module 20 to the clock
`enable (CKEN) inputs of front-side DRAM chips 52 and
`through switch 80 to the clock-enable (CKEN) inputs of
`back-side DRAM chips 56. Thus both front-side DRAM
`35
`chips 52 and back-side DRAM chips 56 have their clocks
`enabled when CEN1 is activated. When clocks are not
`enabled, DRAM chips 52, 56 are in a stand-by mode and draw
`reduced power. Clocks typically are enabled before chips can
`be selected for access by chip-select signals. CEN2 connector
`pad 77 is disconnected by switch 80 and is not used.
`Separate data strobes are used for DRAM chips on front
`and back sides. Since the front-side and backside DRAM
`chips 52, 56 are selected at the same time, the data strobes
`cannot be tied together as for the x8 case. The 8 MOD STB1
`lines are used as the data strobes for front-side DRAM chips
`52 while the 8 MOD STB2 lines are used as the data strobe
`for backside DRAM chips 56. Data strobe can be bi-direc
`tional, being generated by a memory controller on the moth
`erboard for writes and being generated by the DRAM chips
`for reads.
`The 8 first strobe connector pads 78 are routed by separate
`wiring traces on memory module 20 to the data strobe (DS)
`inputs of the 8 front-side DRAM chips 52. However, switch
`82 disconnects MOD-STB1 lines from the data strobe (DS)
`inputs of back-side DRAM chips 56. The MOD-STB1 lines
`are activated to enable data to be driven to or read from the
`data lines D0-D3, D8-D11, D16-D19, D24-D27, D32-D35,
`D40-D43, D48–D51, and D56-D59 that connect to front-side
`DRAM chips 22.
`The 8 second strobe connector pads 79 (MOD STB2) are
`separately routed through 8-bit switch 82 and by wiring traces
`on memory module 20 the data strobe (DS) inputs of back
`side DRAM chips 56. However, switch 82 disconnects MOD
`STB2 from the data strobe (DS) inputs of front-side DRAM
`65
`chips 52. Data strobe 2 is activated to enable data to be driven
`to or read from one or more of the data lines D4-D7, D12
`
`8
`D15, D20-D23, D28-D31, D36-D39, D44-D47, D52-D55,
`and D60-D63 that connect to back-side DRAM chips 56.
`The data maskinputs (DM) are not used. Instead, switch 84
`grounds the data mask (DM) inputs of front-side DRAM
`chips 52 and the data mask (DM) inputs of back-side DRAM
`chips 56. Grounding the data-mask inputs disables this fea
`ture so that all data bytes are written.
`
`ALTERNATE EMBODIMENTS
`
`Several other embodiments are contemplated by the inven
`tors. For example two, three, or more DRAM chips could be
`stacked together and mounted onto a single DRAM footprint
`on the PCB. The chip-select pins for chips in the stack could
`be bent out to be separately driven. Additional chip-selects or
`module-selects could be used, and the memory module could
`have 3 or more ranks. Rather than select ranks using chip
`select, other signals could be used such as an address or a data
`strobe signal. Some memories may have more than one chip
`selectinput, and some combination of these chip selects could
`be used to select the DRAM chips.
`The x4 and x8 DRAM chips could differ slightly in dimen
`sions and number of pins. For example, the x8 DRAMs could
`have pins that are missing from the x4. DRAMs, but since
`most of the pin layout is the same, the x4 and x8 DRAMs can
`mount to the same multi-type footprints. The missing pin
`locations of ×4 chips simply do not solder to underlying
`solder pads 36, 36.
`Rather than use x4 and x8 DRAM chips, other chip sizes
`could be substituted, such as x8 and x16 DRAM chips, or ×4
`and x16 DRAM chips, or other data widths.
`The number of DRAM chips, capacitors, buffers, and other
`comp