throbber
IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`Attorney Docket No.: 37307-0007IP1
`
`In re Patent of: Benisek et al.
`US Patent No.: 6,850,414
`Issue Date:
`February 1, 2005
`Appl. Serial No.: 10/187,763
`§ 371 (c)(1) Date: July 2, 2002
`Title:
`ELECTRONIC PRINTED CIRCUIT BOARD HAVING A
`PLURALITY OF IDENTICALLY DESIGNED, HOUSING-
`ENCAPSULATED SEMICONDUCTOR MEMORIES
`
`Attorney Docket No.: 37307-0007IP1
`
`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`DECLARATION OF VIVEK SUBRAMANIAN
`
`
`
`
`
`I, Vivek Subramanian, declare as follows:
`
`I.
`1.
`
`Introduction.
`I am making this declaration at the request of the Real Party in Interest
`
`(Kingston Technology Company, Inc.) in the matter of Inter Partes Review of U.S.
`
`Patent No. 6,850,414 (the “’414 patent”).
`
`2.
`
`I am being compensated for my work. My compensation does not depend on
`
`the outcome of this proceeding.
`
`3.
`
`I have been asked to consider whether certain references disclose or render
`
`obvious the claims of the ’414 Patent, either alone or in combination with each
`
`other.
`
`
`
`1
`
`KINGSTON 1006
`
`

`

`Attorney Docket No.: 37307-0007IP1
`
`4.
`
`I have been advised that a patent claim may be invalid as obvious if the
`
`differences between the subject matter patented and the prior art are such that the
`
`subject matter as a whole would have been obvious at the time of the invention to a
`
`person having ordinary skill in the art. I have also been advised that several factual
`
`inquiries underlie a determination of obviousness. These inquiries include the
`
`scope and content of the prior art, the level of ordinary skill in the field of the
`
`invention, the differences between the claimed invention and the prior art, and any
`
`objective evidence of non-obviousness.
`
`5.
`
`I have been advised that objective evidence of non-obviousness directly
`
`attributable to the claimed invention, known as “secondary considerations of non-
`
`obviousness,” may include commercial success, satisfaction of a long-felt but
`
`unsolved need, failure of others, copying, skepticism or disbelief before the
`
`invention, and unexpected results. I am not aware of any such objective evidence
`
`of non-obviousness that is directly attributable to the subject matter claimed in the
`
`’414 patent at this time.
`
`6.
`
`In addition, I have been advised that the law requires a “common sense”
`
`approach of examining whether the claimed invention is obvious to a person
`
`skilled in the art. For example, I have been advised that combining familiar
`
`elements according to known methods is likely to be obvious when it does no more
`
`than yield predictable results. I have further been advised that this is especially true
`
`
`
`2
`
`

`

`Attorney Docket No.: 37307-0007IP1
`
`in instances where there are a limited numbers of possible solutions to technical
`
`problems or challenges.
`
`7.
`
`I have been informed that all claims of the ’414 Patent are subject to this
`
`inter partes review.
`
`II. Materials Reviewed
`8.
`In forming the opinions that I express below, I considered my own
`
`knowledge of the art plus at least the following references:
`
`a. The ’414 Patent
`
`b. UK Patent Application GB 2 289 573 A (“Simpson”)
`
`c. U.S. Patent Application Publication No. 2002/0006032 A1
`
`(“Karabatsos”)
`
`d. U.S. Patent No. 5,973,951 (“Bechtolsheim”)
`
`e. U.S. Patent No. 6,038,132 (“Tokunaga”)
`
`f. PC SDRAM Unbuffered DIMM Specification, Revision 1.0
`
`(“Intel DIMM Specification”)
`
`g. The File History of U.S. Patent No. 6,850,414
`
`III. Qualifications
`9.
`I summarize my relevant knowledge and experience below. My Curriculum
`
`Vitae contains additional information and is attached as Exhibit 1010.
`
`
`
`3
`
`

`

`Attorney Docket No.: 37307-0007IP1
`
`10. I received a B.S. in electrical engineering from Louisiana State University in
`
`1994, an M.S. in electrical engineering from Stanford University in 1996, and a
`
`Ph.D. in electrical engineering from Stanford University in 1998.
`
`11. I co-founded Matrix Semiconductor, Inc. in 1998 to develop high density
`
`memory technology.
`
`12. I have been teaching in the Electrical Engineering and Computer Sciences
`
`Department at the University of California, Berkeley since 2000. I was an
`
`Assistant Professor from 2000 to 2005, an Associate Professor from 2005 to 2011,
`
`and a Professor from 2011 to the present.
`
`13. I have been an adjunct professor at the Sunchon National University in
`
`Sunchon, Korea since 2009, leading research in printed electronics.
`
`14. I have been an independent consultant in the semiconductor industry since
`
`2000, focusing on memory technology, flexible electronics, and RFID technology.
`
`15. I have published more than 200 technical papers in journals and at
`
`conferences.
`
`16. I am a named inventor on over 40 U.S. Patents, many of which are in the
`
`field of memory design.
`
`IV. Person of Ordinary Skill in the Art and State of The Art
`
`17. In my opinion, a person of ordinary skill in the art as of the time of the ’414
`
`Patent would have a Bachelor’s degree in Electrical Engineering and at least 2
`
`
`
`4
`
`

`

`Attorney Docket No.: 37307-0007IP1
`
`years’ experience working in the field of semiconductor memory design. I believe
`
`this to be a reasonable statement of the level of ordinary skill in the art for the
`
`patent and claims at issue. I also believe that I was one of ordinary skill in the art
`
`through my education and work experience during the time that I was in
`
`University.
`
`18. The opinions that I provide in this declaration are consistent with the
`
`knowledge and experience of one of ordinary skill in the art at the priority date of
`
`the ’414 Patent.
`
`19. At the time of the ’414 Patent’s priority date, those of ordinary skill in the
`
`art recognized that, within specified design dimensions and tolerances, memory
`
`modules and/or error correction devices could be interchanged and oriented in a
`
`finite number of ways within the physical size constraints set forth by the industry
`
`standards. See Ex. 1002, Simpson, 2:10-15 and Ex. 1003 (Karabatsos).
`
`V. Overview of the ’414 Patent
`
`20. The ’414 Patent is directed to a printed circuit board (“PCB”) that has at
`
`least nine memories chips that are arranged to appreciably reduce the height of the
`
`printed circuit board. Ex. 1001, 2:45-3:10. The specification discloses that one of
`
`the at least nine chips be an error correction chip and that one be arranged
`
`vertically on the printed circuit board, such that the error correction chip
`
`
`
`5
`
`

`

`Attorney Docket No.: 37307-0007IP1
`
`determines the maximum height of the printed circuit board, while the other
`
`semiconductor memories are arranged horizontally. Ex. 1001, 3:11-27, 6:1-4.
`
`21. The supposed invention “is achieved by virtue of the fact that, in the case of
`
`the printed circuit board of the generic type, the housings of the identically
`
`designed semiconductor memories, other than the error correction chip, are
`
`arranged on the printed circuit board in a manner such that they are oriented with
`
`their longer dimension parallel to the contact strip.” Ex. 1001, 3:4-10. According to
`
`the patent, this allows “a certain, albeit small, narrowing of the printed circuit
`
`board.” Ex. 1001, 3:44-46.
`
`22. Notably, though as seen in Fig. 1A (front side) and 1B (rear side), the prior
`
`art is admitted by the applicant for the patent to disclose a printed circuit board
`
`with all semiconductor memories 4 arranged vertically, including the error
`
`correction chip 5. Ex. 1001, Figs. 1A and 1B. The purportedly inventive printed
`
`circuit board, disclosed by the ’414 Patent, with an error correction chip 5 arranged
`
`vertically and remaining semiconductor memories 4 arranged horizontally. Ex.
`
`1001, Figs. 2 and 3.
`
`23. Furthermore, there is no indication in the ’414 patent that orienting the error
`
`correction chip 5, rather than a memory or other type of semiconductor chip,
`
`vertically is anything other than a design choice. In other words, I have not seen
`
`anything within the ’414 patent that would indicate that the decision to orient the
`
`
`
`6
`
`

`

`error correction chip 5 vertically is critical to the design or operation of the ’414
`
`Attorney Docket No.: 37307-0007IP1
`
`patent’s memory module.
`
`
`
`
`
`FIG. 1A shows the front side of a
`
`FIG. 2 shows the front side of an
`
`conventional printed circuit board.
`
`inventive printed circuit board.
`
`FIG. 1B shows the rear side of the
`
`conventional printed circuit board.
`
`FIG. 3 shows the rear side of the
`
`printed circuit board shown in FIG. 2.
`
`
`
`
`
`
`
`24. The specification of the patent asserts that the prior art design of Figs. 1A
`
`and 1B predetermines the size of the printed circuit board because two resistors
`
`“must be arranged between one semiconductor memory 4 and the contact strip 2,
`
`because the upper limit for the length of the leads of the resistors from the contact
`
`strip 2 permits no other arrangement.” Ex. 1001, 5:59-6:4.
`
`
`
`7
`
`

`

`Attorney Docket No.: 37307-0007IP1
`
`25. The specification also explains that by arranging the semiconductor modules
`
`horizontally, there is “no need for any resistors” between the housing and the
`
`contact strip, and thus “the actual printed circuit board height is determined only
`
`by the error correction chip 4b that is brought up to the contact strip 2.” Ex. 1001,
`
`6:19-39. Accordingly, this small “reduction of the printed circuit board height
`
`enables incorporation into even flatter elements of e.g. network computers.” Ex.
`
`1001, 6:47-49. As I describe further below, turning a DRAM chip on its side was
`
`well within the skill level of a person even not versed in the art—a person skilled
`
`in the art would certainly not find this change inventive.
`
`VI. Claim Construction
`
`26. The specification of the ’414 does not specifically define the term “error
`
`correction,” as recited in the claims of the ’414 patent. However, the specification
`
`of the patent does explain that the error correction chip “checks the correctness of
`
`the data before the data are passed on.” Ex. 1001 at 7:2-5. It further describes that
`
`“the reason for this arrangement is that one of the semiconductor memories is used
`
`as an error correction chip in order to perform error checking on data that will be
`
`stored in the rest of the semiconductor memories or that will be read from the
`
`memories.” Ex. 1001 at 1:51-54. There is no further description in the ’414 patent
`
`as to how the error correction chip would correct errors beyond error checking.
`
`The remainder of the description related to the error correction chip is directed to
`
`
`
`8
`
`

`

`Attorney Docket No.: 37307-0007IP1
`
`its location and physical orientation. The use of the term within the claim itself
`
`provides no additional guidance.
`
`27. One or ordinary skill in the art would understand that error detection is
`
`typically a part error of error correction. In view of the specification, one of
`
`ordinary skill in the art would further understand that the broadest reasonable
`
`construction of “error correction chip” based on the specification to mean “a chip
`
`that is able to perform at least error checking on data stored in other semiconductor
`
`memories.”
`
`VII. Simpson
`
`28. I have been advised, and my understanding is, that Simpson is eligible to
`
`serve as prior art for the ’414 Patent under 35 U.S.C. § 102(a). Simpson was
`
`published on November 22, 1995 in the United Kingdom, at least five years before
`
`the priority date of the ‘414 patent. See Ex. 1002, Simpson. Based on my review of
`
`the ’414 patent file history, Simpson was not cited by the USPTO or considered by
`
`the Examiner during prosecution of the ’414 Patent. See Ex. 1007.
`
`29. Simpson teaches a memory module that “allows the user to customize the
`
`module at the point of use rather than having to use the module configured during
`
`its manufacture.” Ex. 1002, Simpson, at 7:8-10. Figs. 1 and 3 below illustrate a
`
`first face and a second face, respectively, of the preferred embodiment of the
`
`invention and design of a printed circuit board.
`
`
`
`9
`
`

`

`Attorney Docket No.: 37307-0007IP1
`
`
`
`
`
`30.
`
`31.
`
`32. In Simpson, the printed circuit board 2 has a connection terminal 10 for
`
`insertion into a module receptacle. Ex. 1002, Simpson, at 10:21-28. The printed
`
`circuit board 2 also has memory devices 12A-12H on one face of the printed
`
`circuit board 2 that are electrically and mechanically connected. Ex. 1002,
`
`Simpson, at 10:1-5, Fig. 2. Both faces include sockets 14A-J to add additional
`
`memory or logic devices as needed. Ex. 1002, Simpson, at 10:5-12, Fig. 3.
`
`Additional memory devices 18A-H can be added using sockets 14C-J. Ex. 1002,
`
`Simpson, at 10:21-30.
`
`
`
`10
`
`

`

`Attorney Docket No.: 37307-0007IP1
`
`33. Further, parity memory devices 16 are situated on both faces of the printed
`
`circuit board. Ex. 1002, Simpson, at 10:32-11:13. Fig. 1 illustrates the parity
`
`memory device 16A arranged perpendicular to the connection terminal 10. Ex.
`
`1002, Simpson, at Fig. 1. And, also as illustrated in Fig. 1, sockets 14C-H are
`
`arranged parallel to the connection terminal 10. Id. Simpson appreciates that any
`
`devices can be added or replaced by sockets as long as the module has a sufficient
`
`amount of memory devices to function. Ex. 1002, Simpson, at 8:5-11.
`
`VIII. Karabatsos
`34. I have been advised, and my understanding is, that Karabatsos is eligible to
`
`serve as prior art for the ’414 patent under 35 U.S.C. § 102(e). Karabatsos has a
`
`was filed in the United States on January 11, 2001. See Ex. 1003, Karabatsos.
`
`Based on my review of the ’414 patent file history, Karabatsos was not cited by the
`
`USPTO or considered by the Examiner during prosecution. See Ex. 1007, the ’414
`
`Patent File History.
`
`35. Karabatsos describes “[a] low profile, registered DIMM [that] has a height
`
`of about 1.2 inches, and a width of about 5.25 inches.” Ex. 1003, Karabatsos at
`
`Abstract, FIG. 1C. Karabatsos describes that the market demand for higher
`
`capacity memory at the time resulted in manufacturers producing many memory
`
`modules (e.g., DIMMs) that had “profiles of 1.5 inches or greater.” Id. at ¶¶
`
`[0004]-[0020]. Karabatsos recognized that the “unavailability of DIMMs with
`
`
`
`11
`
`

`

`Attorney Docket No.: 37307-0007IP1
`
`lower profiles [had] had a serious, negative effect on many computer designs.” Id.
`
`at ¶ [0020]. Karabatsos further explains the negative effect of tall DIMMs on
`
`computer designs lead to server manufacturers designing enclosures around the
`
`height of the memory modules or taking “extraordinary steps” to “slant[] . . .
`
`DIMM sockets at 22½ degrees.” Id. at ¶¶ [0021], [0022].
`
`36.
`
`In order to address this problem, Karabatsos proposes in FIGS. 1A-1C
`
`several different configurations and orientations for mounting memory chips
`
`(SDRAMs) to reduce the profile height of memory modules. See Id. at FIGS. 1A-
`
`1C (reproduced below). Karabatsos’s designs incorporate a dense arrangement of
`
`SDRAMs and, as shown in FIG. 1C, a rearrangement of SDRAM orientation with
`
`a center SDRAM oriented perpendicular to the other SDRAMs. Id.
`
`37.
`
`
`
`
`
`12
`
`

`

`Attorney Docket No.: 37307-0007IP1
`
`
`
`
`
`38.
`
`39.
`
`40. Karabatsos demonstrates that there was a recognized need within the art at
`
`the time of the priority date of the ’414 patent to reduce the height of memory
`
`modules. Furthermore, Karabatsos also illustrates that it was indeed well-known in
`
`the art at the time to re-arrange the layout of memory chips on a memory module
`
`to achieve desired dimensions for a memory module.
`
`IX. Bechtolsheim
`41. I have been advised, and my understanding is, that Bechtolsheim is eligible
`
`to serve as prior art for the ’414 Patent under 35 U.S.C. § 102(b). Bechtolsheim
`
`
`
`13
`
`

`

`Attorney Docket No.: 37307-0007IP1
`
`was published on October 26, 1999 in the United States, more than a year before
`
`the priority date of the ‘414 patent. See Ex. 1004, Bechtolsheim. Based on my
`
`review of the ’414 patent file history, Bechtolsheim was not cited by the USPTO or
`
`considered by the Examiner during prosecution of the ’414 Patent. See Ex. 1007.
`
`42. Bechtolsheim teaches a “single in-line memory module (SIMM) for memory
`
`expansion in a computer system.” Ex. 1004, Bechtolsheim at Abstract. “The SIMM
`
`includes a plurality of memory chips surface-mounted on a printed circuit board.”
`
`Id. Figs. 1a, 1b, and 2a below illustrate a first face and a second face, Figs. 1a and
`
`1b respectively, and an arrangement of the “dynamic random access memory
`
`(DRAM)” chips on the first face of a printed circuit board. See e.g., Id. at 2:27-32;
`
`3:32-4:31; 5:13-15.
`
`
`
`14
`
`

`

`Attorney Docket No.: 37307-0007IP1
`
`43.
`
`
`
`15
`
`
`
`
`
`

`

`Attorney Docket No.: 37307-0007IP1
`
`44.
`
`
`
`45. In Bechtolsheim, the SIMM has a contact regions 50A and 50B for
`
`“insertion within a socket of [a] computer system.” Id. at Abstract; 5:13-23. The
`
`SIMM 5 also has DRAM 10 memory devices mounted on both faces of the SIMM
`
`5 that are electrically and mechanically connected. Id. at 3:32-4:31, Figs. 1a, 1b,
`
`2a. As shown in Fig. 2a, the DRAMs 10 are mounted with a longer edge parallel to
`
`the contact regions 50A and 50B. In Bechtolsheim the “DRAMs 10 [are] any of
`
`several commercially available DRAMs arranged in a ‘by-four’ configuration” and
`
`can include “error correction.” Id. at 3:48-50; 3:65-67.
`
`46. Further, Bechtolsheim includes an additional chip, a driver 15, mounted on
`
`the front face of the SIMM 5 and oriented such that a longer edge is perpendicular
`
`to the contact regions 50A and 50B. Id. at 3:32-55; 5:13-15; Figs. 1a and 2a.
`
`X. Tokunaga
`47. I have been advised, and my understanding is, that Tokunaga is eligible to
`
`serve as prior art for the ’414 Patent under 35 U.S.C. § 102(b). Tokunaga was
`
`
`
`16
`
`

`

`Attorney Docket No.: 37307-0007IP1
`
`published on March 14, 2000 in the United States, more than a year before the
`
`priority date of the ‘414 patent. See Ex. 1005, Tokunaga. Based on my review of
`
`the ’414 patent file history, Tokunaga was not cited by the USPTO or considered
`
`by the Examiner during prosecution of the ’414 Patent. See Ex. 1007.
`
`48. Tokunaga teaches a computer “memory module” that includes a plurality of
`
`“semiconductor memory devices.” Ex. 1005, Tokunaga at Abstract. Tokunaga
`
`demonstrates that it was well-known before the priority date of the ’414 patent to
`
`use typical semiconductor memory devices for “ECC function[s] and/or parity
`
`function[s]” to “check errors in input/output data” of the memory devices and
`
`ultimately the memory module. Id. at 4:62-67; 9:11-16.
`
`XI. Simpson and Karabatsos at the Time of the Invention
`49. Simpson alone or in combination with Karabatsos discloses the same
`
`technology that is allegedly the invention of the ’414 Patent.
`
`50. It would have been obvious to modify the printed circuit board and memory
`
`module design of Simpson to incorporate the constraints disclosed in Karabatsos.
`
`In the resulting design, Simpson would be constrained to a profile height of 1.2
`
`inches in order to address the problem of the “unavailability of DIMMs with lower
`
`profiles” as identified by Karabatsos. One of ordinary skill in the art would have
`
`been motivated to modify Simpson based on the design dimensions of Karabatsos
`
`
`
`17
`
`

`

`Attorney Docket No.: 37307-0007IP1
`
`to meet this market demand and would have had a reasonable expectation of
`
`success when doing so.
`
`51. Furthermore, because Simpson does not explicitly provide a height of the
`
`memory module 2, it would have been obvious to produce Simpson’s memory
`
`module 2 with a “height of between 1.125 and 1.250 inches” as taught by
`
`Karabatsos in order to meet the industry need identified by Karabatsos. Ex. 1003,
`
`Karabatsos at ¶ [0027].
`
`52.
`
`In addition, it would have been readily apparent to one of skill in the art that
`
`Simpson’s layout of semiconductor memory modules (as shown in FIG. 1,
`
`reproduced below) was readily adaptable, if needed, to meet Karabatsos’s
`
`suggested design height by, for example, simply eliminating the row of memory
`
`devices (e.g., memory devices 12g, 12e, 12c, and 12a) to reduce the profile height
`
`of the printed circuit board 2. Note that Simpson is clearly cognizant of this design
`
`flexibility. Ex. 1002, Simpson at 10:10-12 (“The quantity, position and type [of
`
`memory devices, error correction devices, or other semiconductor devices] are
`
`dependent upon the design preferences of the module designer and the organization
`
`of module chosen.”).
`
`
`
`18
`
`

`

`Attorney Docket No.: 37307-0007IP1
`
`53.
`
`
`
`
`54. Furthermore, a reduction in the number of memory devices on a board
`
`would not be a concern to one of skill in the art because, as evidenced by the Intel
`
`DIMM specification, it was known to replace lower rank memory devices (e.g., x8
`
`devices) with fewer higher rank memory devices (e.g., x16 or x32). See e.g., Ex.
`
`1008 Intel DIMM Specification at 34. A figure from page 34 of the Intel DIMM
`
`Specification that illustrates the use of various rank memory devices is reproduced
`
`below. Here, rank is used as would be known to one of skill in the art as
`
`terminology describing the configuration of a bit width of 64 bits (not counting any
`
`error correction bits), which can be accessed at the same time. Therefore, an x8
`
`rank would consist of 8 chips, each being 8 bits wide, while an x16 rank would
`
`consist of 4 chips, each being 16 bits wide. In other words, the ‘xX’ designation of
`
`the rank indicates the bit width of the individual chips used to achieve the overall
`
`64 bit wide rank. Note that bits used for ECC implementation are not included in
`
`
`
`19
`
`

`

`Attorney Docket No.: 37307-0007IP1
`
`the bit count. It would be straightforward to replace, for example, 8 x8 chips with 4
`
`x16 chips to maintain the same overall width.
`
`55.
`
`
`
`56. One of ordinary skill in the art would recognize that modifying Simpson to
`
`reduce the overall profile height of a memory module as taught by Karabatsos
`
`would address a growing industry need and meet a previously unmet market
`
`demand. The motivation to combine the references was obvious.
`
`57. Rearranging memory devices on a memory module to reduce the height of
`
`Simpson’s memory module was well within the knowledge of a person of ordinary
`
`
`
`20
`
`

`

`Attorney Docket No.: 37307-0007IP1
`
`skill by the priority date of the ’414 patent. This can be seen at least by the section
`
`from the Intel Specification shown above, which illustrates three different designs
`
`with two different orientations for memory chips. The Intel Specification evidences
`
`that one of ordinary skill in the art would be know how to rearrange chips on a
`
`DIMM Board and could readily do so, if there was a design requirement, such as
`
`standard compliance or a design requirement that mandated a particular dimension
`
`of printed circuit board, such as a target height.
`
`XII. Bechtolsheim, Karabatsos, and Tokunaga at the Time of the Invention
`58. Bechtolsheim in combination with Karabatsos and Tokunaga discloses the
`
`same technology that is allegedly the invention of the ’414 Patent.
`
`59. It would have been obvious to modify the printed circuit board and memory
`
`module design of Bechtolsheim to incorporate the constraints disclosed in
`
`Karabatsos. In the resulting design, Bechtolsheim would be constrained to a profile
`
`“height of between 1.125 and 1.250 inches” in order to address the problem of the
`
`“unavailability of DIMMs with lower profiles” as identified by Karabatsos. One of
`
`ordinary skill in the art would have been motivated to modify Bechtolsheim based
`
`on the design dimensions of Karabatsos to meet this market demand and would
`
`have had a reasonable expectation of success when doing so.
`
`60. Furthermore, because Bechtolsheim does not explicitly provide a height of
`
`the SIMM 5, it would have been obvious to produce Bechtolsheim’s SIMM with a
`
`
`
`21
`
`

`

`Attorney Docket No.: 37307-0007IP1
`
`“height of between 1.125 and 1.250 inches” as taught by Karabatsos in order to
`
`meet the industry need identified by Karabatsos. Ex. 1003, Karabatsos at ¶ [0027].
`
`61. Moreover, it would have been readily apparent to one of skill in the art that
`
`Bechtolsheim’s layout of semiconductor memory modules (as shown in FIG. 2a,
`
`reproduced below) was readily adaptable, if needed, to meet Karabatsos’s
`
`suggested design height by, for example, simply eliminating the row of memory
`
`devices to reduce the profile height of the SIMM 5.
`
`62.
`
`
`
`
`63. Furthermore, a reduction in the number of memory devices on a board
`
`would not be a concern to one of skill in the art because, as evidenced by the Intel
`
`DIMM specification, it was known to replace lower rank memory devices (e.g., x8
`
`devices) with fewer higher rank memory devices (e.g., x16 or x32). See e.g., Ex.
`
`1008 Intel DIMM Specification at 34. A figure from page 34 of the Intel DIMM
`
`
`
`22
`
`

`

`Attorney Docket No.: 37307-0007IP1
`
`Specification that illustrates the use of various rank memory devices is reproduced
`
`below. See the discussion of memory rank above.
`
`64.
`
`
`
`65. One of ordinary skill in the art would recognize that modifying
`
`Bechtolsheim to reduce the overall profile height of a memory module as taught by
`
`Karabatsos would address a growing industry need and meet a previously unmet
`
`market demand. The motivation to combine the references was obvious.
`
`
`
`23
`
`

`

`Attorney Docket No.: 37307-0007IP1
`
`66. Rearranging memory devices on a memory module to reduce the height of
`
`Bechtolsheim’s memory module was well within the knowledge of a person of
`
`ordinary skill by the priority date of the ’414 patent.
`
`67.
`
`It would also have been obvious to one of skill in the art before the priority
`
`date of the ’414 patent to combine the teachings of Tokunaga with those of either
`
`or both Bechtolsheim and Karabatsos. As noted above, Tokunaga demonstrates
`
`that it was well-known before the priority date of the ’414 patent to use typical
`
`semiconductor memory devices for “ECC function[s] and/or parity function[s]” to
`
`“check errors in input/output data” of the memory devices and ultimately the
`
`memory module. Ex. 1005, Tokunaga at 4:62-67; 9:11-16. One of skill in the art
`
`would be motivated to configure one of the memory devices of either
`
`Bechtolsheim or Karabatsos to provide improved memory modules with error
`
`checking capability.
`
`68. Furthermore, although Bechtolsheim shows a driver 15 as being arranged
`
`perpendicular to contact regions 50A and 50B, instead of an error correction chip,
`
`as disclosed by the ’414 patent, Bechtolsheim’s Fig. 2a explicitly illustrates that
`
`the general arrangement of a plurality of horizontally oriented chips and one
`
`vertically oriented chips on a printed circuit board was well-known. As noted
`
`above, there is no indication in the ’414 patent that orienting the error correction
`
`chip 5, rather than a memory or other type of semiconductor chip, vertically is
`
`
`
`24
`
`

`

`Attorney Docket No.: 37307-0007IP1
`
`anything other than a design choice. Consequently, it is my opinion that orienting a
`
`memory device configured to perform error checking, as discussed in Tokunaga,
`
`vertically on Bechtolsheim’s SIMM 5 would have been an obvious design choice
`
`to one of skill in the art. For example, one may choose to place such a vertically
`
`oriented error checking memory device in place of Bechtolsheim’s driver 15 and
`
`move the driver 15 under one of the horizontally oriented memory devices, as
`
`shown by the location of register chip 6 and PLL chip 8 in Fig. 1C of Karabatsos
`
`(reproduced and annotated below).
`
`69.
`
`
`
`70. As another example, one may choose to place a vertically oriented error
`
`caching memory device in the center of the back side of Bechtolsheim’s SIMM 5,
`
`as shown in Bechtolsheim’s Fig. 1b as annotated below.
`
`
`
`25
`
`

`

`Attorney Docket No.: 37307-0007IP1
`
`71.
`
`
`
`
`
`XIII. Certain References Disclose And/Or Render Obvious All Elements of
`Claims 1 and 4 of the ‘414 Patent.
`A. Simpson alone or in combination with the Intel Specification,
`renders obvious all elements of Claims 1 and 4 of the ’414 Patent
`1.
`Claim 1
`a. “An electronic printed circuit board configuration,
`comprising:”
`72. In my opinion, Simpson discloses an electronic printed circuit board
`
`configuration. See Ex. 1002, Simpson, at 1:10-23, 2:17-20, and 4:28-5:5. Marked-
`
`up Figure 1 of Simpson clearly illustrates an electronic printed circuit board. Id.
`
`
`
`26
`
`

`

`Attorney Docket No.: 37307-0007IP1
`
`73.
`
`
`b. “An electronic printed circuit board having a contact
`strip for insertion into another electronic unit; and”
`74. In my opinion, Simpson discloses an electronic printed circuit board having
`
`a contact strip for insertion into another electronic unit. See Ex. 1002 at 2:24-30,
`
`9:8-16, 10:21-30, and 12:10-14. Specifically, Simpson chooses to use the term
`
`“connector terminal strip 10” rather than “contact strip;” however, the terms are
`
`interchangeable as one of ordinary skill in the art would recognize.
`
`75. This marked-up figure below illustrates how Simpson teaches this element.
`
`Id.
`
`
`
`27
`
`

`

`Attorney Docket No.: 37307-0007IP1
`
`76.
`
`
`c. “A memory module having at least nine identically
`designed integrated semiconductor memories;”
`77. In my opinion, Simpson discloses a memory module having at least nine
`
`identically designed integrated semiconductor memories. See Ex. 1002, Simpson,
`
`at Figures 1 and 3, 5:12-18, 5:34-35, 7:8-12, 8:5-11, 9:18-27, 10:10-19, 13:7-12,
`
`and 13:28-32.
`
`78. As shown in Figure 1, on a single side, Simpson discloses a base module 2
`
`that “consists of an array of memory devices 12A-12H[.]” Ex. 1002, Simpson,
`
`9:18-20; Fig. 1. Module 2 of Simpson also includes a ninth semiconductor memory
`
`16A on that same side. Ex. 1002, 10:14-25 (referring to each of the chips 12A-12H
`
`and 16A as memory devices). Those of ordinary skill in the art would understand
`
`that the memory device 16A is identical to each of memory devices 12A-12H. See
`
`Ex. 1002, Simpson at 11:22-28 (referring to power and signals collectively for all
`
`
`
`28
`
`

`

`Attorney Docket No.: 37307-0007IP1
`
`of the memory devices) and 12:10-14 (describing common capacitors used to
`
`supply power to each of the memory devices).
`
`79. However, the ’414 patent are not limited to having chips on a single side of
`
`the PCB. Simpson makes clear that “memory devices 12 may be mounted on both
`
`sides of the module 2.” Ex. 1002, Simpson, 13:7-12. The illustrated embodiments
`
`of Simpson envision empty sockets 14C-14J populated with memory devices 18A-
`
`18H plugged in for added memory. Simpson, Ex. 1002, 10:14-19; Fig. 3. One of
`
`ordinary skill in the art would also plainly recognize that replaceable memory
`
`devices 18A-18H could be identical to memory devices 12A-12H, as this decision
`
`would merely depend on in order to enable the addition of those eight chips to
`
`increase “the module designer memory capacity from 4Mbits to 8Mbits in length
`
`by plugging into sockets 14C-14J memory devices 18A-18H. See Ex. 1002,
`
`Simpson, 10:10-12; Figs. 1-3. Additionally, sockets 14A-14B could also be filled
`
`with memory devices identical to memory devices 12A-12H as one of ordinary
`
`skill in the art would recognize. Id.
`
`80. This marked-up figure below illustrates how Simpson teaches this element.
`
`Id.
`
`
`
`29
`
`

`

`Attorney Docket No.: 37307-0007IP1
`
`81.
`
`
`d. “Each one of said semiconductor memories being
`encapsulated in a rectangular housing having a
`shorter dimension and a longer dimension;”
`82. In my opinion, Simpson discloses that each one of said semiconductor
`
`memories are encapsulated in a rectangular housing having a shorter dimension
`
`and a longer dimension. See Ex. 1002, Simpson, at Figures 1 and 2.
`
`83. Marked-up Figure 1 illustrates how Simpson teaches this element. Id.
`
`84.
`
`
`
`85. Also, Marked-up Figure 2 illustrates this element. Id.
`
`
`
`30
`
`

`

`Attorney Docket No.: 37307-0007IP1
`
`86.
`
`
`
`87. Further, in my opinion, a person of ordinary skill in the art would have
`
`understood that Figures 1-3 illustrate memory devices 12, 16, and 18 as being—or
`
`could be modified to be—encapsulated in housings, as there is nothing inventive
`
`about this limitation. Also, Simpson discloses that “memory devices 12A-12H are
`
`electrically and mechanically connected to the substrate 4.” Ex. 1

This document is available on Docket Alarm but you must sign up to view it.


Or .

Accessing this document will incur an additional charge of $.

After purchase, you can access this document again without charge.

Accept $ Charge
throbber

Still Working On It

This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.

Give it another minute or two to complete, and then try the refresh button.

throbber

A few More Minutes ... Still Working

It can take up to 5 minutes for us to download a document if the court servers are running slowly.

Thank you for your continued patience.

This document could not be displayed.

We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.

Your account does not support viewing this document.

You need a Paid Account to view this document. Click here to change your account type.

Your account does not support viewing this document.

Set your membership status to view this document.

With a Docket Alarm membership, you'll get a whole lot more, including:

  • Up-to-date information for this case.
  • Email alerts whenever there is an update.
  • Full text search for other cases.
  • Get email alerts whenever a new case matches your search.

Become a Member

One Moment Please

The filing “” is large (MB) and is being downloaded.

Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.

Your document is on its way!

If you do not receive the document in five minutes, contact support at support@docketalarm.com.

Sealed Document

We are unable to display this document, it may be under a court ordered seal.

If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.


Access Government Site

We are redirecting you
to a mobile optimized page.





Document Unreadable or Corrupt

Refresh this Document
Go to the Docket

We are unable to display this document.

Refresh this Document
Go to the Docket