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`
`US005973951A
`
`United States Patent
`
`[19]
`
`Bechtolsheim et al.
`
`[11]
`
`[45]
`
`Patent Number:
`
`5,973,951
`
`Date of Patent:
`
`*Oct. 26, I999
`
`SINGLE IN-LINE MEMORY MODULE
`
`FOREIGN PATENT DOCUMENTS
`
`[54]
`
`[75]
`
`Inventors: Andreas Bechtolsheim, Stanford;
`Fdwar-d Frank, Portola Valley; James
`Tesla, Mountain View; Shawn Storm,
`Mt. View, all of Calif.
`
`I73]
`
`Assignee:
`
`Sun Miemeystems, [nc.. Palo Alto,
`Calif.
`
`[*1
`
`Nfilltiei
`
`This patent issued on a continued pros~
`ecution application filed under 37 CFR
`1.53(d), and is subject to the twenty year
`patent
`term provisions: of 35 U.S.C.
`]54(a)(2).
`
`This patent is subject to a terminal dis-
`clairncr.
`
`[21]
`
`[31]
`
`[53]
`
`[51]
`[53]
`
`[53]
`
`[55]
`
`App]. No; os;a7s,-ans
`
`Filed:
`
`Jun. 19, 1997
`
`Related U.S. Application Data
`
`Continuation of application No. I38;‘643,ITt94. May 2, 1996,
`abandonetl, which is PI continuation of application No.
`tJ8i’4?3,El".u"3, Inn. 7, 1995, Pat. No. 5,532,954, which is a
`continuation of application No. O3i“345,41'7, Nov. 28, 1994,
`Pat. No. 5,465,229, which is 3.1 continuation of application
`No. El8«'2'F9,S24,Ju1. 25. 1994, Pat. No. 5,333,143, which is
`a continuation of application No. 08.? 115,438, Sep. 1, 1993,
`abandoned, which is a continuation of application No.
`EF",f386,4l3, May 19, 1992, Pat. No. 5,270,904.
`
`Int. Cl.“
`US. Cl.
`
`Field of Sear-cli
`
`.
`
`GllC I3i’00
`365352; 365.51; 365159;
`365353
`sesysz, 51, 53,
`3o5..='63, 59
`
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`
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`
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`Noel Kjvlin
`
`[57]
`
`ABSTRACT
`
`for memory
`A single in-line memory module (SIMM)
`expansion in a computer system. The SIMM includes at
`plurality of memory chips surface-niounted on a printed
`circuit board. The printed circuit board includes a dual
`read—out connector edge adapted for insertion within a
`socket of the computer system. One or more driver chips
`may further be mounted on the printed circuit board and
`connected to distribute control signals to the memory chips.
`Aful1~width data path may further be connected between the
`dual read-out connector edge and the plurality of memory
`chips.
`
`(List continued on next page.)
`
`51 (Joints, 6 Drawing Sheets
`
`
`
`1
`
`KINGSTON 1004
`
`KINGSTON 1004
`
`

`

`5,973,951
`Page 2
`
`U.S. PATENT DOCUMENTS
`
`439.3296
`12.51992 Yang Lee
`5,169,333
`2571724
`311,993 Wu el al.
`5,191,404
`439,132?
`371993 ]3,'_]|m,—,n 31 ML ,_
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`471993 Slaaflcr ct al.
`5,200,917
`2570686
`[El/1993 Kane et al.
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`365;-'63
`11.0993 Tesla
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`5,2b3,8T"0
`2,265,218 1171993 Team at a]._ ........................... .. 3951325
`:>,270_.'9o4
`12.11993 Bcchtolshc-1m et al.
`362032
`$272,694 12-‘I993 A1e>§andereta1-
`. #763792
`471994 PM-gale! =11‘
`- 363-03
`2.-319991 W994 Tam’? 0‘ 31-
`363-“?
`?,33.!;,2:g
`Talragl
`.......................................
`-"I.
`T_°“’_‘_" "‘ 3"
`.
`‘_‘ M2
`i’
`J’
`3,420,824
`1s.a]1moto clal.
`36:v,’230.U1
`::.’1‘)05
`.
`.
`_ _
`5,405,229
`11.-1995 Bechlolshenn et al.
`363.532
`5 572954
`771995 Becht-0191151111 et al
`765752
`‘
`"
`‘
`'
`‘
`OT]-[ER pU]3[_1C,1[['[QN5
`
`
`
`
`
`
`
`memory
`
`"“"'“““"3’
`
`Kings on Technology l{TC386H40'00 (200][I]2) memory
`board Dolor photocopies, 3 sheeis, 1989,
`on Technology
`hoard schemafic, 4 Sheets, lggg
`K1.
`1. h
`1
`K.l.V_U“U 16 goululs
`3° "0 ‘Q j
`5
`’
`(-
`5)
`"35 0“
`bcfard °°1°‘" Ph°‘°°°P‘°5~ ~ Shwsv 1939-
`Kings-on Tcchnology KTV5000r’16 (’30f|10l.5) memory
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`hmmj mm,» p]]m[,mpy, 1 511531, 1939
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`bflard schemaIi_ 7, Shams 1989
`‘
`,
`‘"7
`°
`Kings on Technology KST4090.-’35 (2001086) m-=lIl0r)'
`board color photocopies, 2 sheets. I990.
`King; on Technology KST44000,’25 (2001086) memory
`hoard schematic, 2 .~'.he1:L=-;, 1990.
`.
`Kjngs on Technology KTC2‘SLT3SI5—4 (2001090) memory
`“Md 001°!‘ Ph°‘°C°P1°-5» 3 SW75» 1990-
`Kings.on Technology I{'I'C7’SL'l'386—4 (2001090) memory
`board schematic. 3 sheets, 1990.
`
`Kings on Technology KDGH1000 (2001092) memory hoard
`‘film jhotom -C
`,, Rhea‘; 1990
`‘
`“,
`P‘ S’ 7"
`"
`K1n3S10r}T<%hD01<'3Y KDG16000(2001092)mem0f)'board
`schernal1c,3,sheuls,1990.
`Kings on Technology KTV31'1’64,F4 (2001122) memory
`board mjor photocopies, 2 5116315‘ 1990,
`1
`_
`.
`_
`_
`.
`K1ng,s01'_1TI:Lhnology KT\/317674 (2001 122) memory board
`5°h‘~3m3‘1°v 3 Shem» 15'” 1991-
`Kings on Technology KTC4000E (2001157) memory board
`color jhotoggpjegg 3 gheetg,
`—
`“:35 ‘’['?T‘‘6°h::?}‘[’3Y1I9{81;,C4°°°E (2001157) “3"'“’°’3’ b°“"
`5° ‘’“‘‘'“°'
`5 °° 5*
`'
`Compaq computer (Model #101709) memory board #RA
`004163 color phmocoy, 1 sheet, 1986.
`Compaq SLT1’2B6 computer (Model 2680) memory board
`--.
`4
`-
`#°L33lJ27CM °°l°r 1’h°'°°°1’y‘ 1 Sheet’ 198%‘
`_
`Sam M1cms_vs.rem.s', 1.711;. V. Dnmrnm CtJf‘p0f'{J'1‘10f1, Complzunl
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`.
`,,
`9
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`33*J7"'l?
`4397325
`439,-'32.?
`. 439.3329
`439,-“Z80
`, 3397175 Mp
`43973215
`355751
`.2s77305
`.. 4397329
`365,154
`_. 3557235
`. _
`M5752
`
`
`
`------
`
`
`
`671972 Alnmon eral.
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`..
`4,154,751
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`433,719
`3/1931 McGinley .
`4,262,340
`4,1981 Sasaklu et 3'
`4.394.753
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`_____ __
`'
`'
`_
`4,426,689
`I/1984 I1.-2.11.4 :1 al.
`.
`29-‘£32
`”1934 H‘‘''3‘5 """""" "
`‘‘-~‘‘3‘’~m
`4397255
`171934 Hsunsher,Jr. eta].
`4,428,635
`2577211
`211935 Ohno et al.
`4,500,906
`.. 439.3323
`lF|.4'l.985 Rohenson .
`4,543,456
`3397134 M
`1211985 Col1e1 et al.
`4,553,912
`3/[937 DE>Pfl11|
`...................................... 29.-‘I174
`4,551,416
`
`4;'l.987 Clayton
`305.-"52
`4,656,605
`7/[937 Aka-Saki fl 3'-
`3373700
`4.-532.-307
`Q/1937 Grahbe elal.
`4391’2I‘;6
`4,695,111
`971937 Verhocvcn or 11.
`. 4597257
`4,595,529
`10/1937 Hvezda at 41.
`4397235
`4,700,993
`211933 Angleion el al.
`3557131
`4,724,531
`221,933 Clayton ______ ..
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`4,727,513
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`' 35{'”05
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`4,795,224
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`4,802,132
`- - - - -
`50939 NDSC-‘hfse
`‘ - - -- 43‘J.=’3'5U
`4.~342.~5'33
`$333 galkvp 9! al»
`jjggggé
`_
`a ton
`.
`,
`,
`_
`11,1989 Johison
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`
`..
`
`..
`
`
`
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`4397326
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`.
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`6/1991 Sudo et al.
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`5,051,994
`911991 B1Ll:thh1an el :11.
`37?1711.1
`5_.ne'.1_.990
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`1/1992 Billman at al.
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`..
`10)’ e a.
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`9,0992 Yeung
`E” 5113;‘ “"|
`'3
`-“
`.
`-‘
`I "
`3 .
`fl 3'
`5,102,970 11{1992 Dav1d_.J1. Ct at.
`1171992 Anzelone el al.
`5,152,979
`
`5_.l0'4_,016
`1111992 Wu et al.
`__
`5,157,517
`1271992 bong
`
`.
`2577773
`,_ 357,742
`439774
`31557326
`
`5
`‘bl
`361732
`4397415
`365752
`4397150
`
`2
`
`_
`,
`5,119,170
`5,126,910
`5,133,434
`5,145,396
`
`

`

`5,973,95 I
`Page 3
`
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`
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`IBM Personal System!2 Model P10 386 Quick Reference,
`Nov. 1987-‘ (excerpts—9 double sided sheets).
`IBM Personal System;’2 Model P70 386 (Type 8573), Jan.
`23, 1990, (exoerpts—11 double sided sheets).
`IBM 2-8MB 80386 Memory Expansion Option Technical
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`IBM Portable PS.=’2 Models P70 and P75, Technical Aware-
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`sheets).
`DEC‘ MSOI SIMM samples (1 colored sheet).
`Gavilon Computer Memory Module (2 colored sheets).
`
`3
`
`

`

`5,973,95 I
`Page 4
`
`HP 3006 Module (1 colored sheet).
`Micron XCEED Card (1 colored sheet).
`NCRO Module (1 colored sheet).
`S-1 Memory Card Model #2065 (2 colored sheets).
`High Performance Package for Memory;
`IBM Technical
`Disclosure Bulletin, vol. 21, No. 2, Jul. 1928.
`Semiconductor Packaging Using “Chip Mate” Concept With
`Dual Inline Package (DIP) for Bonded Vias, Tenninals and
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`1M><1 Bit
`Samsung Electronics, K_M4lC10UOC./C.tCSL,
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`DEC-Compatible Memory Expansion Boards for Microvax
`3X00 Series Computers, DR.—300.
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`VAX 4000 Model 100, and Micro VAX 3100 Model 30, 40,
`80 and 90 workstations”, Dataran1.'fhc Memory Specialists
`Apr. 1993, 2 pages.
`Texas Instruments, MOS Memory Data Book Commerical
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`Mitsubishi Electric Corp., Semiconductor Marketing Divi-
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`PERICOM Serniconductor C‘orp., Application briel-5,
`Pl74F'CT162344"? For Heavy l.JJ3£l Applications, pp.
`692-693.
`
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`loaded from http:i’,r“www.tclcmagic.com,-=’html,t'enspcc1.htm,
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`B. Issue date: Sep. 1995, pp. 1-38.
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`Corporation,
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`lattice
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`Advanced Product Research, Camden, New Jersey, pp.
`511-525.
`
`(12
`
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`Intcrconnections,” I-Ioneywell, Inc., IEEE Spectrum, Jul.
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`sion Lines Into Multilayer Circuit Boards“, Electronics,
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`AMP Customer Drawing 90-14-39-24, (2 pages).
`AMP Customer Drawing 91—.‘t793—1, (2 pages).
`Top, bottom and side views of Atari (‘X853 Memory Mod-
`uie (color copy), (1 page).
`Top and bottom views Printed Circuit Board of'Atari CX853
`(color copy), (1 page).
`Sams Computerfacts Technical Service Data, Atari Model
`800 Computer, (41 pages).
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`Sheet, (16 pages).
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`Tri-State Outputs, (10 pages).
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`dom-Access Memory Data Sheet, (14 pages).
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`Cartridge, (1 page).
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`dorc VlC—l111 16K RAM Cartridge, (1 page).
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`"Data Sheet, (8 pages).
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`(color copy), (1 page}.
`Texas Instruments SN54Al_S1034 Hex Drivers Data Sheet,
`(6 pages).
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`(excerpts), (14 pages).
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`boards for HP Apollo 9000 Series 700 computers, (2 pages).
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`upgrade kits, documentation, (3 pages}.
`CE Handbook HP Apollo 9000 Series ‘I00 Workstation!
`Servers, (34? pages).
`
`4
`
`

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`U.S. Patent
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`Oct. 26, 1999
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`U.S. Patent
`
`Oct. 26, 1999
`
`Sheet 6 M6
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`5,973,951
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`

`5,973 ,951
`
`1
`SINGLE IN-LINE MEMORY MODULE
`
`This is a continuation application of Scr. No. 08t'643.tl94,
`filed May 2. "1996 now abandoned which ‘is a continuation of
`Ser. No. 08/473,023, filed Jun. 7, 1995. now US. Pat. No.
`5,532,954 issued Jul. 2, 1996, which is a continuation of Ser.
`No. 08l345,4"t"? filed Nov. 28, 1994, now US. Pat. No.
`5,465,229 issued Nov. 7, 1995, which is a continuation of
`Ser. No. 08,879,824, filed Jul. 25, 1994, now U.S. Pat. No.
`5,383,148 issued Jan. 17, 1995, which a continuation ol‘Ser.
`No. 08r'115,438, filed Sep. 1, 1993, now abandoned, which
`is a continuation ofSer_ No. 07}?-186,413, filed May 19, I992,
`now U.S. Pat. No. 5,270,964, issued on Dec. 14, 1.993.
`
`BACKGROUND OF THE INVENTION
`
`it’)
`
`15
`
`1. Related Applications
`This application is related to US. Pat. No. 5,260,892,
`entitled “High Speed Electrical Signal Interconnect
`Structure", issued Nov. 9, 1993 and US. Pat. No. 5,265,218,
`entitled ‘Bus Architecture for Integrated Data and Video
`Memory‘, issued Nov. 23, 1993.
`2. Field of the Invention
`
`25
`
`39
`
`35
`
`60
`
`invention relates to the field of computer
`The present
`systems and memory hardware. More particularly,
`the
`present invention relates to modular circuit boards which
`may be combined to fonn a memory structure within a
`computer system.
`3. Art Background
`Single In-Line Memory Modules (“SIMMS”) are compact
`circuit boards designed to accommodate surface mount
`memory chips. SIMMS. were developed to provide compact
`and easy to manage modular memory components for user
`installation in computer systems designed to accept such
`SIMMS. SIMMS general.ly are easily inserted into a connec-
`tor within the computer system, the SIMM thereby deriving
`all necessary power, ground, and logic signals therefrom.
`A SIMM typically comprises a mttltiplicity of random
`access memory (“R AM”) chips mounted to a printed circuit
`board. Depending on the user’s needs, the RAM memory
`chips may be dynamic RAM (DRAM), non volatile static
`RAM {SRAM) or video RAM (\/RAM). Because DRAM
`memories are larger and cheaper than memory cells for
`SR/\Ms, DRAMS are widely used as the principal building
`block. for main memories in computer systems. SRAM and
`VRAM SIMMs have more limited application for special
`purposes such as extremely fast cache memories and video
`frame buffers, respectively. Because DRAMs form the larg-
`est portion of a computer system memory,
`it
`is therefore
`desirable that memory modules flexibly accornmotlate the .
`computation needs of a user as the users’ requirements
`change over time. Moreover, it is desirable that the SIMM
`modules tnay be added to the computer system with a
`minimum user dilficulty, specifically in terms of configura-
`J:‘J:
`tion of a SIMM within a particular memory structure. In the .
`past, SIMMs have generally been designed to provide
`memory increments of one or more megabytes (MB), but
`where the memory addition comprises only a portion of the
`full data path used in the computer system. A leading
`example of the prior an organization and structure is that
`disclosed in US. Pat. No. 4,656,605, issued Apr. 7, 1987 to
`Clayton. Clayton discloses a compact modular memory
`circuit board to which are mounted nine memory chips
`which are arranged to provide memory increnrents in eight
`bit (one byte) data widths, plus parity bits. Thus, because
`most oomputer systems use data paths of 32, 64 or more bits,
`the SIMM constructed according to Clayton cannot provide
`
`2
`a memory increment for the entire data path. Instead the user
`must obtain and install multiple SIMD/ls,
`in combination
`with performing any additional configuration requirements
`necessary to make the separate SIMMS modules function as
`a single memory unit, such as setting base addresses for the
`SIMM modules installed.
`
`As a result, a user seeking to increase his usable main
`memory by adding SIMMs constructed according to the
`prior art, typically must insert multiple SlMlVls to achieve a
`memory expansion for the entire data path of his computer.
`The foregoing is a consequence of typical prior art SIMM
`architecture, wherein the SIMM is arranged around DRAM
`parts which comprise one byte wide memory increments.
`Thus in a data path having a width of 32 bits, there being
`eight bits per byte, :1 1 megabyte expansion ofmain memory
`using SIMMs constructed according to the prior art would
`require four SIMM modules each of one megabyte capacity
`in order to obtain a full data path expansion of one mega-
`byte.
`in the following
`As will be described in more detail
`detailed description, the present invention provides, among
`other attributes, facility for providing memory expansion in
`Full data path widths, thereby relieving the user oi‘ contig-
`uring and installing multiple SlMMs modules to obtain any
`desired memory increment.
`SUMMARY OF THE INVENTION
`
`A full width single in-line memory module (SIMM) for
`dynamic random access memory (DRAM) memory expan-
`sions is disclosed. A printed circuit board having a multi-
`plicity of DRAM memory elements mounted thereto is
`arranged in a data path having a width of 144 bits. The
`SIMM of the present invention further includes on—board
`drivers to bulfer and drive signals in close proximity to the
`memory elements. In addition, electrically conductive traces
`are routed on the circuit board in such a manner to reduce
`
`loading and trace capacitance to minimize signal skew to the
`distributed memory elements. The SIMM further includes a
`high pin density dual read-out connector structure receiving
`electrical traces from both sides of the circuit board for
`enhanced functionality. The SIMM is installed in oomple-
`mentary sockets one SIMM at a time to provide memory
`expansion in full width increments. Finally, symmetrical
`power and ground routings to the connector structure insure
`that
`the SIMM cannot be inserted incorrectly, wherein
`physically reversing the SIMM in the connector slot will not
`reverse power the SIMM.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The objects, features and advantages of the present inven-
`tion will be apparent from the following detailed description
`given below and from the accompanying drawings of the
`preferred embodiment of the invention in which:
`FIG. la illustrates the electrical schematic of a first side
`of the single in—line memory module (SIMM) according to
`the teachings of the present invention.
`FIG. 1b illustrates the electrical schematic for a left—to-
`right mirror image layout of memory elements on a second
`side of the SIMM.
`
`l'"l('_i. 2a illustrates the physical layout of the memory
`elements and drivers placed on the SIMM.
`FIG. 2b is a magnilied view ofthe dual read-ottt connector
`structure on the SIMM.
`
`FIG. 3 illustrates the stacked conductive layers separated
`‘ by insulating dielectric necessary to bttild up the intercon-
`nections for the electrical schematic shown in FIGS. la and
`lb.
`
`11
`11
`
`

`

`5,973 ,951
`
`3
`FIGS. 4a and 4!? are a connector diagram illustrating data,
`address and control signals routed to a SIMM.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`A bus architecture for integrated data and video memory
`is disclosed. In the following description, for purposes of
`explanation, specific numbers, times, signals etc., are set
`forth in order to provide a thorough understanding of the
`present invention. However, it will be apparent to one skilled
`in the art that the present invention may be practiced without
`these specific details. In other instances, well known circuits
`and devices are shown in block diagram form in order not to
`obscure the present invention unnecessarily.
`The preferred embodiment of the SIMM described herein
`is designed and intended to be used with the integrated data
`and video memory bus disclosed in copending US. patent
`application Ser. No. 07f88tS,IS71, filed May 19, 1992, now
`U.S. Pat. No. 5,265,218, issued Nov. 23, 1993 entitled “A
`Bus Architecture For Integrated Data and Video Memory”.
`It will be apparent, however, to those skilled in the art that
`the specifications disclosed herein can or may be changed
`without departing from the scope of. the present invention.
`Although the preferred embodiment of the present invention
`is disclosed in terms of the data path width matching that of
`the integrated data and video memory bus disclosed in the
`above-referenced U.S. patent application, it will be appre-
`ciated that changing the design of the bus is within the scope
`of the present invention, wherein the SIMM may be matched
`to the data path width of the integrated memory bus.
`Reference is now tnade to FIG. In wherein an electrical
`block diagram of memory elements mounted to a first,
`obverse side of the SIMM is shown. In FIG. lo, a multi-
`plicity of dynamic RAM (DRAM-s) are grouped into two
`clusters 10a and 1015-. There are nine DRAMs II) in each
`cluster. A driver 15 receives control signals, and address
`signals from an external bus arrangement {not shown)
`through a dual sided connector 30. A multiplicity of control
`lines 20 route RAS-(row access strobe}, CAS— (column
`access st robe), WE- (write enable), and OE- (output enable),
`control signals from driver 15 to all the DRAMS 10 mounted
`to SIMM 5. Moreover, driver 15 buffers and subsequently
`distributes address signals 21 to all DRAMS ll} mounted to
`SIMM 5. For purposes of clarity in the present figure, the
`specific routing of data, address and control lines to all the
`DRAMS 10 is omitted. However, as can be seen from FIG.
`In, all Dl~lAMs 10 have four data lines, Dl{AMs 10 being
`any of several commercially available Dl{AMs arranged in
`a "by-four" configuration. Aswill be seen below in connec-
`tion with FIG. lb, DRAMS ll} each of DRAM clusters 100
`and 10b are matched with mirror
`image DRAMs 10
`mounted to the opposite side of SIMM 5 and placed in
`electrical communication by electrical
`traces passing
`through a multiplicity of vias (not shown).
`'Ihe specific routing of the electrical traces on SIMM 5 are
`d