throbber
(12) UK Patent (19) G 8 (11) 2 246 005c13) 8
`
`{54)
`
`Title of Invention
`Sense amplifier driving circuit for a
`semiconductor memory circuit
`
`(51)
`
`INTCL5;G11C7/00
`
`(72)
`
`lnventor(s)
`Dong-Sun Min
`Hong-Sun Hwang
`Soo-ln Cho
`Dae-JeChln
`
`(73)
`
`Proprietor{s)
`Samsung Electronics Co
`Limited
`
`(Incorporated In the Republic
`of Korea)
`
`{74)
`
`416 Maetan-dong
`Kwonsun-ku
`Suwon
`Kyunggl-do
`Republic of Korea
`
`Agent and/or
`Address for Service
`Appleyard Lees
`15 Clare Road
`Halifax
`West Yorkshire
`HX12HY
`United Kingdom
`
`{21)
`
`Application No
`9110880.3
`
`(22) Date of filing
`20.05.1991
`
`(30)
`
`Priority Data
`
`(31) 907388
`
`(32) 23.05.1990
`
`(33) KR
`
`{43)
`
`(45)
`
`Application published
`15.01.1992
`
`Patent published
`31.08.1994
`
`{52) Domestic classification
`(Edition M)
`G4C C11409A C706
`
`{56) Documents cited
`GB2232516A
`GB2220810 A
`GB2213668A
`EP0205294 A2
`US4888503A
`US4038646A
`
`(58)
`
`Field of search
`
`As for published application
`2246005 A viz:
`UK CL(Edition K) H3P PLSS
`PLSWPLX
`Online database: WPI
`updated as appropriate
`
`Page 1 of 56
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`Page 9 of 56
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`Page 11 of 56
`
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`Page 12 of 56
`
`

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`
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`Page 13 of 56
`
`

`
`2246COS
`
`-
`
`1 -
`
`SENSE AMPLIFIER DRIVING CIRCUIT
`FOR A SEMICONDUCTOR MEMORY CIRCUIT
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`The present invention relates to a sense amplifier
`driving circuit and particularly, although not
`exclusively, to a sense amplifier driving circuit which is
`suitable for use in a high density semiconductor memory
`device.
`
`Recently, many different kinds of semiconductor
`memory devices have been developed in which miniaturised
`sense amplifiers are used for amplifying data stored in
`memory cells. However, as the density of memory cells in
`such semiconductor memory devices
`increases, problems
`appear in that peak currents of sense amplifier driving
`signals reach high levels, causing increased noise levels,
`and the stability of the sense amplifiers deteriorates
`during driving of
`the sense amplifiers.
`Therefore,
`efforts have been made to reduce the peak current of the
`sense amplifier driving signals in order to reduce noise
`caused thereby, and to thus improve the stability of the
`sense amplifiers.
`
`Operation of a conventional sense amplifier driving
`circuit will now be described with reference to Figures 1
`and 2 of the accompanying drawings in which:
`
`schematic diagram of a
`is a
`lA
`Figure
`conventional sense amplifier driving circuit;
`
`first
`
`schematic diagram of a
`is a
`lB
`Figure
`conventional sense amplifier driving circuit; and
`
`second
`
`Page 14 of 56
`
`

`
`-
`
`2 -
`
`Figure 2 shows a timing chart for signals generated
`in the conventional sense amplifier driving circuits of
`Figure 1.
`
`-
`
`Referring to Figure lA of the accompanying drawings,
`a plurality of conventional miniaturised sense amplifiers
`SAN, are driven by a conventional sense amplifier
`SA 1
`driving circuit. Each conventional sense amplifier, for
`example SA, comprises two P-MOS transistors connected to
`a
`common
`latch node L~, and
`two N-MOS
`transistors
`connected to a common latch node LAN. Bit lines BL1, BLR
`are connected to gate terminals of the corresponding N-MOS
`and P-MOS
`transistors.
`A plurality of
`the above
`arrangement forms the plurality of sense amplifiers SA1 -
`SAN.
`
`The conventional sense amplifier driving circuit
`comprises a P-MOS driving transistor Ql and an N-MOS
`driving transistor Q2, for driving the sense amplifiers.
`The P-MOS and N-MOS driving transistors are generally
`larger in physical channel size andjor current carrying
`capacity
`than
`the above described N-MOS or P-MOS
`transistors of the sense amplifiers. The P-MOS and N-MOS
`driving transistors are respectively connected to the
`latch nodes L~ and LAN,
`and are also respectively
`connected to an external voltage terminal supplying a
`supply voltage Vee and to a ground terminal at a ground
`potential Vss.
`Inverters INVl and INV2 are connected to
`the gate terminals of the MOS transistors Ql and Q2.
`
`During an active restore operation of an above
`described sense amplifier SA,
`if a
`row address strobe
`signal RAS goes to a
`low level, then an active restore
`enable signal ¢sr goes to a high level. The active restore
`is inverted to a
`enable signal ¢sp
`low
`level by
`the
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`Page 15 of 56
`
`

`
`-
`
`3 -
`
`inverter INVl, and is input to the gate terminal of the
`driving transistor Ql to turn on the transistor Q1. When
`the driving transistor Ql is turned on, a first driving
`signal having a voltage ¢U\ and a current Icc is present
`at the node ~·
`
`Similarly, during a sensing operation of the sense
`amplifier, if the row address strobe signal RAS goes to a
`low level, then a sense enable signal ¢sN goes to a
`low
`level, and is inverted to a high level by the inverter
`The inverted sense enable signal is input to the
`INV2.
`terminal of
`transistor Q2
`to turn on
`gate
`the
`the
`transistor Q2. When the transistor Q2 is turned on, a
`second driving signal having a voltage ¢LAN and a current
`Iss appears on the common latch node LAN.
`
`above mentioned conventional sense
`the
`in
`Thus,
`circuit,
`the sense amplifiers are
`amplifier driving
`on and turn off operations of the
`controlled by turn
`driving transistors Ql, Q2. However, when the driving
`transistors Ql and Q2 are turned on, sharply rising peak
`currents Iccr and Issr are genera ted in the respective
`driving signals at the common latch nodes ~ and LAN, and
`through transistors Ql and Q2
`respectively,
`thereby
`producing a large noise power. Furthermore, the voltages
`¢~, ¢LAN of
`the respective driving signals at the
`latch nodes ~, LAN of
`respective common
`the sense
`amplifiers vary markedly as shown
`in Figure 2 of the
`accompanying drawings, causing instability of the sense
`amplifiers.
`
`the stability of the sense
`improve
`In order to
`amplifiers,
`the conventional sense amplifier driving
`circuits can be arranged such that dual sensing strobes
`are provided by sequential operations of two or more
`
`5
`
`10
`
`15
`
`20
`
`2.5
`
`30
`
`3 5
`
`Page 16 of 56
`
`

`
`- 4 -
`
`transistors. However, since a large number of transistors
`have to be controlled in such a case, controlling the
`transistors becomes very complicated and difficult.
`
`the above described
`to overcome
`In an attempt
`disadvantages, in a second conventional sense amplifier
`driving circuit the large MOS driving transistors Ql and
`Q2 for driving the sense amplifiers SA1 to SAN are replaced
`by smaller MOS
`transistors which are connected to the
`respective sense amplifiers, this being illustrated in
`Figure lB of the accompanying drawings.
`
`The sense amplifier driving circuit illustrated in
`Figure lB is similar to that of Figure lA, except that in
`the circuit of Figure
`lB,
`a plurality of driving
`transistors Ql 1
`- QlN, Q2 1 - Q2N are respectively connected
`to the sense amplifiers SA 1
`That is to say, the
`SAN.
`-
`sense amplifier P-MOS driving transistors Ql 1
`- QlN and the
`sense amplifier N-MOS driving transistors Q2 1
`- Q2N are
`disposed in a distributed manner and are respectively
`connected between
`the common
`latch node ~ and
`the
`terminal at supply voltage vee, and between the common
`latch node LAN and the terminal at ground voltage Vss.
`
`the second sense amplifier driving
`in
`However,
`circuit, the latch nodes L~, LAN have increased parasitic
`capacitance and consequently sensing speed is reduced.
`Also, layout of the circuits becomes difficult.
`
`5
`
`10
`
`~5
`
`20
`
`25
`
`lB and 2 of the accompanying
`Referring to Figures
`drawings, upon
`a driving operation of
`the sense
`amplifiers, if the row address strobe signal RAS goes to
`a
`- QlN and
`low level, the P-MOS driving transistors Q1 1
`the N-MOS driving transistors Q2 1
`- Q2N are respectively
`turned on or off by the active restore enable signals ¢sp
`
`35
`
`Page 17 of 56
`
`

`
`-
`
`5 -
`
`and the sense enable signals ¢sNt as inverted by the
`inverters INV1 and INV2, thereby controlling operation of
`the sense amplifiers. Accordingly, upon driving the sense
`amplifiers, all of the driving transistors Q1 1 - QlN or all
`- Q2N are simultaneously
`of the driving transistors Q2 1
`turned on, producing suddenly increasing peak driving
`signal currents IccP and IssP and suddenly changing driving
`voltages ¢LAN, ¢~ at the latch nodes ~, LAN thereby
`reducing the stability of the sense amplifiers.
`
`As shown by the timing diagram of Figure 2 of the
`accompanying drawings, the peak values IccP and I ssP of the
`respective driving signal currents Icc and Iss are large,
`and steep variations of the driving signal voltages ¢U\
`and ¢LAN occur.
`
`Since the driving transistors are distributed within
`a memory cell array,
`a
`system of driving
`the sense
`amplifiers in which a driving signal which has a dual
`slope is used is difficult to adopt owing to difficulties
`in layout of the circuitry and an increase in chip area.
`
`As described above, the conventional sense amplifier
`driving circuits can have disadvantages such that during
`driving operations of
`the sense amplifiers,
`and
`particularly upon turning on the driving transistors, the
`peak current values Iccr and IssP of the respective driving
`signals are very large. Also variations in the voltages
`¢~ and ¢LAN of the driving signals are severe, and the
`sensing speed of the sense amplifiers becomes very slow
`due to an increase of parasitic capacitance at the latch
`nodes lJ\ and LAN. Layout of circuitry becomes difficult,
`and formation of a dual sensing slope of the driving
`signals also becomes difficult.
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`Page 18 of 56
`
`

`
`- 6 -
`
`Specific embodiments of the present invention are
`intended to address the above mentioned disadvantages of
`conventional circuits.
`
`According to one aspect of the present invention,
`there is provided a sense amplifier driving circuit for
`driving one or more sense amplifiers in a semiconductor
`device, the circuit including an active restore driving
`circuit having a first active current limiting means which
`comprises at least a first current mirror circuit and a
`first constant current source, wherein one or more restor
`driving transistors forming part of said first current
`mirror circuit are connected between said sense amplifiers
`and one or more power terminals, said active restore
`driving circuit being arranged to receive an active
`restore enable signal,
`to produce an active restore
`driving signal and to supply said active restor driving
`signal to said sense amplifier(s) by means of said restore
`driving transistor{s) 1 said active restore driving signal
`having a voltage which is controllable by said first
`active current
`limiting means so as
`to
`increase
`(or
`decrease) at a first rate.
`
`the circuit further comprises a sense
`Preferably 1
`driving circuit having a second active current limiting
`means comprising at least a second current mirror circuit
`and second constant current source, wherein one or more
`sense driving transistors forming part of said second
`current mirror circuit are connected between said sense
`amplifier(s} and one or more ground terminals, said sense
`driving circuit being arranged to receive a sense enable
`signal, to produce a sense driving signal and to supply
`said sense driving signal to said sense amplifier(s) by
`means of said sense driving transistor(s), said sense
`driving signal having a voltage which is controllable by
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`Page 19 of 56
`
`

`
`- 7 -
`
`limiting means so as
`said second active current
`increase (or decrease) at a second rate.
`
`to
`
`5
`
`The voltage of the active restore driving signal and
`the voltage of said sense driving signal may be
`controllable so as
`to
`increase
`(or decrease)
`in a
`substantially linear manner.
`
`Preferably, each sense amplifier comprises two P-MOS
`transistors and two N-MOS transistors.
`
`10
`
`said active restore driving circuit
`Preferably,
`further comprises a first inverter circuit for controlling
`operation of
`the first current mirror circuit
`in
`accordance with the active restore enable signal.
`
`Preferably, said sense driving circuit further
`comprises a
`second
`inverter circuit for controlling
`operation of
`the second current mirror circuit
`in
`accordance with the sense enable signal.
`
`said first constant current source and said second
`constant current source may each comprise an MOS
`transistor having a gate voltage supplied thereto which is
`of a predetermined
`level
`intermediate a power source
`voltage and a ground voltage.
`
`The active restore driving circuit may comprise:
`
`a comparator circuit for detecting a voltage of the
`sense amplifiers and for comparing the detected voltage
`with a reference voltage;
`
`15
`
`20
`
`25
`
`30
`
`a trigger circuit for providing a trigger signal in
`response to an output of the comparator circuit; and
`
`35
`
`Page 20 of 56
`
`

`
`-
`
`8 -
`
`a bias circuit including said first current mirror
`circuit and arranged to control a gate vel tage of the
`restore driving transistor(s)
`in accordance with
`the
`active restore enable signal so as to adjust a current
`flow through said restore driving transistor(s) and the
`voltage of said active restore driving signal, said bias
`circuit being activated in accordance with the trigger
`signal,
`
`whereby the active restore driving signal voltage is
`limited to a maximum internal voltage level, regardless of
`external voltage.
`
`5
`
`10
`
`The maximum internal voltage may be said reference
`voltage.
`
`15
`
`Said bias circuit may comprise:
`
`a plurality of P-MOS transistors arranged to form
`said first current mirror circuit;
`
`20
`
`an inverter circuit for controlling operation of the
`first current mirror circuit in accordance with the active
`restore enable signal, said inverter circuit including an
`N-MOS transistor; and
`
`25
`
`the first
`transistor which serves as
`an N-MOS
`constant current source for said first current mirror
`circuit said N-MOS
`transistor having a drain terminal
`30 which is connected to a source terminal of the N-MOS
`transistor of the inverter circuit, a source terminal
`which is connected to a ground terminal and being arranged
`to receive a bias voltage at a gate terminal thereof
`
`35
`
`Alternatively, said bias circuit may comprise:
`
`Page 21 of 56
`
`

`
`- 9 -
`
`an N-MOS transistor having gate and drain terminal's
`which are connected to the external voltage;
`
`5
`
`10
`
`a P-MOS transistor having a drain terminal which is
`connected to a source terminal of the N-MOS transistor, a
`gate terminal which is connected to a ground terminal and
`a source terminal which is connected to the gate terminal
`of said restore driving transistor(s),
`
`transistor
`transistor and said P-MOS
`said N-MOS
`forming said first current mirror circuit together with
`said restore driving transistor(s); and
`
`15
`
`the first
`transistor which serves as
`an N-MOS
`constant current source for said first current mirror
`circuit and which is arranged to receive a bias voltage at
`a gate terminal thereof and has a drain terminal which is
`connected to the source terminal of the N-MOS transistor
`of the inverter circuit, and having a source terminal
`20 which is connected to a ground terminal.
`
`The bias voltage is preferably a voltage intermediate
`said external voltage and a ground voltage.
`
`25
`
`Preferably, one or more gate voltages of said driving
`transistor is or are shifted to an intermediate level
`between the external voltage and a ground voltage during
`driving of said sense amplifiers.
`
`30
`
`The trigger circuit may comprise:
`
`a first P-MOS transistor having a drain terminal
`which is connected to the external voltage;
`
`Page 22 of 56
`
`

`
`- 10 -
`
`a first N-MOS transistor of which a gate terminal and
`a drain terminal are connected respectively to a gate
`terminal and a
`source
`terminal of said first P-MOS
`transistor;
`
`a second N-MOS transistor, a drain terminal of which
`is connected to the source terminal of said first N-MOS
`transistor and a source terminal of which is connected to
`a ground terminal;
`
`A NAND gate, one input terminal of which is connected
`to the source terminal of said first P-MOS transistor, and
`to the drain terminal of a said first N-MOS transistor,
`and another terminal of which receives an enable clock
`signal for enabling the sense amplifier driving circuit;
`and an inverter INV3 connected to the output terminal of
`said NAND gate.
`
`5
`
`10
`
`15
`
`The trigger circuit may comprise an inverter having
`a P-MOS transistor and an N-MOS transistor.
`
`20
`
`Said comparator circuit may comprise:
`
`a differential amplifying circuit consisting of two
`P-MOS transistor and two N-MOS transistors; and
`
`25
`
`to source
`a constant current source connected
`terminals of said N-MOS of said differential amplifying
`circuit said constant current source receiving a driving
`control clock;
`
`30
`
`said comparator circuit being capable of comparing a
`reference voltage input into a gate terminal of one of
`said N-MOS transistors and the voltage Vup (of the latch
`
`Page 23 of 56
`
`

`
`- 11 -
`
`node) input into a gate terminal of the other of said N(cid:173)
`MOS transistors.
`
`Preferably, the reference voltage and the detected
`voltage of said sense amplifier(s) are compared with each
`other upon an active restore operation, such that if the
`detected voltage is equal to or larger than the reference
`voltage, operation of
`the current mirror circuit is
`stopped to clamp the voltage of the active restore enable
`signal to a constant level.
`
`The internal reference voltage may be in the range 3
`to 5 volts, and preferably in the range 3.8 to 4.2 volts.
`
`Said active restore driving voltage is preferably
`arranged to increase (or decrease)
`in first and second
`stages such that in said first stage the increase (or
`decrease) occurs at said first rate and in said second
`stage, the increase (or decrease) occurs at a different
`rate. Said different rate may be higher than said first
`rate.
`
`Preferably, said active restore driving circuit is
`arranged to provide said active restore driving signal to
`the restore driving transistor{s) and said first current
`mirror circuit adjusts a current flow through the restore
`driving transistors in response to a first active restore
`signal and a third current mirror circuit is provided to
`adjust said current flow in response to a second active
`restore enable signal, whereby said first and
`third
`current mirror circuits are activated sequentially so that
`the active restore driving signal has a linear dual slope.
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`Page 24 of 56
`
`

`
`- 12 -
`
`through said first
`Preferably, a current flowing
`current mirror circuit is smaller than a current flowing
`through said third current mirror circuit.
`
`5
`
`the
`By way of example, specific embodiments of
`present invention will now be described with reference to
`Figures 3 to 10 of the accompanying drawings in which :-
`
`10
`
`15
`
`20
`
`25
`
`30
`
`Figure 3 is a circuit illustration of a first sense
`amplifier driving circuit according to a first specific
`embodiment of the present invention, and which may be used
`in a high density miniaturised semiconductor memory
`device;
`
`timing chart for driving signals
`is a
`Figure 4
`generated in the first sense amplifier driving circuit of
`Figure 3;
`
`Figure 5 is a schematic block diagram of a second
`sense amplifier driving circuit according to a second
`specific embodiment of the present invention,
`in which
`active restore signals are clamped;
`
`Figure 6 is a more detailed circuit illustration of
`the second sense amplifier driving circuit shown in Figure
`5;
`
`is a more detailed illustration of an
`Figure 7
`alternative sense amplifier driving circuit according to
`the second specific embodiment, which is similar to the
`circuit of Figure 6, but which is a modified version
`thereof;
`
`Page 25 of 56
`
`

`
`- 13 -
`
`Figure 8 is a timing chart showing signal waveforms
`for signals generated
`in
`the second sense amplifier
`driving circuit;
`
`Figure 9 shows a schematic circuit diagram of and a
`timing chart for a third sense amplifier driving circuit
`according to a third embodiment of the present invention,
`in which a dual slope is provided during an active restore
`operation; and
`
`Figure 10 shows a schematic circuit diagram of and a
`timing chart for a fourth sense amplifier driving circuit
`according
`to a
`further embodiment of
`the present
`invention, in which a dual sensing slope is provided in a
`sensing operation.
`
`Referring to Figures 3A and 3B of the accompanying
`drawings, the first sense amplifier driving circuit will
`now be described.
`
`The first sense amplifier driving circuit includes an
`active restore driving circuit 1, and a sense driving
`circuit 2.
`
`the active restore driving circuit
`In Figure 3A,
`includes a P-MOS driving transistor QlO and the sense
`driving circuit includes an N-MOS driving transistor Q20,
`which are respectively connected to latch nodes ~ and LAN
`of a number N of highly miniaturised sense amplifiers SA1 -
`SAN.
`
`In Figure 3B, a circuit similar to that of Figure 3A
`is shown, but
`instead of
`the active restore driving
`circuit having a single P-MOS driving transistor and the
`sense driving circuit having a single N-MOS driving
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`Page 26 of 56
`
`

`
`- 14 -
`
`the active restore
`in Figure JA,
`transistor as shown
`driving and sense driving circuit respectively include a
`- Q10N and a
`plurality of P-MOS driving transistors Ql0 1
`plurality of N-MOS driving transistors Q20 1
`- Q20N, which
`are divided amongst the number N of sense amplifiers. Each
`driving transistor Q10 1 - Q10n and Q20 1 - Q20n is connected
`in a distributed manner via
`latch nodes ~' LAN as
`appropriate
`to
`the N sense amplifiers SA 1
`SAN
`respectively.
`
`In the circuits of Figures JA and 3B each of the
`SAN consists of
`two P-MOS
`sense amplifiers SA 1
`transistors and two N-MOS transistors. The latch nodes
`~' LAN of the sense amplifiers are respectively connected
`to a first power supply terminal at a supply voltage Vee
`and to a second power supply terminal at a ground voltage
`vss through said P-MOS driving transistor Q10 and said N(cid:173)
`MOS driving transistor Q20 in the case of Figure JA, or
`through said P-MOS driving transistors Ql0 1 - QlON and said
`N-MOS driving transistors Q20 1 - Q20N in the case of Figure
`3B.
`
`the N-MOS
`The P-MOS driving transistor Q10 and
`driving transistor Q20 are each
`large sized driving
`transistors. By large sized it is meant that the driving
`transistors have channel dimensions and corresponding
`current carrying capabilities which are larger than the
`channel dimensions andfor corresponding current carrying
`capabilities of the transistors of the sense amplifiers,
`and which are sufficient to enable the driving transistors
`to carry enough current to and from the sense amplifiers
`to enable rapid operation thereof.
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`The active restore driving circuit comprises P-MOS
`- Ql0 11 ) , a P-MOS current adjusting
`transistors QlO (or Q10 1
`
`35
`
`Page 27 of 56
`
`

`
`- 15 -
`
`transistor Q12, an N-MOS
`a
`transistor Qll,
`P-MOS
`transistor Q13, and
`an N-MOS constant current source
`transistor Q14 as shown in Figure 3, and will now be
`described.
`
`The gate and source terminals of the P-MOS current
`adjusting
`transistor Qll are connected
`to
`the gate
`terminal of said P-MOS driving transistor QlO or to the
`gate terminals of said P-MOS driving transistors Q10 1
`-
`QlON as appropriate. Together with said P-MOS driving
`transistor QlO or said P-MOS driving transistors Q10 1
`-
`QlON, as appropriate, the current adjusting transistor Qll
`comprises a current mirror circuit for thereby adjusting
`the current flow through said driving transistor QlO (or
`- QlOn) during an active restore
`driving transistors Q10 1
`operation of the sense amplifiers.
`
`the current
`terminals of
`The gate and source
`adjusting transistor Qll are also connected to an output
`terminal of an inverter circuit consisting of the P-MOS
`transistor Q12 and the N-MOS transistor Q13, so that the
`above mentioned current mirror circuit operates
`in
`response to an active restore enable signal ¢sp applied to
`the gate of the transistors Ql2 and Q13.
`The source
`terminal of the N-MOS transistor Ql3 is connected to the
`N-MOS transistor Q14 which serves as a constant current
`source for the current mirror circuit and limits the
`current flowing through the current adjusting transistor
`Qll to a value which is substantially the same as the
`value of a constant current Ir flowing through the constant
`current source transistor Ql4.
`
`The constant current source transistor Q14 receives
`a bias voltage Vbias at its gate terminal, and its source
`terminal is connected to the second supply terminal at the
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`Page 28 of 56
`
`

`
`- 16 -
`
`The drain terminals of said P-MOS
`ground voltage Vss.
`transistors Qll, Q12, are connected to the first power
`supply terminal at the supply voltage Vee.
`
`The sense driving circuit comprises N-MOS driving
`transistors Q20 (or Q20 1 -Q200 ) , an N-MOS current adjusting
`transistor Q15,
`an N-MOS
`transistor Q16,
`a
`P-MOS
`transistor Q17,
`and a P-MOS constant current source
`transistor Q18 as shown in Figure 3, and will now be
`described.
`
`is
`The N-MOS current adjusting transistor Q15
`arranged with the driving transistor Q20 or the driving
`- Q20N as appropriate to form a second
`transistors Q20 1
`current mirror circuit, and has gate and source terminals
`which are connected to the gate terminals of the N-MOS
`- Q20N.
`The gate and source
`driving transistors Q20 1
`terminals of the transistor Ql5 are connected to a second
`inverter circuit consisting of the N-MOS transistor Q16
`and the P-MOS transistor Q17.
`
`The drain terminal of the P-MOS transistor Q17 is
`connected to the P-MOS transistor Q18 which serves as a
`constant current source for the second current mirror
`circuit. The gate terminal of the constant current source
`transistor Q18 is set to receive a bias voltage Vbias of
`an intermediate level between Vee and Vss, and the drain
`terminal of the constant current source transistor Ql8 is
`connected to the external power supply terminal Vee, while
`the source
`terminals of
`the N-MOS current adjusting
`transistor Q15, and the N-MOS transistor Q16 are each
`connected to the second supply terminal having a ground
`voltage Vss.
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`Page 29 of 56
`
`

`
`- 17 -
`
`the first sense
`An active restore operation of
`amplifier driving circuit will now be described.
`
`During an active restore operation of the sense
`amplifiers, if a row address strobe signal RAS goes to a
`low level so as to be in an active cycle, then an active
`restore enable signal ¢., which is input into the inverter
`is set to a high
`level.
`circuit,
`Thus,
`the P-MOS
`transistor Ql2 will be
`turned off, and
`the N-MOS
`transistor Ql3 will be turned on.
`Accordingly,
`the
`output of the inverter circuit is set to have a low level,
`resulting in the P-MOS current adjusting transistor Qll of
`the current mirror circuit being turned on and the driving
`transistors QlO, or Ql0 1 - QlON as appropriate, also being
`turned on.
`
`The constant current IP has a value which is limited
`by the constant current source transistor Q14. According
`to this specific ernobodiment, the bias voltage Vbias at
`the gate of the constant current source transistor Q14 has
`a value which is intermediate between Vee and Vss and
`which is proportional to Vee.
`
`Thus, a signal at node ~g is set to have a voltage
`¢LApg which
`is
`less
`than
`[Vcc-Vth], and which
`is
`intermediate between the high level and the low level, so
`that the driving transistors QlO or Q10 1-QlON will be
`slowly turned on (where Vth is the threshold voltage of
`the driving transistor).
`
`The driving transistors QlO or Ql0 1-QlON connected to
`the node L~ are arranged together with the P-MOS current
`adjusting transistor Qll
`to
`form
`the current mirror
`circuit, so that a current Icca of an active restore
`driving signal to the sense amplifiers SA which flows
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`Page 30 of 56
`
`

`
`- 18 -
`
`transistors Q10 or Ql0 1-QlON as
`the driving
`through
`appropriate, will be substantially proportional to the
`current IP flowing through the P-MOS current adjusting
`transistor Q11.
`Thus,
`the current Icca of the active
`restore driving signal to the sense amplifiers SA is
`controllably limited by the driving transistor QlO, the
`current adjusting transistor Q11, and the constant current
`source transistor Q14.
`
`Thus, during the active restore operations, the peak
`current IccaP of the active restore driving signal which
`flows
`- QlON as
`through the transistors Q10, or Q10 1
`appropriate,
`is limited by the action of the current
`mirror circuit so that it does not exceed a predetermined
`value which is determined by the constant current IP and
`- QlON.
`the sizes of the transistors Qll and Q10 or Q10 1
`The voltage <I>LA, of the active restore driving signal
`varies in a linear form, which is controlled by the value
`of current which flows through the driving transistor, and
`hence by the value of the constant current Ip which flows
`through
`the current adjusting transistor. Thus
`the
`stability of the sense amplifiers may be improved.
`
`5
`
`10
`
`15
`
`20
`
`A sensing operation of the first sense amplifier
`driving circuit will now be described.
`
`25
`
`30
`
`During a sensing operation of the sense amplifiers,
`the current Issa of a sense driving signal which flows
`- Q20N,
`is
`through the driving transistors Q20 or Q20 1
`adjusted by the N-MOS current adjusting transistor Q15
`which forms the second current mirror circuit together
`with said driving N-MOS transistors Q20 or Q20 1 - Q20N. The
`current Issa of
`the sense driving signal mirrors a
`constant current
`IN which
`flows
`through
`the current
`
`Page 31 of 56
`
`

`
`- 19 -
`
`adjusting transistor Q15 via the constant current source
`transistor Q18.
`
`the current
`termina

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