DEVECE
`
`YUAN WAUR
`
`TAK H. NINE
`
`CAMBRIDGE
`5; UNIVERSITY PRESS
`
`Page 1 of 122
`
`SAMSUNG EXHIBIT 1008
`
`

`
`PUBLISHED BY THE PRESS SYNDICATE OF THE UNIVERSITY OF CAMBRIDGE
`
`The Pitt Building, Trurnpington Street, Cambridge CB2 lRP, United Kingdom
`
`CAMBRIDGE UNIVERSITY PRESS
`
`http://www.cup.carn.ac.uk
`The Edinburgh Building, Cambridge CB2 2RU, UK
`40 West 20th Street, New York, NY 10011-4211, USA http://www.cup.org
`10 Stamford Road, Oakleigh, Melbourne 3166, Australia
`
`© Cambridge University Press 1998
`
`This book is in copyright. Subject to statutory exception
`and to the provisions of relevant collective licensing agreements,
`no reproduction of any part may take place without
`‘the Written permission of Cambridge University Press.
`
`First published 1998
`
`Printed in the United States of America
`
`Typeset in Times Roman 11/14 pt. and Eurostile in IATEX 25 [TB]
`
`A catalog record for this book is available from the British Library
`
`Library of Congress Cataloging-in~Publication Data
`
`Taur, Yuan, 1946-
`Fundamentals of modern VLSI devices / Yuan Tam‘, Tak H. Ning.
`p.
`cm.
`
`ISBN 0-521-55056-4. —ISBN 0-521-55959-6 (pbk.)
`1. Metal oxide semiconductors, Complementary.
`2. Bipolar
`transistors.
`3. Integrated circutis — Very large scale integration.
`1. Ning, Tak H..
`1943-
`.
`11. Title.
`TK7871.99.M44T38
`1998
`621.395 -— dc21
`
`98-16162
`CIP
`
`TSBN 0 521 55056 4 hardback
`
`ISBN 0 521 55959 6
`
`paperback
`
`Page 2 of 122
`
`

`
`INTRODUCTION
`
`,
`
`,x§»?‘5
`
`Since the invention of the bipolar transistor in 1947, there has been an unprece-
`dented growth of the semiconductor industry, with an enormous impact on the
`way people work and live. In the last twenty years or so, by far, the strongest
`
`growth area of the semiconductor industry has been in silicon very-large—scale—
`integration (VLSI) technology. The sustained growth in VLSI technology is fueled
`
`by the continued shrinking of transistors to ever smaller dimensions. The benefits of
`miniaturization —— higher packing densities, higher circuit speeds, and lower power
`dissipation —- have been key in the evolutionary progress leading to today’s com-
`
`puters and communication systems that offer superior performance, dramatically
`reduced cost per function, and much reduced physical size, in comparison with
`their predecessors. On the economic side, the integrated—circuit (IC) business has
`
`grown worldwide in sales from $1 billion in 1970 to $20 billion in 1984 and is
`projected to reach $185 billion in 1997. The electronics industry is now among the
`largest industries in terms of output as well as employment in many nations. The
`importance of microelectronics in the economic, social, and even political develop-
`ment throughout the world will no doubt continue to ascend. The large worldwide
`investment in VLSI technology constitutes a formidable driving force that will all
`but guarantee the continued progress in IC integration density and speed, for as
`long as physical principles will allow.
`
`’I.'I EVOLUTION OF VLSI
`DEVICE TECHNOLOGY
`
`An excellent account of the evolution of the metal—oxide—semiconductor field—effect
`
`transistor (MOSFET), from its initial concept to VLSI applications in the mid-
`1980s, can be found in the paper by Sah (Sah, 1988). Figure 1.1 gives a chronology
`of the major milestone events i11 the development of VLSI technology. The bipolar
`transistor technology was developed early on and was applied to the first integrated-
`circuit memory in mainframe computers in the 1960s. Bipolar transistors have been
`used all along where raw circuit speed is most important, for bipolar circuits remain
`the fastest at the individual—circuit level. However, the large power dissipation of
`
`Page 3 of 122
`
`

`
`"V
`
`1.
`
`INTRODUCTION
`
`First bipolar
`transistor
`(I 947)
`
`One-transistor
`DRAM cell
`invented
`(1968)
`
`First
`MOSFET
`( J 960)
`
`1C
`invcntcd
`(1958)
`
`First micro-
`processor
`(1971)
`
`.
`
`'
`
`-
`
`a
`
`-
`
`a
`
`'
`
`'
`
`7
`
`.
`
`.’
`
`-
`
`%
`
`power dissipation, engineers have been ab
`le to integrate hundreds of millions of
`CMOS transistors on a single chip and still
`have the chip readily air—coolablc. Until
`recently, the integration level of CMOS was not li
`mited by chip—level power dis-
`sipation, but by chip fabrication technology. Anoth
`er advantage of CMOS circuits
`
`Page 4 of 122
`
`

`
`EVOLUTION OF VLSI DEVICE TECHNOLOGY
`1|/I
`
`
`comes from the ratioless, full rail~to—rail logic swing, which improves the noise
`margin and makes a CMOS chip easier to design.
`As linear dimensions reached the 0.5-um level in the early 1990s, the perfor-
`mance advantage of bipolar transistors was outweighed by the significantly greater
`circuit density of CMOS devices. The system performance benefit of integrated
`functionality superseded that of raw transistor performance, and practically all the
`VLSI chips in production today are based on CMOS technology. Bipolar transistors
`are used only where raw circuit speed makes an important difference. Consequently,
`bipolar transistors are usually used in smal1—size bipolar—only chips, or in so-called
`BiCMOS chips where most of the functions are implemented using CMOS transis-
`tors and only a relatively small number are implemented using bipolar transistors.
`Advances in lithography and etching technologies have enabled the industry
`to scale down transistors in physical dimensions, and to pack more transistors
`in the same chip area. Such progress, combined with a steady growth in chip
`size, resulted in an exponential growth in the number of transistors and mem-
`ory bits pcr chip. The recent trends and future projections in these areas are
`illustrated in Fig. 1.2. Dynamic random-access memories (DRAMS) have char-
`acteristically contained the highest component count of any IC chips. This has
`been so because of the small size of the onc—transistor memory cell (Dennard,
`
`1968) and because of the large a11d often insatiable demand for more memory in
`computing systems. It is interesting to note that the entire content of this book can be
`stored in one 64—Mb DRAM chip, which is in volume production in 1997 and has
`a11 area equivalent to a square of about l.2 X 1.2 cm2.
`One remarkable feature of silicon devices that fuels the rapid growth of the
`
`information technology industry is that their speed increases and their cost decreases
`
`1E+l0
`
`1E+9
`
`1E+8
`
`,_ 3+7
`
`lE+6
`
`l E+5
`
`lE+4
`
`
`
`Numberoftransistorsperchip
`
`
`
`
`
`Minimumfeaturesize(um)
`
`lE+3
`1970
`
`‘
`
`‘
`1980
`
`*
`
`1990
`Ycar
`
`‘
`2000
`
`FIGURE 1.2. Trends in lithographic feature size, and number of transistors per
`chip for DRAM and microprocessor chips.
`
`Page 5 of 122
`
`

`
`‘I.
`
`INTRODUCTION
`
`as their size is reduced. The transistors manufactured today are 20 times faster and
`occupy less than 1% of the area of those built 20 years ago. This is illustrated in
`the trend of microprocessor units (MPUs) in Fig. 1.2. The increase in the clock
`frequency of microprocessors is the result of a combination of improvements in
`microprocessor architecture and improvements in transistor speed.
`
`1.2 |\/IODEFIN VLSI DEVICES
`
`It is clear from Fig. l .2 that modern transistors of practical interesthave feature sizes
`of 0.5 um and smaller. Although the basic operation principles of large and small
`
`transistors are the same, the relative importance of the Various device parameters and
`performance factors for the small—dimension modern transistors is quite different
`from that for the transistors of the early 1980s or earlier. It is our intention to focus
`our discussion in this book on the fundamentals of silicon devices of sub—0.5—um
`generations.
`
`1.2.1 MODERN CMOS TRANSISTORS
`
`A schematic cross section of modern CMOS transistors, consisting of an n—channel
`
`MOSFET and a p—channel MOSFET integrated on the same chip, is shown in
`Fig. 1.3. A generic process flow for fabricating the CMOS transistors is outlined
`
`in Appendix 1. The key physical features of the modern CMOS technology, as
`illustrated in Fig. 1.3, include: p-type polysilicon gate for the p-channel MOSFET
`and n—type polysilicon gate for the n—channel MOSFET, refractory metal silicide
`on the polysilicon gate as well as on the source and drain diffusion regions, and
`shallow—trench oxide isolation.
`
`In the electrical design of the modern CMOS transistor, the power—supply Voltage
`is reduced with the physical dimensions in some coordinated manner. A great deal
`of design detail goes into determining the channel length, or separation between
`the source and drain, accurately, maximizing the on current of the transistor while
`
`nMOSFET
`
`pMOSFET
`
`Oxide spacer
`
`p-type substrate
`
`FIGURE 1.3. Schematic device cross section for an advanced CMOS technology.
`
`Page 6 of 122
`
`

`
`’| ,3 SCOPE AND BRIEF DESCRIPTION OF THE BOOK
`
`B
`
`E
`
`C I
`
`p+ polysilicon
`
`11+ polysilicon
`p+ polysilicon
`
` W
`\w;\x‘ -Q
`'‘
`
`7
`
`n+ subcollector
`
`Polysilicomfilled
`deep trench isolation
`
`FIGURE 1.4. Schematic cross section of a modern n—p—n
`bipolar transistor.
`
`maintaining an adequately low off current, minimizing variation of the transistor
`characteristics with process tolerances, and minimizing the parasitic resistances
`and parasitic capacitances.
`
`1.2.2 MODERN BIPOLAR TRANSISTORS
`
`The schematic cross section of a modern silicon bipolar transistor is shown in
`Fig. 1.4. The process outline for fabricating this transistor is shown in Appendix 2.
`The salient features of this transistor include: shallow—trench field oxide and deep-
`trench isolation, polysilicon emittcr, polysilicon base contact which is sclf—aligned
`to the emitter contact, and a pedestal collector which is doped to the desired level
`only directly underneath the emitter.
`Unlike CMOS, the power—supply voltage for a bipolar transistor is usually kept
`constant as the transistor physical dimensions are reduced. Without the ability to
`reduce the operating Voltage, electrical breakdown is a severe concern in the design
`of modern bipolar transistors. In designing a modern bipolar transistor, 21 lot of
`effort is spent tailoring the doping profile of the various device regions in order to
`maintain adequate breakdown—vo1tage margins while maximizing the device per-
`formance. At the same time, unlike the bipolar transistors before the early 1980s
`when the device performance was mostly limited by the device physical dimensions
`practical at the time, a modern bipolar transistor often has its performance limited
`by its current—density capability and not by its physical dimensions. Attempts to
`improve the current—density capability of a transistor usually lead to reduced break-
`down Voltages.
`
`1.3 SCOPE AND BRIEF DESCFIIPTICJN
`OF THE BOOK
`
`In writing this book, it is our goal to address the factors governing the perfor-
`mance of modern VLSI devices in depth. This is carried out by first discussing the
`
`Page 7 of 122
`
`

`
`Page 8 of 122
`
`Page 8 of 122
`
`

`
`1.3 SCOPE AND BRIEF DESCRIPTION OF THE BOOK
`
`understanding the more important but more complex short—channel MOSFETS,
`
`which have lower capacitances and carry higher currents per gate voltage swing.
`The second part of Chapter 3 covers the specific features of s11ort—channe1
`MOSFETS important for device design purposes. The subsections include short-
`channel effects, velocity saturation and overshoot, channel—length modulation, and
`source—drain series resistance.
`
`CHAPTER 4: CMOS DEVICE DESIGN
`
`Chapter 4 considers the major device design issues in a CMOS technology. It begins
`with the concept of MOSFET scaling — the most important guiding principle for
`achieving density, speed, and power improvements in VLSI evolution. Several non-
`
`scaling factors are addressed, notably, the thermal voltage and the silicon bandgap,
`which have significant implications on the deviation of the CMOS evolution path
`from ideal scaling. Two key CMOS device design parameters — threshold voltage
`and channel length — are then discussed in detail. Subsections on threshold voltage
`include off-current requirement, nonuniform channel doping, gate work—function
`effects, channel profile design, and quantum—mechanical and discrete dopant effects
`on threshold voltage. Subsections on channel length include the definition of effec-
`tive channel length, its extraction by the conventional method and the shift—and—ratio
`method, and the physical interpretation of effective channel length.
`
`CHAPTER 5: CMOS PERFORMANCE FACTORS
`
`Chapter 5 examines the key factors that govern the switching performance and
`power dissipation of basic digital CMOS circuits which form the building blocks
`of a VLSI chip. Starting with a brief description of static CMOS logic gates and their
`layout, we examine the parasitic resistances and capacitances that may adversely
`affect the delay of a CMOS circuit. These include source and drain series resistance,
`
`junction capacitance, overlap capacitance, gate resistance,‘ and interconnect capac—
`itance and resistance. Next, we formulate a delay equation and use it to study the
`sensitivity of CMOS delay performance to a variety of device and circuit parameters
`such as wire loading, device width and length, gate oxide thickness, power-supply
`voltage, threshold voltage, parasitic components, and substrate sensitivity in stacked
`circuits. The last section of Chapter 5 further extends the delay equation to project
`the performance factors of several advanced CMOS materials and device structures.
`
`These include SOI CMOS, high~mobility Si—SiGe CMOS, and low—temperature
`CMOS. The unique advantage of each approach is discussed in depth.
`
`CHAPTER 6: BIPOLAR DEVICES
`
`The basic components of a bipolar transistor are described in Chapter 6. The discus-
`sion is based entirely on the vertical n—p—n transistor, since practically all high-speed
`
`Page 9 of 122
`
`

`
`Page 10 of 122
`
`Page 10 of 122
`
`

`
`The metal—oxide—semiconductor field—effect transistor (MOSFET) is the building
`
`block of VLSI circuits in microprocessors and dynamic memories. Because the
`current in a MOSFET is transported predominantly by carriers of one polarity only
`(e. g., electrons in an n—channel device), the MOSFET is usually referred to as a
`unipolar or majority~carrier device. Throughout this chapter, n—channel MOSFETS
`are used as an example to illustrate device operation and derive drain—current equa-
`tions. The results can easily be extended to p—channel MOSFETS by exchanging
`
`the dopant types and reversing the voltage polarities.
`The basic structure of a MOSFET is shown in Fig. 3.1. It is a four—terrninal
`
`device with the terminals designated as gate (subscript g), source (subscript s),
`
`E;Y-
`;
`
`%9
`
`drain (subscript d), and substrate or body (subscript 17). An n—channel MOSFET,
`or nl\/IOSFET, consists of a p—type silicon substrate into which two n+ regions,
`the source and the drain, are formed (e.g., by ion implantation). The gate elec-
`
`trode is usually made of metal or heavily doped polysilicon and is separated
`
`from the substrate by a thin silicon dioxide film, the gate oxide. The gate oxide
`is usually formed by thermal oxidation of silicon. In VLSI circuits, a MOSFET
`
`is surrounded by a thick oxide called the field oxide to isolate it from the ad-
`
`jacent devices. The surface region under the gate oxide between the source and
`drain is called the channel region and is critical for current conduction in a MOS— 4
`FET. The basic operation of a MOSFET device can be easily understood from
`the MOS capacitor discussed in Section 2.3. When there is no voltage applied
`to the gate or when the gate Voltage is zero, the p—type silicon surface is either
`in accumulation or in depletion and there is no current flow between the source
`
`and drain. The MOSFET device acts like two back—to—back p—n junction diodes
`
`with only low~level leakage currents present. When a sufficiently large positive
`
`voltage is applied to the gate, the silicon surface is inverted to n—type, which
`forms a conducting channel between the n+ source and drain. If there is a volt-
`age difference between them, an electron current will flow from the source to
`the drain. A MOSFET device therefore operates like a switch ideally suited for
`digital circuits. Since the gate electrode is electrically insulated from the sub-
`strate, there is effectively no dc gate current, and the channel is capacitively
`
`Page 11 of 122
`
`

`
`3.1
`
`lLDN3—CHANNEl_ MSFET3
`
`Source (S)
`
`p—type silicon substrate (b)
`
`. —Vbs
`
`FIGURE 3.1. Three—diInensiona1 View of basic MOSFET device structure. (After Arora, 1993.)
`
`coupled to the gate via the electric field in the oxide (hence the name field—efi‘ect
`transistor).
`
`3. ‘I LDNG—CHANNEL |\/IDSFETS‘
`
`This section describes the basic characteristics of a long—channel MOSFET, which
`will serve as the foundation for understanding the more important but more comp-
`lex short—channel MOSFETS in Section 3.2. First, a general MOSFET current
`model based on the gradual channel approximation (GCA) is formulated in
`Section 3.1.1. The GCA is Valid for most regions of MOSFET operation except
`beyond the pinch-off or saturation point. A charge—sheet approximation is then in-
`troduced in Section 3.1.2 to obtain analytical expressions for the source—drain cur-
`rent in the linear and saturation regions. Current characteristics in the subthreshold
`region are discussed in Section 3.1.3. Section 3.1.4 addresses the threshold—Voltage
`dependence on substrate bias and temperature. Section 3.1.5 presents an empiri-
`cal model for electron and hole mobilities in a MOSFET channel. Lastly, intrinsic
`MOSFET capacitances and inVersion—1ayer capacitance effects (neglected in the
`charge sheet approximation) are covered in Section 3.1.6.
`
`Page 12 of 122
`
`

`
`FIGURE 3.2. A schematic MOSFET
`cross section, showing the axes of coor-
`dinates and the bias Voltages at the four
`terminals for the drain—cu1rent model.
`
`channel
`
`p-type substrate
`
`general drain-current model for a long—channel
`simplified using a charge—sheez‘ approximation
`an analytical expression for the source—drain
`current. Figure 3.2 shows the schematic cross section of a11 n—ehannel MOSFET
`in which the source is the n+ region on the left, and the drain is the n+ region on
`
`tween the
`coordinate system consistent with Section 2.3
`on MOS capacitors, namely, the x-axis is perpendicular to the gate electrode and
`is pointing into the p-type substrate with x = 0 at the silicon surface. The y—aXis
`‘
`direction, with y
`
`field oxide.
`
`Conventionally, the source Voltage is defined as t
`voltage is Vds, the gate Voltage is
`Initially, we assume Vbs = 0, ie,
`
`is the electron quasi—Fermi potential
`to the Fermi potential of the n+
`
`Page 13 of 122
`
`

`
`3.1 LNG-Gl=.ANNEl.. MUSFETS
`
`and the substrate, the Fermi potential of the source is the same as that of the bulk
`
`substrate. Therefore, in terms of the channel=to-substrate diode, V(y) plays the
`
`same role as the reverse bias V1; in Section 2.3.5 on MOS capacitors under
`
`nonequilibrium. As was discussed in Section 2.2.3, the quasi—Ferrni potential stays
`
`essentially constant across the depletion region, i.e.,V(y) does not change with
`x in the direction perpendicular to the surface. At the drain end of the channel,
`
`V0’ = L) = Vols-
`
`3.’i.1.’l
`
`INVERSION CHARGE DENSITY AS A FUNCTION
`
`OF QUASLFERMI POTENTIAL
`
`From Eq. (2.150) and Eq. (2.187), the electron concentration at any point (x, y) is
`given by
`
`n?
`_
`n(x, y) = Z—v‘—e4<t W”.
`a
`
`(3.1)
`
`Following the same approach as in Section 2.3.2, one obtains an expression for the
`
`electric field similar to that of Eq. (2.153):
`
`dx
`
`a’2(x, y) = (fly = 2kTN” [(5
`"'2
`— V/kT
`+ K/_l:?'<€
`q
`
`8sz'
`
`kT
`
`+ Q -1)
`41”
`1///kT
`—
`— E .
`
`(eq
`
`(3.2)
`
`The condition for surface inversion, Eq. (2.190), becomes
`
`11/(OJ) = V0’) + 2103,
`
`(3-3)
`
`which is a function of y. From Eq. (2.191), the maximum depletion layer Width is
`
`_ 25si[V(y) + ZWB]
`Wdm(}’) - ————fi :
`Q a
`
`(3-4)
`
`which is also a function of y.
`
`3.1 .1 .2 GFIADUALCHANNEL APPROXIMATION
`
`One of the key assumptions in any 1-D MOSFET model is the gradual channel
`approximation (GCA), which assumes that the variation ofthe electricfield in the
`y-direction (along the channel) is much less than the corresponding variation in
`
`the x-direction (perpendicular to the channel) (Pao and Sah, 1966). This allows us
`
`to reduce Poisson’s equation to the 1-D form (x—component only) as in Eq. (2.147).
`
`The GCA is Valid for most of the channel regions except beyond the pinch-ofi‘ point,
`
`Page 14 of 122
`
`

`
`3. MOSFET DEVICES
`
`which will be discussed later. One further assumes that both the hole current and the
`
`generation and recombination current are negligible, so that the current continuity
`equation can be applied to the electron current in the y—direction. In other words,
`the total drain—to—source current I45 is the same at any point along the channel. From
`
`Eq. (2.45), the electron current density at a point (x, y) is
`
`3.1
`_——....
`
`Curr
`
`drair
`
`'In(-X9
`
`: —q:u’nn(-xv
`
`dV(y)
`
`(3.5)
`
`31.
`
`Ana?
`
`of(1,(
`
`where n(x, y) is the electron density, and pm is the electron mobility in the channel.
`The carrier mobility in the channel is generally much lower than the mobility in
`the bulk, due to additional surface scattering mechanisms, as will be addressed in
`
`Section 3.1.5. With V(y) defined as the quasi—Fermi potential, i. e., playing the role
`of Q5” in Eq. (2.45), Eq. (3.5) includes both the drift and diffusion currents. The
`total current at a point y along the channel is obtained by multiplying Eq. (3.5)
`with the channel width W and integrating over the depth of the inversion layer. The
`
`integration is carried out from x = O to xi, the bottom of the inversion layer where
`
`W=‘/’BI
`
`Ids(y> = qW A
`
`dV
`Mnn(x, y)—— dic-
`dy
`
`(3.6)
`
`There is a sign change, as we define Ids > 0 to be the drain—to—source current in
`the —y direction. Since V is a function of )2 only, dV/dy can be taken outside
`the integral. We also assume that /Ln can be taken outside the integral by defining
`an efiective mobility, uefic, at some average gate and drain fields. What remains in
`the integral is the electron concentration, n(x, y). Its integration over the inversion
`
`layer gives the inversion charge per unit gate area, Q1-:
`
`Q,:(y)= ~61
`
`Y2
`
`0
`
`n(x,y)dx-
`
`Equation (3.6) then becomes
`
`dV
`dV
`Id_v(y) = _//vefi”W:1,;Qi(y) = “MefiW;Z3)‘Qi(V)-
`
`(3-7)
`
`(3-8)
`
`In the last step, Q ,- is expressed as a function of V; V is interchangeable with y,
`since V is a function of y only. Multiplying both sides of Eq. (3.8) by dy and
`
`integrating from O to L (source to drain) yield
`
`L
`
`Vds
`
`/ Lad)‘ = /WW f [-9,-<1/>1 dv.
`
`0
`
`0
`
`(3.9)
`
`Page 15 of 122
`
`

`
`lLUll\lG—13~=iANNEl.lV1SFETs
`
`Current continuity requires that Ids be a constant, independent of y. Therefore, the
`drain—to—source current is
`
`VHS
`
`V
`
`1...: 11.1% /0
`
`[—Q.-(V)]dV.
`
`(3.10)
`
`3.1.3.3 PAD AND SAH’S DOUBLE INTEGRAL
`
`An alternative form of Q,-(V) can be derived if n(x, y) is expressed as a function
`
`of (1#, V) using Eq. (3.1), i.e.,
`
`2
`
`n<x, y) = net. V) = ]':,—‘e4<*”*V>/kT,
`
`(1
`
`(3.11)
`
`and substituted into Eq. (3.7):
`
`1/(B
`
`Q;-(V) = —q f not. v>:~;— dw
`
`W: (mi?/Na)eq(1lfeV)/kT
`~ *9 W
`
`W.
`
`Here, tlrs is the surface potential at x = O and %’(i/r, V) = —d1,///dx is given by the
`
`square root of Eq. (3.2). Substituting Eq. (3.12) into Eq. (3.10) yields
`
`W V...
`
`Ids = qrueficffl
`
`W
`
`w. H; Na ego./»—V>/kr
`
` :_ dV-
`
`50% V)
`
`This is referred to as Pao and Sah’s double integral (Pao and Sah, 1966). The
`boundary Value 1//S is determined by two coupled equations: Eq. (2.180) and QS =
`-85,-%S(wS) or Gauss’s law, where %s(i[rs) is obtained by letting Tfl = 1m in Eq. (3.2).
`
`In inversion, only two of the terms in Eq. (3.2) are significant and need to be kept.
`
`The merged equation is then
`
`n=m+m—
`
`Qs
`
`Cox
`
`em
`
`I
`
`4/28sikTNa [(1% £2eq(¢,s_V)/k7]
`Cox
`kT + N;
`
`1/2
`
`5
`
`which is an implicit equation for §lrs(V). Equations (3.14) and (3.13) can only be
`
`solved numerically.
`
`3.1.2 MDSFET I-VGHARACTERISTICS
`
`In this subsection, we derive the basic expressions for long—channel current in the
`
`linear and saturation regions.
`
`.
`
`i3’:V.
`4.
`
`1.
`
`5
`
`é5
`
`.,
`E
`
`,5
`
`ié
`
`3
`
`E
`g,
`E,
`
`g
`
`E
`
`.
`
`.
`
`_.
`
`,
`
`Page 16 of 122
`
`

`
`3. MDSFET DEVICES
`
`3.1.2.1 CHARGE—SHEET APPRDXIMATIUN
`
`In order to derive an analytical solution for the drain current, we simplify the
`general model using the charge—sheet approximation (Brews, 1978) in which the
`inversion—1ayer thickness is treated as zero. It assumes that all the inversion charges
`are located at the silicon surface like a sheet ofcharge and that there is no poten-
`tial drop or band bending across the inversion layer. Furthermore, the depletion
`approximation is applied to the bulk depletion region. After the onset of inversion,
`the surface potential is pinned at llfs = 2103 + V(y), as indicated by Eq. (3.3). From
`Eq. (3.4), the bulk depletion charge density is
`
`Qd % _qNaVVdm = —\/2<9siqNa(2WB + V).
`
`(3.15)
`
`The total charge density in the silicon is given by Eq. (2.180),
`
`Qs = —C0x(Vg '" Vfl7 " ‘#5) : ”“C0x(Vg " Vfb "‘ ZWB _
`
`The inversion charge density is then the difference of the above two equations,
`
`Q1’ = Qs H Qd
`
`(3-17)
`
`: _Cox(Vg _ Vfll _ 2‘/(B _ V) + V 28siqNa(2‘#B +
`
`Substituting Eq. (3.17) into Eq. (3.10) and carrying out the integration, we obtain
`the drain current as a function of the gate and drain voltages:
`
`.
`
`W
`
`V
`
`2
`
`Vds
`Ids : Meflcoxir [(Vg _ Vfh _ 21.33 ’“
`[(2% + Vds)3/2 ~ (zest/2]].
`
`2/(/28S,~qNa
`
`3C0):
`
`Equation (3 . 18) represents the basic 1 eV Characteristics of a MOSFET device based
`on the charge—sheet model. It indicates that, for a given Vg, the drain current Id,
`first increases linearly with the drain Voltage Vds (called the linear or triode region),
`then gradually levels off to a saturated value (saturation region). These two distinct
`regions are further examined below.
`
`3.1.2.2 CHARACTERISTICS 1N THE LINEAR [TRlDDE} RETGIUN
`
`V\7hen Vds is small, one can expand Eq. (3.18) into a power series in V4, and keep
`
`only the lowest—order (first—order) terms:
`
`
`
`
`
`log(41,)(arbitraryscale)
`
`Ids : /Jiefi’Cox L (Vg
`
`W17
`
`ZWB
`
`W
`: /LefiC0xf(Vg _ Vt)‘/ds»
`
`V 45si5lNa‘/f8 > Vd
`
`C...
`
`S
`
`(3.19)
`
`Page 17 of 122
`
`

`
`3/1
`
`ILDNGGHANNEL MDSFETS
`
`where V; is the threshold voltage given by
`
`Vt = Vfl; + QWB +
`
`V 48sz'q No We
`
`Cox
`
`(3.20)
`
`.4.W.m;msgm«wtswimvsazszvgamasvrmmwwevzteaamit
`
`Comparing this equation with Eq. (2.175) and Eq. (2.180), one can see that V, is
`
`simply the gate voltage when the surface potential or band bending reaches 27,l:B
`and the silicon charge (the square root) is equal to the bulk depletion charge
`
`for that potential. As a reminder, 2wB : (2kT/q) ln(Na/n,-), which is typi-
`
`cally 0.6-0.9 V. When Vg is below V}, there is Very little current flow and the
`MOSFET is said to be in the sttbthreshold region, to be discussed in Section 3.1.3.
`
`Equation (3.19) indicates that, in the linear region, the MOSFET simply acts like
`
`a resistor with a sheet resistivity, cps}, = 1/[;teffC0x(Vg — Vt)], modulated by the
`gate voltage. The threshold voltage V, can be determined by plotting Ids Versus
`
`V3 at low drain voltages, as shown in Fig. 3.3. The extrapolated intercept of the
`linear portion of the [ds(Vg) curve with the Vg—axis gives the approximate Value
`of V,. In reality, such a linearly extrapolated threshold voltage (Von) is slightly
`
`higher than the “Z1//3” Vt due to inVersion—layer capacitance and other effects, as
`
`will be addressed in Section 3.1.6. Notice that the IdS(Vg) curve is not linear near
`the threshold Voltage. This is because the charge—sheet approximation, on which
`
`Eq. (3.19) is based, is no longer Valid in that regime. L0w—drain [dS(Vg) curves are
`also used to extract the eflective channel length of a MOSFET, as will be discussed in
`
`Chapter 4.
`
`1E+0
`
`1E-2
`
`1E—4
`
`
`
`
`
`LinearIds(arbitraryscale)
`
`
`
`
`
`log(Ids)(arbitraryscale)
`
`I
`1
`
`1
`1.5
`
`I
`2
`
`Gate Voltage Vg (V)
`Von“ Vt
`
`FIGURE 3.3. Typical MOSFET Id,—Vg characteristics at low drain bias
`Voltages. The same current is plotted on both linear and logarithmic scales.
`The dotted line illustrates the determination of the linearly extrapolated
`threshold Voltage, Van.
`
`Page 18 of 122
`
`

`
`3. MCSFET DEVICES
`
`3.1
`
`LI
`
`7
`
`saturati
`strate d
`througl
`is valid
`
`Of Vds.
`
`3.1.2.-
`Thesat‘
`Eq.(3.Z
`power:
`
`3.1.2.3 CHARACTERISTICS IN THE SATURATION REGION
`
`For larger values of Vds, the second—order terms in the power series expansion of
`Eq. (3.18) are also important and must be kept. A good approximation to the drain
`current is then
`
`W
`
`Ids : Meficoxf ((Vg _ Vt)Vds "
`
`m=l+
`
`_..__? : 1 + Cdm _
`COX
`COX
`
`'
`
`(322)
`.
`
`is the b0dy—efi’ecr coefiicient. Here m typically lies between 1.1 and 1.4 and is
`related to the body eflect to be discussed in Section 3.1.4. Equation (322) shows
`several alternative expressions for m. The one in terms of the capacitance
`ratio follows from ‘Eq. (2.174), where Cd,” is the bulk depletion capacitance at
`ws = Zwg. Alternatively, m can be expressed in terms of a thickness ratio, since
`Cdm : 8S,'/ Wdmv, Cox = so,,/ tax, and ssi/sax W 3. The threshold voltage, given by
`Eq. (3.20), can be expressed in terms of m as V, = Vfl, + (2m — l)2wB. As Vds
`increases, Ids follows a parabolic curve, as shown in Fig. 3.4, until a maximum or
`saturation value is reached. This occurs when Vds = Vdm = (Vg — V,)/ m, at which
`
`W (V — V)’
`Ids = Idsat : /Jdefi‘ C0x”Z -
`
`(3.23)
`
`Equation (3.23)
`
`reduces to the well—known expression for
`
`the MOSFET
`
`(Vdsat: law) 3,
`
`Vg4
`
`
`
`Draincurrent
`
`Drain voltage
`
`w
`
`FIGURE 3.4. Long—channe1 MOSFET IdS—VdS characteristics (solid
`curves) for several different values of Vg. The dashed curve shows the
`trajectory of drain voltage beyond which the current saturates. The dot-
`ted curves help to illustrate the parabolic behavior of the characteristics
`before saturation.
`
`Page 19 of 122
`
`

`
`gE\/flcggg
`
`3.’l LNG-CHANNEL TVISFETS
`§=?
`
`nsion of
`he drain
`
`(3.21)
`
`(322)
`
`4 and is
`'1) shows
`
`acitance
`tance at
`'10, since
`given by
`. As Vds
`imum 01’
`at which
`
`(323)
`
`[QSFET
`
`saturation current when the bulk depletion charge is neglected (valid for low sub-
`strate doping) so m = 1. The dashed curve in Fig. 3.4 shows the trajectory of V45,”
`through the various IdS—VdS curves for different Vg. Equation (3.21), or Eq. (3.18),
`is valid only for V4, 5 Vlgm. Beyond Vdm, I4, stays constant at Idm, independent
`0f Vds.
`
`3.1.2.4 THE ONSET OF PINCH-OFF AND CURRENT SATURATION
`
`The saturation of drain current can be understood from the inversion charge density,
`Eq. (3.17). For V 5 21//B, one can expand the square—root term of Eq. (3.17) into a
`power series in V and keep only the two lowest terms,
`
`;
`
`T
`a
`1
`3
`
`Q.~(V) = —C0,,(vg — V, — mV).
`
`‘
`
`(3.24)
`
`Q,-(V) is plotted in Fig. 3.5. Equation (3.10) states that the drain current is propor-
`tional to the area under the — Q i(V) curve between V = 0 and V4,. When Vds is
`small (linear region), the inversion charge density at the drain end of the channel
`is only slightly lower than that at the source end. As the drain voltage increases
`(for a fixed gate voltage), the current increases, but the inversion charge density at
`the drain decreases until finally it goes to zero when Vds = Vdmt = (Vg —— Vt)/m.
`At this point, Ids reaches its maximum value. In other words, the surface channel
`vanishes at the drain end of the channel when saturation occurs. This is called
`pinch—0fi” and is illustrated in Fig. 3.6. When Vds increases beyond saturation, the
`pinch-off point moves toward the source, but the drain current remains essentially
`the same. This is because for Vds > Vdm, the voltage at the pinch—off point remains
`
`0
`Source
`
`’
`
`Vds
`Drain
`
`Vdmi
`_ V: T V.
`m
`
`FIGURE 3.5. Inversion charge density as a function of the
`quasi-Fermi potential of a point in the channel. Before sat-
`uration, the drain current is proportional to the shaded area
`integrated from zero to the drain voltage.
`
`Page 20 of 122
`
`

`
`3. MOSFET DEVICES
`
`Depletion region
`
`_Vb:
`
`flu!
`
`FIGURE 3.6. (a) MOSFET operated in the linear region (low drain Voltage).
`(b) MOSFET operated at the onset of saturation. The pinch-off point is indicated
`by Y. (C) MOSFET operated beyond saturation Where Lhe channel length is reduced
`to L’. (After Sze, 1981.)
`
`Page 21 of 122
`
`

`
`3/l LONGCHANNEIL MDSFETS
`
`at Vdsat and the current, given by
`
`L’
`
`fo 1d.dy=u.fiWf0
`
`Vdsat
`
`[—Qi(V)]dV,
`
`(3.25)
`
`stays the same apart from a slight decrease in L (to L’), as shown in Fig. 3.6.
`This phenomenon is called channel length modulation and will be discussed in
`association with short—channel MOSFETS in Section 3.2.
`
`Further insight into the MOSFET behavior at pinch—off can be gained by ex-
`
`amining the function V(y). lntegrating from 0 to )2 after multiplying both sides of
`
`Eq. (3.8) by dy yields
`
`V
`
`no = MW /0 [—Qz(V)]dV
`= M,c,,,.W<(Vg — V,)V — §V2>.
`
`Substituting Ids from Eq. (3.21) into Eq. (3.26), one can solve for V(y):
`
`(3.26)
`
`(3.27)
`
`V(y):
`
`V—V
`m
`
`g
`
`t_ (g t)_%(g r>vds+%Vd%,.
`
`V~—V 2
`m
`
`V——V
`m
`
`v
`
`Both V(y) and —Q,-/mC,,x = (Vg — Vt)/m — V(y) are plotted in Fig. 3.7 for several
`Values of Vds. At low Vds, V(y) varies almost linearly between the source and drain.
`
`As Vds incre