`
`Office européen des brevets
`
`@ Publication number:
`
`0
`
`EUROPEAN PATENT APPLICATION
`
`Application number: 93115770.5
`
`@ Int. Cl.5: G11C 7/05
`
`@ Applicant: UNITED MEMORIES, INC.
`1873 Austin Bluffs Parkway
`Colorado Springs, CO 80918(US)
`Applicant: Nippon Steel Semiconductor Corp.
`1580, Yamamoto
`Tateyama-shi, Chiba 294(JP)
`
`Inventor: Hardee, Kim C.
`9760 Kit Carson Lane
`
`Colorado Springs, Colorado 80920(US)
`
`Representative: Quinterno, Giuseppe et al
`c/o Jacobacci-Casetta & Perani S.p.A.
`Via Alfieri, 17
`I-10121 Torino (IT)
`
`isolation transistors 232, 234, 238, 240) and a
`of
`corresponding isolation signal (ISOL, ISOR).
`
`/4o\ lD_LPB
`
`(VCC)
`
`Date of filing: 30.09.93
`
`Priority: 12.11.92 us 976312
`
`Date of publication of application:
`18.05.94 Bulletin 94/20
`
`Designated Contracting States:
`DE FR GB IT NL
`
`(SD Sense amplifier with local write drivers.
`
`@ A sense amplifier for a very high density in—
`tegrated circuit memory using CMOS technology is
`described. Each sense amplifier includes first and
`second local sense amplifier drive transistors, one
`(140) connecting the P channel transistors (112, 114)
`
`to VCC; the other (142) connecting the N channel
`transistors (142)
`to VSS. A read amplifier circuit
`(150-156)
`is provided within each sense amplifier
`and is operated by read control signals (DR, DRB,
`YR).
`Internal nodes of the latch of the sense am-
`plifier are coupled by pass transistors (122, 124) that
`are responsive to column write control signals (
`).
`Local data write driver transistors (128, 130, 132,
`134) are also provided to selectively couple the pass
`transistors to VCC-Vt or VSS in response to further
`data write control signals (DW, DWB). A relatively
`wider power line (184) is coupled to the drive tran-
`sistors (140) to provide VCC thereto, and a narrower
`line (181) is used to control
`those first sense am-
`plifier drive transistors (140). Corresponding wide
`and narrow lines (190, 186) are used for the second
`local sense amplifier drive transistors which couple
`the N channel
`transistors to ground. Each sense
`amplifier may be shared between first and second
`pairs of bit lines (220, 222; 224, 226) through the use
`
`EP0597231A2
`
`Rank Xerox (UK) Business Services
`13.10/3.09/3.3.4)
`
`Page 1 of 16
`
` SAMSUNG EXHIBIT 1006
`
`
`
`EP 0 597 231 A2
`
`The present invention relates to integrated cir-
`cuit memories and particularly relates to sense
`amplifiers for use therein.
`include a large
`Integrated circuit memories
`number of memory cells which are usually set forth
`in an array. The memory cells may be volatile or
`non-volatile.
`If they are volatile, they may be static
`RAM cells or dynamic RAM cells. There may be
`one large array, or a given memory chip may have
`several
`sub-arrays which may be arranged in
`blocks. Typically, the memory device comprises a
`large number of bit lines extending in one direction.
`The bit lines may be paired or non paired. Where
`they are paired, they are often referred to as com-
`plementary bit Iines, or paired bit
`lines. Comple-
`mentary bit lines are used for both static RAM and
`dynamic RAM applications. The bit lines generally
`extend in a first direction, and a plurality of word
`lines extend in a second direction which is per-
`pendicular to the first direction. Typically, a mem-
`ory cell
`is located at or near the crossing of a bit
`line with a word line.
`
`Often, a memory array is divided into subar-
`rays, and each subarray may further be divided
`into blocks. Each subarray will often have its own
`"peripheral circuitry" such as decoders.
`The memory array or subarray is usually said
`to be organized into rows and columns. Generally,
`a row indicates the memory cells located along
`(coupled to) a word line. A column is therefore
`ordinarily perpendicular
`to a row and generally
`indicates a collection of memory cells along (coup-
`led to) a bit line or a bit line pair. Generally, each
`column is connected to a respective sense am-
`plifier. One job of the sense amplifier is to sense
`the effect that the memory cell has on the bit line-
`(s) and to amplify that signal for outputting in a
`read operation. Conversely,
`the sense amplifier
`may also drive or control the bit line(s) when the
`memory is writing data into a memory cell.
`CMOS technology is prevalent today. Figure 1
`illustrates a prior art configuration and shows a
`sense amplifier 10 using CMOS technology. The
`operation and configuration of such a sense am-
`plifier 10 is well known and will not be explained
`except briefly herein. Amplifier 10 contains P chan-
`nel transistors 12 and 14 having source electrodes
`commonly coupled to a line 16 which carries from
`time to time a signal LP also called LATCHP. The
`sense amplifier also comprises a pair of N channel
`transistors 18, 20 having source electrodes com-
`monly coupled to a line 22 which sometimes car-
`ries a signal which may be called LN or LATCHN.
`A pair of internal nodes A, B are connected to gate
`electrodes.
`In particular, node A is coupled to the
`gate electrodes of
`transistors 12 and 18, while
`node B is coupled to the gate electrodes of transis-
`tors 14 and 20. These transistors form a latch. A
`
`first bit line BL1 on the left side of sense amplifier
`10 is coupled to node B which is also coupled
`between the drain electrode of P channel transistor
`12 and the drain electrode of N channel transistor
`
`18. Likewise, a complementary bit line BL1 BAR is
`connected to node A which is also coupled be-
`tween the drain electrode of P channel transistor 14
`and N channel transistor 20. Transistors 12 and 14
`
`transistors whereas
`are referred to as "pull—up"
`transistors 18 and 20 are referred to as "pull-down"
`transistors. When a transistor 24 is turned on,
`it
`couples VCC through its source-drain path to line
`16,
`thereby providing the LATCHP signal. Sense
`amplifier 10 forms a flip—flop so that either transis-
`tor 12 or 14 but not both will be turned on and will
`
`the voltage at its corresponding node toward
`pull
`VCC. At or near the same time, one of the transis-
`tors 18 or 20 will pull down the voltage at the other
`node toward VSS which will be connected to line
`
`In this way,
`22 via a transistor 26 being turned on.
`one of the two nodes is pulled high and the other is
`pulled low, and the sense amplifier latches into a
`stable state.
`
`In any large memory, such as a 16 megabit
`DRAM,
`there will be thousands of columns and
`thousands of rows. This is represented in Figure 1
`which shows a second sense amplifier 30 con-
`nected to corresponding bit line pair BL2 and BL2
`BAR, and an N-th sense amplifier 32 coupled to bit
`lines BLN and BLN BAR.
`It should be appreciated
`that N may be on the order of 1000 or more. The
`LATCHP signal
`is applied to all N of these sense
`amplifiers via line 16, and the LATCHN signal
`is
`applied to them via the line 22.
`It will be seen in
`Figure 1
`that a plurality of
`resistances 34 are
`illustrated. These are not discrete resistance de-
`
`vices but rather indicate the parasitic resistance of
`the lines 16 and 22, which, even though they are
`formed of conductive materials such as metal or
`
`the like, nevertheless over great distances will have
`some resistance value. Over each resistance, there
`will be a voltage drop from the voltage applied via
`transistor 24 or 26, as the case may be. Accord-
`ingly,
`the voltage that eventually reaches sense
`amplifier 32 may be appreciably diminished from
`VCC or VSS, and that sense amplifier will work
`inefficiently or slowly.
`It will also be appreciated
`that because of this problem, sense amplifier 10
`does not activate at the same time as sense am-
`
`plifier 32 and the resulting skew prolongs access
`time. Additionally, some prior art designs can be
`unstable if
`the selected sense amplifier
`is con-
`nected to the data line (the bit lines) too early.
`Thus, as power supply (VSS) line 22 is trying
`to pull down to 0v, transistors start to turn on in the
`sense amplifiers. A current flows to the right on line
`22, and there exists a voltage drop due to the
`resistance of line 22. Practical
`limitations prevent
`
`Page 2 of 16
`
`
`
`EP 0 597 231 A2
`
`the solution of greatly widening line 22 to reduce
`its resistance —— the chip area is jealously allocated.
`Hence, in the illustrated architecture, the right-most
`sense amplifier 10 turns on first, and sense am-
`plifier 32 will turn on thereafter.
`Generally, one desires to pull down line 22 at a
`controlled rate. The far end (most
`remote from
`transistor 26) of line 22 will drop in voltage slower
`than the near end. This slows the memory, which is
`undesirable, but if circuitry drove the near end too
`fast, then the corresponding near sense amplifiers
`would become unreliable.
`
`Another problem occurs when the near sense
`amplifiers latch logic "1's" and the far amplifier
`latches a logic
`There is a pattern sensitivity
`because when the bit
`lines are precharged to
`%VCC, the memory cell moves only one of the bit
`lines lower or higher.
`Sensing a "1" occurs before sensing a "0"
`because LN needs to drop only 1 Vt below a
`voltage level corresponding to a
`However,
`to
`sense a "0" LN must be 1Vt below the "0" level,
`and this occurs later. Large current
`flows when
`"1's" are read. Because of the large currents, the
`decline in voltage at the far end of line 22 slows to
`an uncontrolled rate. This effectively can add 7
`nsec.
`to the sensing process -- a substantial and
`undesirable increase.
`
`One approach that has been proposed for ad-
`dressing this problem is depicted in Figure 2.
`It
`shows the same sense amplifiers 10,30, and 32,
`and has the same signals LATCHP and LATCHN
`provided by transistors 24 and 26 respectively.
`However, further N channel transistors have been
`added beneath the sense amplifiers and a modi-
`fication has been made so that LATCHN is carried
`
`these lines 40 is
`lines. One of
`by two distinct
`constructed relatively wide to carry most of
`the
`current, and the other line 42 is relatively narrower
`because it will carry current for just a single se-
`lected sense amplifier. Line 40 is coupled to the
`sources of a plurality of transistors 44, each sense
`amplifier having a respective transistor 44. Each
`transistor 44 has its gate electrode coupled to VCC
`and is therefore generally on. Transistors 44 are
`relatively small
`in size so that they do not carry
`much current to any single sense amplifier.
`The narrower line or rail 42 is coupled to the
`several sense amplifiers by source-drain paths of
`respective transistors 46, which are shown also as
`N channel transistors. Transistors 46 are decoded
`
`indicated by a low to high transition
`and this is
`signal YR 47 shown beside the gate electrode of
`transistor 46 for sense amplifier 32 at the far left
`side of Figure 2. The other transistors 46 also are
`coupled to their YR signals, which are shown illus-
`tratively at 0v,
`i.e. they are not selected columns.
`Thus,
`the column which has been selected de-
`
`codes its YR signal to apply to the gate electrode
`of
`the transistor 46 thereby to couple the narrow
`LATCHN line 42 to the sense amplifier. See also
`Okamura et al., "Decoded—Source Sense Amplifier
`for High-Density DRAMs", IEEE J. Solid State Cir-
`cuTits, Vol. 25, No.
`1
`(Feb 1990), pp 18-23. This
`solution does reduce the sensing skew since the
`current flowing through line 40 is reduced due to
`the weak transistors 44 in the current path. There-
`fore,
`the voltage drop down line 40 is reduced.
`Disadvantages of this approach are that the large
`transistors 46 must be added and that the capaci-
`tive loading on the column select signal YR is
`increased since it must drive the gates of transis-
`tors 46. There is poor control over the current draw
`and extra loading to the YR line because it
`is
`driving an extra transistor per sense amplifier.
`Chin et al.,
`"An Experimental 16-Mbit DRAM
`with Reduced Peak-Current Noise," IEEE J. Solid
`State Circuits, vol. 24, no. 5 (Oct. 1989) at p. 1191
`et seq. and particularly in Figure 4 adds both p-
`channel and n-channel
`transistors between sense
`
`amplifiers and power supply lines. However, it does
`not use one connection to the VCC line and one
`
`It
`connection to the VSS line per sense amplifier.
`does not drive these power
`lines from one end
`only, but rather from several connections that are
`distributed in the array. Signals SAP and SAN bar
`may correspond to LP and LN respectively. Thus,
`in the architecture disclosed that article, there are
`several sense amplifiers connected together, and
`there will still be some pattern sensitivity.
`Figure 3 illustrates further transistors that have
`been used in the past or are used in current
`generations (16 Meg) of very large capacity in-
`tegrated circuit memories. Thus, sense amplifier 10
`is coupled between LATCHP and LATCHN signals
`which are generally VCC and VSS. The data sig-
`nals coming from the data lines are illustrated as D
`and its complement D BAR. However, the source-
`drain paths of further pass transistors 48 and 50
`couple the data signal D to the sense amplifier, and
`an identical arrangement is provided for the com-
`plementary data signal. Transistor 48 is
`respon-
`sively coupled to a global column select signal Y
`which is applied to the gate electrode thereof. Most
`16 meg DRAMs have such global Y select signals.
`Additionally, very large scale memories, as men-
`tioned above,
`include one or more blocks, and
`transistors 50 are illustrated to show a block enable
`
`In
`signal controlling the operation of transistor 50.
`this, the complementary data signals must be high.
`near VCC, during reading and the pass transistors
`must be small compared to the LATCH transistors
`to avoid instability.
`Figure 4 shows some of the problems of cir-
`cuitry styled along the lines of Figure 3.
`In Figure
`4, three identically constructed sense amplifiers 10
`
`Page 3 of 16
`
`
`
`EP 0 597 231 A2
`
`are illustrated, and for ease of reference they will
`be referred to in this drawing as 10A, 10B and 10C.
`For ease of
`illustration,
`the LATCHP line 16 and
`LATCHN line 22 are not shown. The column select
`
`signal Y is a global select signal and is therefore
`shown as having a voltage of VCC. The block
`enable signals are separately provided so that the
`pass transistors 50 for sense amplifier 10A have
`their gate electrodes coupled to a line 52A which
`carries a first block select signal. Similarly, pass
`transistors 50 for sense amplifier 10B have their
`gate electrodes coupled to a second block select
`line 52B which carries a second block select signal,
`and a block select signal
`line 520 similarly cor-
`responds to sense amplifier 10C.
`Sense amplifier 10A is illustratively in an inac-
`tive block,
`for
`sake of explanation.
`"|nactive"
`means herein that LN and LP are at ‘EVCC and the
`latch is inactive. Its block has not been enabled so
`
`the block enable signal on line 52A is low at zero
`volts. Thus, pass transistors 50A are off, and re-
`gardless of whether transistors 48A may be on,
`sense amplifier 10A is generally isolated from data.
`However, to prevent it from latching, LATCHP and
`LATCHN must both be kept at =1;VCC, and the data
`write signal DW and its complement DWB are held
`at VCC.
`
`Sense amplifier 10B is in an active block with
`LN at 0v and LP at VCC. However, with the block
`select at 0v, no write will occur even with the global
`column select Yw at VCC.
`
`Since amplifier 10C is in an active block and a
`write operation is to occur through amplifier 10C.
`The block select signal on line 52C is high, at VCC.
`The column select signal Y is high. With the data
`signal DW high at VCC and its complement DWB
`low at zero volts (or vice-versa if different data is
`being written), the pass transistors 48C, 50C on at
`least one side of sense amplifier 10C will turn on,
`and the sense amplifier will latch the data state and
`drive the bit
`lines so that the data state will be
`
`written into the memory cell or cells along the
`column (usually at the active word line).
`An object of the present invention is to improve
`the sense amplifiers to overcome or reduce the
`aforementioned problems.
`The present invention provides a CMOS sense
`amplifier with local write driver transistors to elimi-
`nate the pattern sensitivities and delays of the prior
`art. Also, each sense amplifier has its own respec-
`tive drive transistors. Third, each sense amplifier
`includes a column read amplifier which eliminates
`the instability problem because the latch nodes are
`never connected to the data lines. Further, the local
`write drivers solve the problems associated with
`global columns selects. Prefer embodiments of the
`present
`invention will use column read YR and
`column write YW signals.
`
`In one of its aspects, while the prior art used
`narrow and wide lines or
`rails each carrying a
`LATCHN signal, the present invention uses narrow
`and wide lines in connection with the LATCHN
`
`signal but connects them differently. Additionally,
`the present invention in one of its aspects includes
`narrow and wide lines or
`rails for
`the LATCHP
`
`in the preferred embodiment,
`supply signal. Thus,
`each sense amplifier has a respective N channel
`transistor having its source-drain path coupled to
`VSS or a signal LATCHN via the wide line. The
`gate electrodes of those N channel drive transistors
`are gated by the narrow drive line which preferably
`carries the complement LNB of the LATCHN sig-
`nal.
`
`in another aspect of the in-
`Correspondingly,
`vention, each sense amplifier includes a respective
`P channel drive transistor, the source-drain path of
`which couples the P channel
`transistors of
`the
`sense amplifier latch to the high voltage such as
`VCC or LATCHP. That high voltage is carried by
`one of the wide drive lines. The narrower of the
`
`drive lines associated with LATCHP is coupled to
`the gate electrodes of these P channel drive tran-
`sistors and carries a complement LPB of
`the
`LATCHP signal.
`Preferably the sense amplifier is shared by a
`column on each side thereof.
`
`Three aspects of present
`
`invention therefore
`
`are:
`
`(1) the connection of each sense amplifier via
`transistors or other switching devices to the
`power supply lines without directly connecting
`together power supply lines for multiple sense
`amplifiers;
`(2) the use of local read amplifiers; and
`(3) the use of local write circuitry.
`Further aspects of
`the invention exist, and these
`three are mentioned as salient points. While it may
`not be necessary to employ all three in combina-
`tion to embody the present invention, the use of all
`three features is most beneficial.
`
`In describing the prior art and the present
`invention,
`reference has been made and will be
`made to accompanying drawings wherein:
`Figure 1 shows a typical CMOS sense amplifier
`group;
`Figure 2 shows the same group of sense am-
`plifiers connected according to one prior art
`modification;
`Figure 3 shows the same prior art sense am-
`plifier with pass transistors for a global column
`select and for block enable features;
`Figure 4 shows three such prior art sense am-
`plifiers having column select and block enable
`capabilities and illustrating the voltages applied
`from time to time depending on the current state
`of the sense amplifier;
`
`Page 4 of 16
`
`
`
`EP 0 597 231 A2
`
`Figure 5 illustrates a sense amplifier constructed
`according to a preferred embodiment of
`the
`present invention;
`Figure 6 shows a simplified form of the sense
`amplifier of the present invention collected into a
`group of such sense amplifiers according to a
`further aspect of the invention;
`Figure 7 shows how the sense amplifier of the
`present invention may operate in various modes;
`and
`
`Figure 8 shows how the preferred sense am-
`plifier may be connected selectively to two pairs
`of bit lines.
`
`Figure 5 illustrates a preferred sense amplifier
`100 according to various aspects of
`the present
`invention. Amplifier 100 includes internal nodes 102
`and 104 in a latch formed by transistors 112, 114,
`118 and 120. Node 102 is coupled to the gate
`electrodes of P channel transistor 112 and N chan-
`
`nel transistor 118, whereas node 104 is coupled to
`the gate electrodes of P channel transistor 114 and
`N channel transistor 120. The configuration of the
`flip—flop itself within the sense amplifier is the same
`as that of sense amplifier 10.
`A column write select signal Yw is coupled to
`the gate electrodes of pass transistors 122, 124.
`Preferably, the column write signal YW and a col-
`umn read signal YR describe below are decoded
`for each four columns, so that each four columns
`has a unique YW and YR. However, this is unnec-
`essary to embody the principles of the invention. In
`one configuration, each subarray may be fairly
`large —— 4Meg illustratively —— and may have a
`respective column decoder that will generate col-
`umn select signals for that whole subarray.
`It
`is
`desired to be able to write to just one block within
`the subarray. That will be
`an
`"active block"
`wherein the sense amplifiers are active. An "inac-
`tive block'' is one where the sense amplifiers are in
`precharge.
`Returning to the description of Fig. 5, however,
`the source—drain path of pass transistor 122 is
`coupled to node 104, and the source—drain path of
`transistor 124 is coupled to node 102.
`Transistor 122 is also coupled to a node 126
`between the source electrode of a local data write
`driver transistor 128 and the drain of another local
`data write driver transistor 130. Transistors 128 and
`
`130 are N channel devices having their source-
`drain paths coupled in series. The drain of transis-
`tor 128 is coupled to VCC and the source of
`transistor 130 is coupled to ground. A data write
`signal DW is coupled to the gate electrode of
`transistor 128 and its complement DWB is coupled
`to the gate electrode of transistor 130. A similar
`configuration exists on the right side of sense am-
`plifier 100 where transistors 132 and 134 are coup-
`led between VCC and ground and have a node 136
`
`therebetween which is coupled to transistor 124.
`Note, however,
`that
`the data write signal DW is
`coupled to control transistor 134 whereas its com-
`plement DWB is coupled to the gate electrode of
`transistor 132. That is to say, the data write signal
`DW turns on a pull-up transistor 128 on the left
`side of the sense amplifier 100, but turns on a pull
`down transistor 134 on the right side of sense
`amplifier 100.
`Its complementary signal DWB like-
`wise has reciprocal effects on the left and right
`sides.
`The source electrodes of P channel transistors
`
`112 and 114 within amplifier 100 are coupled to a
`further P channel
`transistor 140,
`the source elec-
`trode of which is coupled to VCC (or LATCHP).
`The gate electrode of this P channel device 140 is
`coupled to receive a signal LPB which is the logical
`complement of LATCHP. FET 140 is referred to as
`a iocal sense amplifier drive transistor. Similarly,
`the source electrodes of the N channel transistors
`
`118 and 120 within amplifier 100 are coupled to
`ground through the source—drain path of a further
`local sense amplifier drive transistor 142. The gate
`electrode of
`transistor 142 is coupled to receive
`signal LNB which is
`the logical complement of
`LATCHN.
`
`The lower portion of Figure 5 includes a local
`column read amplifier which includes four N chan-
`nel transistors 150, 152, 154, and 156. The source-
`drain paths of transistors 150 and 152 are coupled
`in series. The drain electrode of
`transistor 150
`
`receives a signal DRB which is a logical com-
`plement of a data read signal DR. The source
`electrode of
`transistor 152 is coupled to ground.
`Node 104 is coupled via a conductive line 158 to
`the gate electrode of transistor 152. The gate elec-
`trode of transistor 150 is coupled to a column read
`signal YR. The source—drain path of transistors 154
`and 156 are coupled in series between the data
`read signal DR and ground. The gate electrode of
`transistor 154 is coupled to the gate electrode of
`transistor 150, and accordingly is coupled to the
`column read signal YR. The gate electrode of tran-
`sistor 156 is coupled to internal node 102 via a
`conductive line 160.
`
`the circuit of Figure 5 includes data
`Hence,
`read circuitry formed by transistors 150 through
`156. Transistors 128, 130, 132 and 134 comprise
`local data write transistors. Transistors 140 and 142
`
`It
`comprise local sense amplifier drive transistors.
`will be understood that there are thousands of such
`
`circuits 100 in a large integrated circuit memory.
`The signals LPB and LNB connected to the local
`sense amplifier drive transistors,
`the data write
`signal DW and its complement DWB coupled to
`the local data write driver transistors, and the data
`read signals DR and DRB are shared among or
`applied to many sense amplifiers on the memory
`
`Page 5 of 16
`
`
`
`EP 0 597 231 A2
`
`device. The global Y select signals YR (for reading)
`and Yw (for writing) are shared among several
`sense amplifiers in a direction perpendicular to the
`LNB, LPB, and data lines. There are separate read
`and write data buses. DR and DRB comprise a
`read data bus and DW and DWB comprise a write
`data bus. To sense (latch) data, the bit line signal
`is connected to the latch nodes L and LB by
`circuitry shown in subsequent drawings, or can be
`connected directly in some embodiments to these
`latch nodes, and then the local sense amplifier
`drive transistors 140 and 142 turn on by LPB going
`low and LNB going high. These transistors 140 and
`142 give the advantage over the traditional sense
`amplifier that each sense amplifier
`is decoupled
`from other sense amplifiers, and latching can be
`more accurately controlled with these two signals
`LPB and LNB. The sense amplifiers are decoupled
`from each other because the drains of transistors
`
`140 and 142 are separate for each sense amplifier.
`Transistors 150.152.154.156 comprise a read
`amplifier which provides a non-destructive read op-
`eration. The column read signal YR can go high at
`any time, even prior to latching, without upsetting
`the sense amplifier. Additionally, the data read sig-
`nals DR and DRB can be at any voltage without
`upsetting the sense amplifier. A further advantage
`is that transistors 150 through 156 can be sized
`independently of
`the sense amplifiers transistors
`112,114,118,120.
`Writing is accomplished when the column write
`signal Yw (a decoded signal) is high and either of
`the data write signals DW or DWB is high.
`If both
`of these data write signals are low, writing does not
`occur. This circuit eliminates the need for a block
`
`enable (BE) signal of the sort shown in Figure 3
`and implicit in Figure 4. The local data write driver
`transistors 128-134 can be shared with other col-
`
`umn circuits as long as they have separate column
`write signals. A modification to this circuit of Figure
`5 couples the gate electrode of transistor 128 to its
`drain, and does the same for transistor 132. This
`may reduce the number of metal lines required and
`can save area or
`improve the layout. They will
`result in about the same writing speed. The VCC
`connections at
`the drain electrodes of
`transistor
`128 and 132 are eliminated, but
`there is some
`increased loading on the data write signals DW and
`DWB.
`
`Figure 6 is similar to Figure 1 and Figure 2.
`For clarity of illustration, sense amplifiers (and as-
`sociated circuitry) 100 are shown in block form in
`Figure 6. Each block marked 100 is intended to
`include all of
`the devices of Figure 5 with the
`exception of
`transistors 140 and 142 which are
`shown in Figure 6 for each sense amplifier 100.
`The connections to the bit lines are not shown, and
`it will be understood that each sense amplifier 100
`
`may be connected to a respective pair of bit lines
`either directly or selectively through nodes 102 and
`104 of Figure 5.
`In Figure 6, power is supplied to
`the P channel transistors 112, 114 of each sense
`amplifier 100 via transistors 140. Preferably each
`transistor 140 is a P channel device the gate elec-
`trode of which is coupled to the signal LPB which
`stands for Latch P BAR. A relatively narrow line
`connects the LPB signal to the gate electrodes of
`an entire group of sense amplifiers 100 as shown
`in Figure 6. The LPB signal may be generated by a
`transistor 180,
`the source-drain path of which is
`coupled to ground. Transistor 180 may comprise
`an N channel
`transistor so that when a positive
`voltage is applied to its gate electrode, LPB is
`pulled to ground and all of transistors 140 coupled
`to that particular transistor 180 should turn on. This
`would thereby couple the VCC voltage (or LATCHP
`signal) applied at 182 through a relatively wide line
`184 to the source electrodes of transistors 140.
`
`A similar configuration is used for the N chan-
`transistors at
`the bottom of Figure 6. The N
`nel
`channel transistors 118, 120 within sense amplifiers
`100 are coupled to ground via N channel transis-
`tors 142 as explained with respect to Figure 5. The
`gate electrodes of transistors 142 are coupled via a
`relatively narrow line 186 to the signal LNB which
`stands for Latch N BAR. Signal LNB may be gen-
`erated by a preferably P channel transistor 188, the
`source-drain path of which is coupled between
`VCC and line 186. The gate electrode of transistor
`188 and transistor 180 are coupled to suitable
`control signals. When transistor 188 is conductive
`(its gate electrode receives a low voltage), the LNB
`signal is pulled to VCC thereby to turn on transis-
`tors 142. This couples each sense amplifier to a
`relatively wide line 190 which couples VSS (or
`LATCHN) to the source electrodes of each transis-
`tor 142.
`
`the narrow line 181 carries very
`In Figure 6,
`little current. Each sense amplifier 100 is isolated
`from the others. Each one has its own connection
`
`to the power supply lines 184 and 190. This re-
`duces or eliminates pattern sensitivity of the type
`
`which is encountered in architectures such as @
`with distributed connections (multiple sense amps
`connected together to power supply lines).
`Figure 7 shows some of the voltages when the
`preferred circuit 100 is used in a large memory,
`and is comparable to Figure 4. Not all of
`the
`devices of Figure 5, however, are shown in Figure
`7, and only some of the devices have been labeled
`in sense amplifier 100A. Thus, the local data write
`driver transistors 128, 130, 132 and 134 are label-
`ed, as are the column write select transistors 122,
`124. Not shown are the local sense amplifiers drive
`transistors 140 and 142, but the connections are
`shown to LATCHP and LATCHN which may be
`
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`EP 0 597 231 A2
`
`taken to be either the wide lines 184 and 190 or
`the drain electrodes of
`transistors 140 and 142.
`
`The column read amplifier formed by transistors
`150-156 is not shown and should be understood to
`
`be present. Assuming that a column write signal is
`to be generated, the column select signal on line
`200 is shown as being high, at VCC. Figure 7
`assumes that sense amplifier 100A is to be part of
`an inactive block, sense amplifier 100B is for an
`active block without a write, and sense amplifier
`1000 is part of an active block where a write is to
`occur.
`
`Sense amplifier 100A in the inactive block re-
`ceives a full VCC signal at the gate electrode of its
`pass transistors 122 and 124. However, the local
`data write driver transistors 128 through 134 all
`receive zero volts applied to the gate electrodes
`thereof because DW and DWB are at zero volts.
`It
`
`will be noted that with regard to the transistors 128
`and 132, the aforementioned modification has been
`shown where the connection to VCC has been
`eliminated at the drain electrodes of those transis-
`tors which have instead been connected to their
`
`gate electrodes. Note that in the inactive block, the
`P channel transistors 112, 114 are coupled to re-
`ceive only %VCC, and likewise the N channel tran-
`sistors 118 and 120 are coupled to receive the
`same voltage. Thus, in this state, the latch is inac-
`tive and no power is consumed.
`Sense amplifier 100B is located in an active
`block but is not to have a write operation. Because
`it
`is in an active block, the LATCHP signal is at a
`full VCC, and the LATCHN signal is at zero volts.
`However, since no write operation is to occur, DW
`and DWB are low (0v), and transistors 128 through
`134 comprising the local data write driver transis-
`tors are all coupled to receive zero volts at their
`gate electrodes.
`In this configuration,
`the sense
`amplifier latch holds the previous data state and no
`write occurs.
`
`Sense amplifier 100C is in the active block and
`therefore LATCHP is at a full VCC level and
`LATCHN is at zero volts, as shown. However, a
`write operation is to occur, and illustratively the
`data write signal DW is at zero volts and its com-
`plement DWB is at VCC. Transistor 130 turns on,
`thereby coupling the zero volts from LATCHN to
`the node 104 via pass transistor 122. Transistor
`132 receives VCC at
`its gate electrode and its
`drain electrode, and will
`turn on, coupling a non-
`zero voltage through pass transistor 124 to node
`102. With node 102 at a non-zero voltage and node
`104 pulled down to zero volts via transistor 130, the
`sense amplifier latches and will drive the bit lines
`(not shown) to the one