UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________
`
`SAMSUNG ELECTRONICS CO., LTD.
`Petitioner
`
`v.
`
`PROMOS TECHNOLOGIES INC.
`Patent Owner
`
`____________________
`
`Patent No. 6,195,302
`____________________
`
`DECLARATION OF DR. R. JACOB BAKER, PH.D., P.E. IN SUPPORT OF
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 6,195,302
`
`
`
`SAMSUNG EXHIBIT 1002
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`Page 1 of 101
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`
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 6,195,302
`
`
`TABLE OF CONTENTS
`
`I. 
`
`II. 
`
`INTRODUCTION............................................................................................................. 3 
`
`BACKGROUND AND QUALIFICATIONS ................................................................. 3 
`
`III.  MATERIALS REVIEWED ............................................................................................. 6 
`
`IV. 
`
`V. 
`
`PERSON OF ORDINARY SKILL IN THE ART ......................................................... 8 
`
`TECHNICAL BACKGROUND ...................................................................................... 8 
`A. 
`MOSFET ................................................................................................................. 9 
`B. 
`MOSFET As a Switch .......................................................................................... 11 
`C. 
`Basic Operating Principles of a MOSFET ............................................................ 16 
`D. 
`Resistance of a MOSFET ...................................................................................... 17 
`E. 
`Basic Operating Principles of a DRAM ................................................................ 19 
`
`VI.  OVERVIEW OF THE ’302 PATENT .......................................................................... 21 
`
`VII.  CLAIM CONSTRUCTION ........................................................................................... 25 
`“a timer unit having an output coupled to the control electrode and
`A. 
`generating a control signal” .................................................................................. 25 
`“a first component within the timer unit causing the control signal to
`change from a first logic level towards a second logic level at a first rate” ......... 25 
`“a second component within the timer unit causing the control signal to
`change to the second logic level at a second rate” ................................................ 26 
`“a delay unit coupled to the sense control signal node and generating a
`delayed sense control signal” ................................................................................ 26 
`
`B. 
`
`C. 
`
`D. 
`
`VIII.  OVERVIEW OF THE PRIOR ART............................................................................. 26 
`A. 
`Seo......................................................................................................................... 26 
`B. 
`Min ........................................................................................................................ 30 
`C. 
`Schuster ................................................................................................................. 38 
`
`IX. 
`
`THE PRIOR ART DISCLOSES OR SUGGESTS ALL OF THE FEATURES
`OF THE CHALLENGED CLAIMS ............................................................................. 41 
`A. 
`Seo and Min Disclose or Suggest the Features of Claims 1-5 and 10-12 ............. 41 
`1. 
`Claim 10 .................................................................................................... 41 
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 6,195,302
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`Claim 11 .................................................................................................... 71 
`2. 
`Claim 12 .................................................................................................... 72 
`3. 
`Claim 1 ...................................................................................................... 73 
`4. 
`Claim 2 ...................................................................................................... 90 
`5. 
`Claim 3 ...................................................................................................... 91 
`6. 
`Claim 4 ...................................................................................................... 91 
`7. 
`Claim 5 ...................................................................................................... 92 
`8. 
`Seo Discloses the Features of Claims 10-12 ......................................................... 94 
`9. 
`Claim 10 .................................................................................................... 94 
`10. 
`Claim 11 .................................................................................................... 96 
`11. 
`Claim 12 .................................................................................................... 96 
`Seo, Min, and Schuster Disclose or Suggest the Features of Claim 6 .................. 96 
`12. 
`Claim 6 ...................................................................................................... 96 
`
`B. 
`
`C. 
`
`CONCLUSION ............................................................................................................. 100 
`
`X. 
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 6,195,302
`
`
`I, R. Jacob Baker, Ph.D., P.E., declare as follows:
`
`I.
`
`INTRODUCTION
`1.
`
`I have been retained by Samsung Electronics Co., Ltd. (“Petitioner”)
`
`as an independent expert consultant in this proceeding before the United States
`
`Patent and Trademark Office (“PTO”).
`
`2.
`
`I am being compensated at a rate of $550/hour for my work.
`
`3. My compensation is in no way contingent on the nature of my
`
`findings, the presentation of my findings in testimony, or the outcome of this or
`
`any other proceeding. I have no other interest in this proceeding.
`
`4.
`
`I have been asked to consider whether certain references disclose or
`
`suggest the features recited in the claims of U.S. Patent No. 6,195,302 (“the ’302
`
`Patent”) (Ex. 1001)1. My opinions are set forth below.
`
`II. BACKGROUND AND QUALIFICATIONS
`5.
`I presently serve as a Professor of Electrical and Computer
`
`Engineering at the University of Nevada, Las Vegas (UNLV). All of my opinions
`
`stated in this declaration are based on my own personal knowledge and
`
`professional judgment. In forming my opinions, I have relied on my knowledge
`
`
`1 Where appropriate, I refer to exhibits that I understand to be attached to the
`
`petition for Inter Partes Review of the ’302 patent.
`
`3
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 6,195,302
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`and experience in designing, developing, researching, and teaching regarding
`
`circuit design and memory devices referenced in this declaration.
`
`6.
`
`I am over 18 years of age and, if I am called upon to do so, I would be
`
`competent to testify as to the matters set forth herein. I understand that a copy of
`
`my current curriculum vitae, which details my education and professional and
`
`academic experience, is attached as Ex. 1010 in this proceeding. The following
`
`provides an overview of some of my experience that is relevant to the matters set
`
`forth in this declaration.
`
`7.
`
`I have been teaching electrical engineering at UNLV since 2012.
`
`Prior to this position, I was a Professor of Electrical and Computer Engineering at
`
`Boise State University from 2000. Prior to my position at Boise State University, I
`
`was an Associate Professor Electrical Engineering between 1998 and 2000 and
`
`Assistant Professor of Electrical Engineering between 1993 and 1998 at the
`
`University of Idaho. I have been teaching electrical engineering since 1991.
`
`8.
`
`I received my Ph.D. in Electrical Engineering from the University of
`
`Nevada, Reno in 1993. I also received a MS and BS in Electrical Engineering
`
`from UNLV in 1988 and 1986, respectively.
`
`9.
`
`As described in my curriculum vitae, I am a licensed Professional
`
`Engineer in the state of Idaho and have more than 30 years of experience,
`
`including extensive experience in circuit design and manufacture of Dynamic
`
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 6,195,302
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`Random Access Memory (DRAM) integrated circuit chips and CMOS Image
`
`Sensors (CISs) at Micron in Boise, Idaho. I also spent considerable time working
`
`on the development of Flash Memory while at Micron. My efforts resulted in
`
`more than a dozen Flash-memory related patents. Among other experiences, I led
`
`development of the delay-locked loop (DLL) in the late 90s so that Micron
`
`products could transition to the DDR memory standard. I have worked as a
`
`consultant at other companies designing memory chips, including Sun, Oracle, and
`
`Contour Semiconductor. I also worked on the design of CISs and memory as a
`
`consultant for OmniVision.
`
`10.
`
`I have taught courses in integrated circuit design (analog, digital,
`
`mixed-signal, memory circuit design, etc.), linear circuits, microelectronics,
`
`communication systems, and fiber optics. As a professor, I have been the main
`
`advisor to seven Doctoral students and over 70 Masters students.
`
`11.
`
`I am the author of several books covering the area of integrated circuit
`
`design including: DRAM Circuit Design: Fundamental and High-Speed Topics
`
`(two editions), CMOS Circuit Design, Layout, and Simulation (three editions), and
`
`CMOS Mixed-Signal Circuit Design (two editions). I have authored, and co-
`
`authored, more than 100 papers and presentations in the areas of solid-state circuit
`
`design, and I am the named inventor on 144 granted U.S. patents in integrated
`
`circuit designs including flash memory and DRAM.
`
`5
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 6,195,302
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`I have received numerous awards for my work, including the
`
`12.
`
`Frederick Emmons Terman (the “Father of Silicon Valley”) Award. The Terman
`
`Award is bestowed annually upon an outstanding young electrical/computer
`
`engineering educator in recognition of the educator’s contributions to the
`
`profession.
`
`13.
`
`I am a Fellow of the IEEE for contributions to memory circuit design.
`
`I have also received the IEE Circuits and Systems Education Award (2011).
`
`14.
`
`I have received the President’s Research and Scholarship Award
`
`(2005), Honored Faculty Member recognition (2003), and Outstanding Department
`
`of Electrical Engineering Faculty recognition (2001), all from Boise State
`
`University. I have also received the Tau Beta Pi Outstanding Electrical and
`
`Computer Engineering Professor award the four years I have been at UNLV.
`
`15.
`
`I am not an attorney and offer no legal opinions, but in the course of
`
`my work, I have had experience studying and analyzing patents and patent claims
`
`from the perspective of a person skilled in the art.
`
`III. MATERIALS REVIEWED
`16. The opinions in this Declaration are based on the documents I
`
`reviewed, my knowledge and experience, and professional judgment. In forming
`
`my opinions expressed in this Declaration, I have reviewed the following
`
`materials: U.S. Patent No. 6,195,302 (Ex. 1001); Prosecution History of U.S.
`
`6
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 6,195,302
`
`Patent No. 6,195,302 (Ex. 1003); U.S. Patent No. 5,140,199 (“Seo”) (Ex. 1004);
`
`U.K. Patent GB2246005B (“Min”) (Ex. 1005); European Patent EP 0597231 A2
`
`(“Hardee EP”) (Ex. 1006); Schuster et al., “A 15-ns CMOS 64K RAM,” IEEE J.
`
`of Solid-State Circuits, Vol. SC-21, No. 5, Oct. 1986 (“Schuster”) (Ex. 1007); Taur
`
`et al., Fundamentals of Modern VLSI Devices, 1998 (“Taur”), including chapters
`
`1, 3, and 4 (Ex. 1008); U.S. Patent No. 4,980,799 (“Tobita”) (Ex. 1009); and any
`
`other materials I refer to in this declaration in support of my opinions..
`
`17. All of the opinions contained in this declaration are based on the
`
`documents I reviewed and my knowledge and professional judgment. My opinions
`
`have also been guided by my appreciation of how a person of ordinary skill in the
`
`art would have understood the claims and the specification of the ’302 patent at the
`
`time of the alleged invention, which I have been asked to initially consider as the
`
`late 1990’s (including February 5, 1999, the filing date for of U.S. Provisional
`
`Patent Application No. 60/118,737, whose benefit is claimed by the ’302 patent).
`
`My opinions reflect how one of ordinary skill in the art would have understood the
`
`’302 patent, the prior art to the patent, and the state of the art at the time of the
`
`alleged invention.
`
`18. Based on my experience and expertise, it is my opinion that certain
`
`references disclose all the features recited in claims 1-6 and 10-12 (“challenged
`
`claims”) of the ’302 patent, as I discuss in detail below.
`
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 6,195,302
`
`
`IV. PERSON OF ORDINARY SKILL IN THE ART
`19.
`I am familiar with the level of ordinary skill in the art with respect to
`
`the inventions of the ’302 patent as of what I understand is the filing date of
`
`February 5, 1999 for Provisional App. 60/118,737, to which the ’302 patent claims
`
`priority. Specifically, based on my review of the ’302 patent, the technology, the
`
`educational level and experience of active workers in the field, the types of
`
`problems faced by workers in the field, the solutions found to those problems, the
`
`sophistication of the technology in the field, and drawing on my own experience, I
`
`believe a person of ordinary skill in art at that time would have had at least a B.S.
`
`degree in electrical engineering, or equivalent thereof, and at least two to three
`
`years of experience in design of semiconductor memory circuits. More education
`
`can supplement practical experience and vice versa. Depending on the engineering
`
`background and level of education of a person, it would have taken a few years for
`
`the person to become familiar with the problems encountered in the art and become
`
`familiar with the prior and current solutions to those problems. All of my opinions
`
`in this declaration are from the perspective of one of ordinary skill in the art as I
`
`have defined it here during the relevant timeframe, i.e., February 1999.
`
`V. TECHNICAL BACKGROUND
`20.
`In this section, I present a brief overview of basic circuit concepts that
`
`will assist in better understanding the ’302 patent and the prior art that I discuss in
`
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 6,195,302
`
`
`this declaration. In particular, I cover below the operation of a metal-oxide-
`
`semiconductor field-effect transistor (MOSFET or MOS transistor), which is the
`
`building block of the circuits described in the ’302 patent and the prior art. I also
`
`briefly discuss the basic architecture of memory systems that are applicable to the
`
`’302 patent and related prior art.
`
`A. MOSFET
`21.
`In 1998, a metal oxide semiconductor field effect
`
`transistor
`
`(MOSFET) was known by those skilled in the art as the building block of circuits
`
`in various applications, including memory systems. (Ex. 1008 at 112.) MOSFETs
`
`have been known since at least as early as 1960, i.e., decades before the alleged
`
`invention of the ’302 patent. (Id. at 2.) As an example, a book by Taur entitled
`
`Fundamentals of Modern VLSI Devices, also explains this known characteristic of
`
`MOSFETs. (See e.g., Ex. 1008 at 2.)
`
`22. The MOSFET was known to be a four-terminal device with the
`
`terminals designated as gate, source, drain, and substrate (substrate is sometimes
`
`referred to as a body). (Id. at 112.) The substrate was typically a silicon substrate.
`
`Although pure silicon is a poor conductor, the electrical conductivity of silicon was
`
`known to be increased by introducing impurity atoms, or dopants, into the silicon.
`
`(Id. at 12-13.) Silicon material doped with p-type dopants is called p-type silicon,
`
`and silicon material doped with n-type dopants is called n-type silicon. (Id. at 13).
`
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 6,195,302
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`Taur provides an example of the basic structure of a MOSFET in FIG. 3.1 that
`
`includes a p-type silicon substrate and n-type source and drain regions that are each
`
`heavily doped compared to the substrate. (Id. at 112.)
`
`
`
`(Id. at 113.)
`
`23. The configuration shown in Figure 3.1 of Taur was consistent with the
`
`basic structure of such a configured MOSFET that one skilled in the art would
`
`have understood even years before Taur was published. (See, e.g., reference to
`
`Arora 1993 below the figure.)
`
`24.
`
`In configurations where the source and drain regions are heavily n-
`
`doped, similar to the configuration shown in FIG. 3.1 above, the MOSFET was
`
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 6,195,302
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`typically known as an n-channel MOSFET (or NMOSFET, NMOS transistor, or
`
`simply NMOS). Another type of MOSFET that was known is a p-channel
`
`MOSFET (or PMOSFET, PMOS transistor, or simply PMOS), in which the dopant
`
`types are reversed compared to those of an n-channel MOSFET as I described
`
`above (and exemplary shown in FIG. 3.1.) (See also id. at 112.)
`
`B. MOSFET As a Switch
`25.
`In the simplified model for a MOSFET, there is no current flow
`
`between the source and drain unless the voltage between gate and source terminals
`
`exceeds a threshold voltage. (Id.) When a sufficiently large voltage (called the
`
`threshold voltage of the transistor or VT) is applied between the gate and the
`
`source, the silicon surface between the source and drain is inverted to n-type,
`
`which forms a conductive n-channel between the source and drain. (Id.) If there is
`
`a voltage difference between the source and drain, current will then flow between
`
`those terminals. (Id.) Thus, the MOSFET operates like a switch and conducts
`
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 6,195,302
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`current depending on the |VGS| (voltage between gate and source terminals).2 (Id.)
`
`For a PMOS, the current flows from source to drain when the gate voltage is below
`
`the source voltage by the threshold voltage. On the contrary, for an NMOS, the
`
`current flows from drain to source when the gate voltage is greater than the source
`
`voltage by the threshold voltage.
`
`26. The following demonstratives illustrate the above basic concepts.
`
`Demonstrative A illustrates the symbols that were commonly attributed to an
`
`NMOS and a PMOS in circuit designs at the time of the alleged invention of the
`
`’302 patent. The gate, drain, and source are respectively labeled G, D, and S in
`
`these demonstratives.
`
`
`2 The MOSFET also operates in what is called the “sub-threshold” region,
`
`where a very small amount of current is conducted by the MOSFET because the
`
`gate-source voltage is lower than threshold. The “sub-threshold” mode is not
`
`really implicated in the ’302 patent and the prior art because the applied voltages
`
`will result in the gate-source voltage being higher than threshold.
`
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 6,195,302
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`DEMONSTRATIVE A
`
`
`
`Demonstrative B illustrates an NMOS with a threshold voltage of 1V and describes
`
`that when the gate to source voltage (VGS) is less than 1V (e.g., both gate and
`
`source are at ground (shown by the green triangles), no current flows through the
`
`NMOS (represented by the red “X”), but when the gate to source voltage is greater
`
`than or equal to the threshold voltage, current flows from drain to source (shown
`
`by the orange arrow).
`
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 6,195,302
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`DEMONSTRATIVE B
`
`
`
`27. Demonstrative C similarly illustrates the operation of a PMOS with
`
`the difference being that for the PMOS, the gate voltage has to be lower than the
`
`source voltage for the PMOS to conduct current. That is, instead of VGS being
`
`greater than VT, the VSG must be greater than VT.
`
`
`
`DEMONSTRATIVE C
`
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 6,195,302
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`28. A simple circuit example of an inverter brings together the above
`
`basic MOSFET concepts. For instance, as shown below in demonstrative D, an
`
`inverter consists of a PMOS and NMOS in series with shared drain terminals. This
`
`configuration is consistent with what was known to one of ordinary skill in the art
`
`at the time of the alleged invention for the ’302 patent. The source of the PMOS is
`
`at 5V in this example and the source of the NMOS is at 0V. Assume that the
`
`threshold is 1V. When an input voltage (VIN) of 5V is provided to the gates of
`
`both the PMOS and the NMOS, the VSG of the PMOS is 0V (less than VT) and
`
`the VGS of the NMOS is 5V (greater than VT). Accordingly, the PMOS is turned
`
`off and the NMOS is turned on. Because there is no current flowing through the
`
`PMOS, the NMOS will “pull down” the voltage at its drain terminal causing an
`
`output voltage (VOUT) of 0V.
`
`
`
`DEMONSTRATIVE D
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 6,195,302
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`If, however, in the same example the input is at 0V, the PMOS will
`
`29.
`
`turn on, NMOS will shut off, as a result of which the PMOS will “pull up” the
`
`voltage at its drain to 5V.
`
`DEMONSTRATIVE E
`
`
`
`30.
`
`I refer to these basic concepts of “pull up” and “pull down” when I
`
`explain the prior art below (see infra Sections VIII, IX).
`
`C. Basic Operating Principles of a MOSFET
`31.
`I also explain some of the basic physics behind the MOSFET
`
`operation because I refer back to this during my explanation of the prior art (see
`
`infra Sections VIII, IX).
`
`32. The current-conducting capability of the MOSFET depends on the
`
`dimensions of the transistor, i.e., width (W) and length (L) as shown in FIG. 3.1 of
`
`Taur (reproduced above in Section V.A). When the MOSFET operates in the
`
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 6,195,302
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`above-threshold region (i.e., |VGS|3 is greater than threshold), for a given VDS, the
`
`MOSFET current (i.e., the drain-source or source-drain current) is proportional to
`
`|VGS|, i.e., a higher |VGS| results in a higher current through the MOSFET. The
`
`below equations apply to an NMOS but similar equations apply to a PMOS:
`
`
`
`
`
`(Ex. 1008 at 118, 120.)
`
`D. Resistance of a MOSFET
`33. Every MOSFET has associated parasitic resistance and a channel
`
`resistance. This inherent characteristic is described in Taur, Fundamentals of
`
`Modern VLSI Devices (“Taur”), which describes the total resistance associated
`
`with a MOSFET as the sum of three series resistances: a source resistance Rs, a
`
`
`3 I use the absolute value sign with VGS because for a PMOS, the VSG has to be
`
`greater than threshold for the PMOS to conduct.
`
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 6,195,302
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`drain resistance Rd, and a channel resistance Rch. (Ex. 1008 at 205-06.) The
`
`source resistance Rs and a drain resistance Rd are assumed to connect an intrinsic
`
`MOSFET to the external terminals where a drain-source voltage Vds and gate
`
`voltage Vg are applied. (Ex. 1008 at 205-06.) Taur shows these resistances
`
`schematically in an equivalent circuit as follows:
`
`
`
`(Ex. 1008 at 205, FIG. 4.20.)
`
`34. Because the source and drain regions are normally symmetrical, the
`
`sum of Rs and Rd may be denoted by Rsd. (Ex. 1008 at 206.) The total resistance
`
`for a MOSFET is captured by the following equation:
`
`
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`(Ex. 1008 at 206.)
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 6,195,302
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`35. Thus, one of ordinary skill would have recognized that the total device
`
`resistance of a MOSFET is the sum of a parasitic impedance Rsd across the source
`
`and drain terminals of transistor Te and a channel resistance Rch. (Id.) Based on
`
`the MOSFET model described in Taur, a PMOS (for example) may be represented
`
`in my demonstrative below:
`
`
`
`DEMONSTRATIVE F
`
`E. Basic Operating Principles of a DRAM
`36.
`I also explain some of the basic principles of a dynamic random
`
`access memory (DRAM) because I refer back to this during my explanation of the
`
`prior art (see infra Sections VIII, IX).
`
`37. At the time of the alleged invention of the ’302 patent, it was well
`
`known that integrated circuit memories could include memory cell arrays
`
`consisting of thousands of memory cells arranged in a matrix of rows (word lines)
`
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 6,195,302
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`and columns (bit lines), with each memory cell located at or near the crossing of a
`
`bit line and word line. (See Ex. 1009 at 1:20:34.) The basic architecture of such
`
`integrated circuit memories can be understood by looking at the structure of a
`
`DRAM, which was a type of known integrated circuit memory.
`
`38. A DRAM includes a memory cell array consisting of memory cells
`
`arranged in a matrix of rows of word lines and columns of bit lines. (Id. at 1:22-
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`34.)
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`(Id. at FIG. 1, illustrating an example of a conventional DRAM.)
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`39. To read and write to the memory cells of a DRAM, other circuitry is
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`provided. (Id. at 1:20-34, FIG. 1.) For instance, an address buffer AB may receive
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 6,195,302
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`an externally applied external address and generate an internal address, which is
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`provided to an X decoder ADX and Y decoder ADY that decode the internal
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`address and select a corresponding row and column, respectively, in the memory
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`cell array MA. (Id.) The bit lines were often coupled into complementary bit line
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`pairs, with each pair associated with a sense amplifier that amplifies the signal on
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`the bit lines during a read operation and drives/controls the bit lines when data is
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`being written into the memory cells. (See id. at FIG. 2.)
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`VI. OVERVIEW OF THE ’302 PATENT
`40. The ’302 patent is entitled “Dual slope sense clock generator.” (Ex.
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`1001 at Title.) FIG. 1 of the ’302 patent discloses a memory device 100 including
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`sense amplifiers 101a, 101b, and 101c that are coupled to a high voltage line Vcc
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`and ground via driver transistors 104 and 106, respectively:
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`(Ex. 1001 at FIG. 1.)
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 6,195,302
`
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`41. Each sense amplifier 101a, 101b, 101c includes a pair of NMOS
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`transistors and a pair of PMOS transistors arranged in a cross-coupled
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`configuration. (Id. at FIG. 1.) The sense amplifiers 101a-101c share a latch power
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`supply node LP and a latch power supply node LN. (Id. at FIG. 1, 1:62-67, 4:58-
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`59.) Each sense amplifier 101, 101b, 101c is coupled to ground by a
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`corresponding driver transistor 106 and is coupled to a voltage Vcc by a
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`corresponding driver transistor 104. (Id. at FIG. 1.) Each driver transistor 104 is
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`driven by a common control signal LPB, and each driver transistor 106 is driven by
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`a common control signal LNB. (Id.) Driver transistors 104 are PMOS pull-up
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`transistors, and driver transistors 106 are NMOS pull-down transistors. (Id.)
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`42. To activate the sense amplifiers 101, “the LPB signal is driven to a
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`logic low coupling VCCI to sense amp 101 through drive transistor 104 [and]
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`[s]imilarly, the LNB signal is driven high to couple sense amp 101 to ground or
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`VSS through drive transistor 106.” (Id. at 5:38-42.)
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`43.
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`“FIG. 3 shows in block diagram form a circuit useful in generating the
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`dual slope LPB and LNB control signals.” (Id. at 5:56-58.) The circuit for
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`generating control signals LNB and LBP is shown below:
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 6,195,302
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`(Id. at FIG. 1.)
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`44. Signals SENR and SENL are inputs to the circuit in FIG. 3 and are
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`described as follows in the ’302 patent:
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`In operation, one of the input signals SENR or SENL will go to
`a logic high when sensing is to begin and then goes to a logic
`low during precharge or standby mode. . . . During standby,
`when both SENR and SENL are low, the control signal on node
`302 is a logic high. Soon after either SENR or SENL goes high,
`the signal on node 302 will transition to a logic low.
`(Id. at 5:66-6:6.)
`
`45. The ’302 patent discloses that after the signal on node 302 transitions
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`to a logic low, a pull-down path is activated to pull down the voltage at node LPB,
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`and a pull-down path is activated to pull up the voltage at node LNB:
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 6,195,302
`
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`The signal on node 302 is inverted by inverter 304 and applied
`to the control node of transistor 303. Hence, shortly after either
`SENR or SENL goes high, transistor 303 is turned on pulling
`the LPB signal low through resister 306. Similarly, when the
`signal on node 302 goes low, transistor 313 is turned on pulling
`the LNB signal high through resistor 316. Resistor 316 controls
`the rate of change or dv/dt of LNB while resistor 306 controls
`the dv/dt of LPB.
`(Id. at 6:7-14.)
`
`46. The ’302 patent discloses that after a delay, a second pull-down path
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`is activated to pull down the voltage at node LPB, and a second pull-up path is
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`activated to pull up the voltage at node LPN:
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`After a delay determined by delay element 307, transistor 308
`will be turned on pulling LPB to ground with a much lower
`resistance. When transistor 308 is turned on, LPB will fall to
`the ground voltage with a high dv/dt. Similarly, after a delay
`determined by delay unit 317, transistor 318 will be turned on
`to pull the LNB signal to VCCI rapidly without the dv/dt
`limiting effect of resistor 316 described hereinbefore.
`(Id. at 6:15-21.)
`
`47.
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`“[D]uring the second phase turn on with high dv/dt, both the first
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`stage transistors 303 and 313 remain on in parallel with transistors 308 and 318.”
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`(Id. at 6:33-36.)
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 6,195,302
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`48. Thus, the ’302 patent discloses that signal LPB, which controls drive
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`transistor 104, is generated by turning on transistor 303 to pull down LPB, then
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`after a delay, transistor 308 is turned on so that LPB is pulled down via two
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`separate paths corresponding to transistors 308 and 303. (Id. at 6:33-36, FIG. 3.)
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`Signal LNB is generated in an analogous manner using staggered pull-up paths
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`(i.e., a first pull-up path corresponding to transistor 313 is enabled, and then after a
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`delay, a second pull-up path corresponding to transistor 318 is enabled, while the
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`first pull-up path is still enabled). (Id. at 6:33-36, FIG. 3.)
`
`VII. CLAIM CONSTRUCTION
`A.
`“a timer unit having an output coupled to the control electrode and
`generating a control signal”
`
`49.
`
`I have been asked to assume that the “timer unit . . . generating a
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`control signal” recited in claim 1 means “at least a pair of transistors and one or
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`more circuit components that delay a signal and its equivalents.” I have applied
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`this understanding in my analysis.
`
`B.
`
`“a first component within the timer unit causing the control signal
`to change from a first logic level towards a second logic level at a
`first rate”
`
`50.
`
`I have been asked to assume that the “first component . . . causing the
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`control signal to change from a first logic level towards a second logic level at a
`
`first rate” recited in claim 1 means “a first transistor and its equivalents.” I have
`
`applied this understanding in my analysis.
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`Declaration of R. Jacob Baker, Ph.D., P.E.
`U.S. Patent No. 6,195,302
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`C.
`
`“a second component within the timer unit causing the control
`signal to change to the second logic level at a second rate”
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`51.
`
`I have been asked to assume that the “second component . . . causing
`
`the control signal to change to the second logic level at a second rate” recited in
`
`claim 1 means “a second transistor and its equivalents.” I have applied this
`