Paper No. 15
`Trials@uspto.gov
`Filed: April 4, 2018
`571.272.7822
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner,
`
`v.
`
`PROMOS TECHNOLOGIES, INC.,
`Patent Owner.
`____________
`
`Case IPR2017-00038
`Patent 6,195,302 B1
`____________
`
`
`
`Before JAMESON LEE, KEVIN F. TURNER, and
`JOHN A. HUDALLA, Administrative Patent Judges.
`
`TURNER, Administrative Patent Judge.
`
`
`
`FINAL WRITTEN DECISION
`Inter Partes Review
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`
`
`
`Trials@uspto.gov
`Filed: April 4, 2018
`571.272.7822
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner,
`
`v.
`
`PROMOS TECHNOLOGIES, INC.,
`Patent Owner.
`____________
`
`Case IPR2017-00038
`Patent 6,195,302 B1
`____________
`
`
`
`Before JAMESON LEE, KEVIN F. TURNER, and
`JOHN A. HUDALLA, Administrative Patent Judges.
`
`TURNER, Administrative Patent Judge.
`
`
`
`FINAL WRITTEN DECISION
`Inter Partes Review
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
`
`
`
`
`
`
`
`IPR2017-00038
`Patent 6,195,302 B1
`Petitioner, Samsung Electronics Co., Ltd. (“Petitioner”), filed a
`Petition (Paper 2, “Pet.”) requesting an inter partes review of claims 1–6 and
`10–12 of U.S. Patent No. 6,195,302 B1 (Ex. 1001, “the ’302 Patent”)
`pursuant to 35 U.S.C. §§ 311–319. Patent Owner, ProMOS Technologies,
`Inc. (“Patent Owner”), did not file a Preliminary Response. We determined
`that the information presented in the Petition established that there is a
`reasonable likelihood that Petitioner would prevail in challenging claims 1–6
`and 10–12 of the ’302 Patent under 35 U.S.C. §§ 102(b) and 103(a).
`Pursuant to 35 U.S.C. § 314, we instituted this proceeding on April 11,
`2017, as to the challenged claims of the ’302 Patent. Paper 6 (“Institution
`Decision” or “Dec. on Inst.”).
`During the course of trial, Patent Owner filed a Patent Owner
`Response (Paper 10, “PO Resp.”), and Petitioner filed a Reply to the Patent
`Owner Response (Paper 12, “Reply”). The parties filed a “Joint Stipulation
`Regarding Scheduling Order” (Paper 13) in which “the parties waive[d] oral
`argument in this proceeding,” so no oral hearing was held. See Paper 14.
`We have jurisdiction under 35 U.S.C. § 6. This decision is a Final
`Written Decision under 35 U.S.C. § 318(a) as to the patentability of
`claims 1–6 and 10–12 of the ’302 Patent. For the reasons discussed below,
`Petitioner has demonstrated by a preponderance of the evidence that the
`challenged claims are unpatentable.
`
`
`I. BACKGROUND
`
`Related Proceedings
`A.
`Petitioner and Patent Owner indicate that the ’302 Patent has been
`
`asserted by Patent Owner in ProMOS Technologies, Inc. v. Samsung
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`2
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`IPR2017-00038
`Patent 6,195,302 B1
`Electronics Co., Ltd., et al., No. 1:15-cv-898-SLR-SRF (D. Del.). Pet. 1;
`Paper 5, 1. The ’302 Patent is also the subject of another petition, also filed
`by Petitioner, seeking inter partes review of claims 1–6, 10–12, and 14–18
`under different grounds of unpatentability, IPR2017-00039, where a trial
`was instituted in that proceeding as well.
`Petitioner and Patent Owner indicate that these patents are related to
`the ’302 patent: U.S. Patent Nos. 5,761,112; 6,849,897; 6,020,259;
`6,088,270; and 6,699,789. Id. Patent Owner identifies these inter partes
`review proceedings for the related patents: IPR2017-00032 (Patent No.
`6,849,897); IPR2017-00033 and IPR2017-00035 (Patent No. 6,020,259);
`IPR2017-00036 (Patent No. 6,088,270); IPR2017-00037 (Patent No.
`6,699,789); and IPR2017-00040 (Patent No. 5,761,112). Paper 5, 1.
`
`The ’302 Patent
`The ’302 Patent is directed to a random access memory and the
`operations within a random access memory for reading or refreshing
`memory cells, specifically applied to sense amplifiers. Ex. 1001, 1:7–9.
`
`B.
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`IPR2017-00038
`Patent 6,195,302 B1
`The ’302 Patent discloses a memory device with sense amplifiers, as
`illustrated in Figure 1, reproduced below:
`
`
`
`Figure 1 illustrates a memory device according to an embodiment of the
`’302 Patent.
`Sense amplifiers 101a–101c are coupled to high voltage line Vcc and
`ground via driver transistors 104 and 106, respectively. Id. at 4:40–5:4.
`Driver transistors 104, which are PMOS pull-up transistors, and driver
`transistors 106, which are NMOS pull-down transistors, are controlled by
`control signals LPB and LNB, respectively. Id. The ’302 Patent illustrates
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`IPR2017-00038
`Patent 6,195,302 B1
`the functionalities of the sense amplifiers with respect to Figure 2,
`reproduced below:
`
`
`
`Figure 2 illustrates a portion of a memory device according to an
`embodiment of the ’302 Patent.
`The ’302 Patent discloses that storage capacitors 201 are selectively
`coupled to bit lines 202 through access switches 203 in response to address
`signals supplied to word lines 204. Id. at 5:5–9. Prior to a read operation, a
`pair of bit lines 202 are “equalized at some voltage between a logic high and
`a logic low signal,” and a word line (WL) signal is activated. Id. at 5:18–21,
`5:35–37. After the WL signal is activated, “the LPB signal is driven to a
`logic low[,] coupling VCCI to sense amp 101 through drive transistor 104
`[and] [s]imilarly, the LNB signal is driven high to couple sense amp 101 to
`ground or VSS through drive transistor 106.” Id. at 5:38–42. The ’302 Patent
`also provides that “LNB and LPB are generated by a circuit such as that
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`IPR2017-00038
`Patent 6,195,302 B1
`shown in FIG. 3 that generates LNB and LBP both as dual slope signals.”
`Id. at 5:45–47. Figure 3 is reproduced below:
`
`
`
`Figure 3 illustrates timer circuit according to an embodiment of the ’302
`Patent.
`The ’302 Patent discloses that when sensing is to begin, “one of the
`input signals SENR or SENL will go to a logic high,” which causes
`signal 302 to transition to a logic low because of NOR gate 301 and
`inverter 304. Id. at 5:66–6:6. Signal LPB is disclosed as being generated as
`follows:
`
`[S]hortly after either SENR or SENL goes high,
`transistor 303 is turned on pulling the LPB signal low through
`resist[o]r 306. . . . Resistor 316 controls the rate of change or
`dv/dt of LNB while resistor 306 controls the dv/dt of LPB. After
`a delay determined by delay element 307, transistor 308 will be
`turned on pulling LPB to ground with a much lower resistance.
`When transistor 308 is turned on, LPB will fall to the ground
`voltage with a high dv/dt.
`Id. at 6:8–18.
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`6
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`IPR2017-00038
`Patent 6,195,302 B1
`Signal LNB is generated in a similar manner (i.e., a first pull-up path
`corresponding to transistor 313 is enabled, and then after a delay, a second
`pull-up path corresponding to transistor 318 is enabled, while the first pull-
`up path is still enabled), id. at 6:33–36, with both signals, LNB and LPB,
`being generated as “dual slope signals.” Id. at 5:45–47.
`Claims 1 and 10 of the challenged claims of the ’302 Patent are
`independent and reproduced below:
`1. A memory device comprising:
`a plurality of sense amplifiers distributed about an integrated circuit chip,
`each sense amplifier having a power node for receiving current;
`a low-impedance power supply conductor;
`at least one drive transistor having a first current carrying electrode
`coupled to the power supply conductor, a second current carrying
`electrode coupled to the power nodes of a preselected number of the
`sense amplifiers, and a control electrode;
`a control line coupled to the control electrode;
`a timer unit having an output coupled to the control electrode and
`generating a control signal;
`a first component within the timer unit causing the control signal to
`change from a first logic level towards a second logic level at a first
`rate; and
`a second component within the timer unit causing the control signal to
`change to the second logic level at a second rate, wherein the second
`rate is greater than the first rate such that the first component and the
`second component are concurrently activated to cumulatively affect
`the rate of change to the second logic level.
`
`
`10. A sense amplifier clock driver circuit for an integrated circuit
`memory, the driver circuit providing at least one clock signal for
`controlling the operation of sense amplifier driver transistors and
`comprising:
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`IPR2017-00038
`Patent 6,195,302 B1
`a sense control signal node receiving an externally generated sense
`control signal indicating when sensing is to occur;
`a first impedance having a terminal coupled to a selected logic level
`signal;
`a first switch having current carrying electrodes coupled to drive the
`clock signal to a selected logic level through the first impedance, the
`first switch controlled by the sense control signal;
`a delay unit coupled to the sense control signal node and generating a
`delayed sense control signal;
`a second impedance having a terminal coupled to the selected logic level
`signal; and
`a second switch having current carrying electrodes coupled to drive the
`clock signal to the selected logic level through the second impedance,
`the second switch controlled by the delayed sense control signal such
`that the first switch and the second switch are concurrently activated
`after the delayed sense control signal is generated.
`Ex. 1001, 8:11–33, 9:10–34.
`
`C.
`
`Instituted Grounds
`We instituted trial based on the following grounds (Dec. on Inst. 29):
`Reference(s)
`Basis
`Claim(s) Challenged
`
`Seo1 and Min2
`
`Seo
`
`§ 103(a)
`
`§ 102(b)
`
`1–5 and 10–12
`
`10–12
`
`Seo, Min, and Schuster3
`
`§ 103(a)
`
`6
`
`
`1 U.S. Patent No. 5,140,199, issued Aug. 18, 1992 (Ex. 1004, “Seo”).
`2 UK Patent No. GB2246005B, published Aug. 31, 1994 (Ex. 1005, “Min”).
`3 Stanley E. Schuster et al., “A 15-ns CMOS 64K RAM,” IEEE J. of Solid-
`State Circuits, Vol. SC-21, No. 5, pp.704–12 (Oct. 1986) (Ex. 1007,
`“Schuster”).
`
`8
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`IPR2017-00038
`Patent 6,195,302 B1
`
`A.
`
`II. ANALYSIS
`Post-Institution Analysis
`In our Decision on Institution, we concluded that the argument and
`evidence adduced by Petitioner demonstrated a reasonable likelihood that
`claims 1–6 and 10–12 are unpatentable as anticipated or obvious based on
`the challenges identified in the table in Section I.C above. Dec. on Inst. 29.
`We must now determine whether Petitioner has established by a
`preponderance of the evidence that the specified claims are unpatentable
`over the cited prior art. 35 U.S.C. § 316(e). In this regard, we previously
`instructed Patent Owner that “any arguments for patentability not raised in
`the [Patent Owner Response] will be deemed waived.” Paper 7, 3; see also
`In re Nuvasive, Inc., 842 F.3d 1376, 1381 (Fed. Cir. 2016) (holding that
`patent owner’s failure to proffer argument at trial as instructed in scheduling
`order constitutes waiver). Additionally, the Board’s Trial Practice Guide
`states that the Patent Owner Response “should identify all the involved
`claims that are believed to be patentable and state the basis for that belief.”
`Office Patent Trial Practice Guide, 77 Fed. Reg. 48,756, 48,766 (Aug. 14,
`2012).
`Patent Owner’s Response to the Petition is limited to a reservation of
`its rights, noting that the “Supreme Court granted certiorari in Oil States
`Energy Servs., LLC v. Greene’s Energy Grp., LLC, No. 16-712, 2017 WL
`2507340 (U.S. June 12, 2017)” to consider the constitutionality of inter
`partes review proceedings, and Patent Owner reserves its right to argue that
`any ruling be applicable to the instant proceeding. PO Resp. 1. Petitioner
`responds that “Patent Owner does not submit any arguments contesting the
`merits of the Decision or the evidence set forth by Petitioner.” Reply 1. We
`
`9
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`
`
`B.
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`IPR2017-00038
`Patent 6,195,302 B1
`agree that Patent Owner has not contested the instituted grounds and
`evidence. As such, the arguments and evidence presented by Petitioner,
`which we deemed to show a reasonable likelihood of Petitioner
`demonstrating unpatentability of the challenged claims, must now
`demonstrate unpatentability by a preponderance of the evidence.
`
`Level of Ordinary Skill in the Art
`In determining the level of skill in the art, various factors may be
`considered, including the “type of problems encountered in the art; prior art
`solutions to those problems; rapidity with which innovations are made;
`sophistication of the technology; and educational level of active workers in
`the field.” In re GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995) (citing
`Custom Accessories, Inc. v. Jeffrey-Allan Indus., Inc., 807 F.2d 955, 962
`(Fed. Cir. 1986)). In addition, the prior art of record in this proceeding—
`namely, Inoue, Ogawa, and Okamura—is indicative of the level of skill in
`the art. See Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001);
`GPAC, 57 F.3d at 1579; In re Oelrich, 579 F.2d 86, 91 (CCPA 1978).
`With regard to the level of ordinary skill in the art, Petitioner states:
`“A person of ordinary skill in the art at the time of the alleged invention of
`the ’302 patent would have had at least a Bachelor’s degree in electrical
`engineering, or equivalent thereof, and at least two to three years of
`experience in design of semiconductor memory circuits.” Pet. 5. Petitioner
`further states that “[m]ore education can supplement practical experience
`and vice versa.” Id. Petitioner’s position is supported by the Declaration of
`Dr. Baker. Ex. 1002 ¶ 19. We applied this definition of the level of
`ordinary skill in the art in our Institution Decision. See Dec. on Inst. 10.
`
`10
`
`
`
`
`C.
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`IPR2017-00038
`Patent 6,195,302 B1
`We discern no reason to change our determination that Petitioner’s
`proposed definition comports with the qualifications a person would need to
`understand and implement the teachings of the ’302 Patent and the prior art
`of record. Accordingly, we apply Petitioner’s definition of the level of
`ordinary skill in the art.
`
`Claim Interpretation
`In an inter partes review, claim terms in an unexpired patent are
`interpreted according to their broadest reasonable construction in light of the
`specification of the patent in which they appear. See 37 C.F.R. § 42.100(b);
`Cuozzo Speed Techs., LLC v. Lee, 136 S. Ct. 2131, 2142–46 (2016).
`Consistent with that standard, we assign claim terms their ordinary and
`customary meaning, as would be understood by one of ordinary skill in the
`art at the time of the invention, in the context of the entire patent disclosure.
`See In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007).
`There are, however, two exceptions: “1) when a patentee sets out a
`definition and acts as his own lexicographer,” and “2) when the patentee
`disavows the full scope of a claim term either in the specification or during
`prosecution.” Thorner v. Sony Comp. Entm’t Am. LLC, 669 F.3d 1362, 1365
`(Fed. Cir. 2012). It is inappropriate to limit a claim to a preferred
`embodiment without a clear intent in the specification to redefine a claim
`term or a clear disavowal of claim scope. See id. Limitations that are not a
`part of the claim should not be imported into the claim. See SuperGuide
`Corp. v. DirecTV Enters., Inc., 358 F.3d 870, 875 (Fed. Cir. 2004).
`In our Institution Decision, we considered Petitioner’s proposal (see
`Pet. 17–25) to construe specific claim terms according to 35 U.S.C. § 112,
`
`11
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`IPR2017-00038
`Patent 6,195,302 B1
`sixth paragraph. Dec. on Inst. 9–10. We determined that persons of
`ordinary skill in the art would have understood the structures recited in the
`specific claim terms such that those terms would have not been understood
`as nonce words, implicating 35 U.S.C. § 112, sixth paragraph. Id. (citing
`Lighting World, Inc. v. Birchwood Lighting, Inc. 382 F.3d 1354, 1359–60
`(Fed. Cir. 2004)).
`We additionally determined that no claim term required an express
`construction. Id. at 10. In the Institution Decision, however, we initiated
`multiple grounds that might be impacted by a determination as to whether
`the preamble of claim 10 should be seen as limiting of the overall claim
`scope. See id. at 18, 25 (discussing (1) that Seo fails to explicitly disclose
`multiple “sense amplifier driver transistors,” as recited in claim 10, and
`relying on Min for this deficiency, and (2) that Seo may be anticipatory of
`claim 10, if the preamble of that claim is not limiting). Upon institution, we
`presumed that the positions of the parties with respect to the effect of the
`preamble of claim 10 would become clear, but that has not occurred.
`Therefore, we specifically address the nature of the preamble of claim 10,
`and thus the preambles of claims 11 and 12, dependent on claim 10, herein.
`The determination of whether a preamble limits a claim is made on a
`case-by-case basis in light of the facts in each case; there is no litmus test
`defining when a preamble limits the scope of a claim. Catalina Mktg. Int’l
`v. Coolsavings.com, Inc.,289 F.3d 801, 808 (Fed. Cir. 2002). “If the claim
`preamble, when read in the context of the entire claim, recites limitations of
`the claim, or, if the claim preamble is ‘necessary to give life, meaning, and
`vitality’ to the claim, then the claim preamble should be construed as if in
`
`12
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`IPR2017-00038
`Patent 6,195,302 B1
`the balance of the claim.” Pitney Bowes, Inc. v. Hewlett-Packard Co., 182
`F.3d 1298, 1305 (Fed. Cir. 1999).
`The preamble of claim 10 recites: “A sense amplifier clock driver
`circuit for an integrated circuit memory, the driver circuit providing at least
`one clock signal for controlling the operation of sense amplifier driver
`transistors and comprising.” The aspect of that preamble that the at least one
`clock signal provides control for the operation of multiple sense amplifier
`driver transistors is an intended use. We also conclude that the same clock
`signal may be provided to one or more of the sense amplifiers; the
`Specification of the ’302 Patent does not distinguish that the control signals
`differentiate between sense amplifiers or transistors contained therein. Id.
`In addition, the language at issue is not necessary to give life, meaning, or
`vitality to the body and structure of claim 10.
`As such, the at least one clock signal of claim 10 can be used to
`control the operation of a single or multiple sense amplifiers. Tying the use
`of that clock signal to control the operation of multiple sense amplifiers is an
`intended use of claim 10. As well, the remainder of claim 10 does not recite
`or refer to a single or multiple sense amplifiers. As such, we determine that
`the preamble portion “for controlling the operation of sense amplifier driver
`transistors” is not limiting and is of no significance to the construction of
`claim 10.
`We maintain our determination, from the Institution Decision, that no
`other express claim construction is necessary other than the discussion
`above.
`
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`
`D. Obviousness Ground Based on Seo and Min
`Petitioner contends claims 1–5 and 10–12 are obvious over Seo and
`Min. Pet. 25–77. We begin with a review of the references and then address
`Petitioner’s contentions.
`Seo
`1.
`Seo relates to semiconductor memory devices, and more particularly to
`sense amplifier circuitry for sensing data from memory cells. Ex. 1004, 1:7–
`8. Figure 5 of Seo is reproduced below:
`
`
`
`Figure 5 illustrates the circuitry of a sense amplifier driver according to one
`embodiment. Id. at 3:22–23.
`Sensing clock driver 10 generates a signal at node LAG that drives the
`
`gate of the NMOS transistor Ts to a high value, which turns on transistor Ts
`and connects sense amplifier 40 to Vss. Id. at 5:55–58, 7:4–10. Seo
`14
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`IPR2017-00038
`Patent 6,195,302 B1
`discloses that “[i]f a sensing enable state is established by the equalization
`control clock Qeq being at the Vss level and the sensing clock signal Qs
`being at the Vcc level, then node ‘d’ of sensing clock driver 10 [falls] to Vss
`level immediately owing to the function of n-channel MOS transistor Th of
`inverter IV10,” causing transistor Te to immediately turn on. Id. at 6:56–63.
`Seo continues that transistor Ts is not turned on completely because
`transistor Te has a small current driving capability and is unable to pull up
`signal LAG immediately to the Vcc level to completely turn on transistor Ts.
`Id. at 6:63–66. Thereafter, node “e” is lowered to Vss level after having
`been delayed for a certain period due to resistor R3 of inverter IV10 and
`transistor Td turns on. Id. at 6:67–7:4. “Therefore, the potential of node
`LAG raises to Vcc level with a multi-slope characteristics, so that it can
`completely turn on the n-channel MOS sense transistor Ts.” Id. at 7:4–7.
`The resultant sensing signal LAB of the Vss level carries out the sensing
`operation for the data stored in the memory cell. Id. at 7:7–10. This process
`is also illustrated in Figure 6 of Seo, with Petitioner’s annotations,
`reproduced below:
`
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`
`
`See Pet. 13; Ex. 1002 ¶ 56. Figure 6 provides a timing chart illustrating the
`operations of the sense amplifier driver circuit. Id. at 3:24–26.
`
`
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`
`2. Min
`Min describes a “sense amplifier driving circuit which is suitable for
`use in a high density semiconductor memory device.” Ex. 1005, 1:6–8. Min
`discloses a prior art sense amplifier driver circuit in Figure 1A, which is
`reproduced below:
`
`
`
`Figure 1A provides schematic diagram of a first conventional sense
`amplifier driving circuit. Id. at 1:28–29.
`The sense amplifiers SA1–SAn are connected to one another at node
`LAP and at LAN, respectively, and are connected to Vcc and Vss by driving
`transistors Q1 and Q2, respectively. Min discloses a variation of the
`Figure 1A sense amplifier driving circuit arrangement in Figure 1B, which is
`reproduced below:
`
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`Patent 6,195,302 B1
`
`
`
`Figure 1B provides schematic diagram of a second conventional
`sense amplifier driving circuit. Id. at 1:31–32. In this circuit, each
`sense amplifier is provided with its own respective driving transistor,
`with Q1i connected to Vcc and Q2i connected to VSS, as illustrated.
`Min also discloses an improved driver circuit, which is
`reproduced below with a corresponding timing diagram as illustrated in
`Figure 9:
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`
`
`Figure 9 is a schematic circuit diagram of and a timing chart for a sense
`amplifier driving circuit according to one embodiment. Id. at 13:5–9.
`Min details that a dual slope characteristic for signal ϕLAP (voltage at
`node LAP) is achieved by a sequential pull-down approach by which a first
`pull-down path is activated to pull down the voltage at the gate of PMOS
`transistor Q110, and then after a delay a second pull-down path is activated.
`Id. at 29:18–30:3. Min also discloses that “signal ϕSP1 is set to have a high
`level,” which turns on NMOS transistor Q112, and after a certain period of
`time, the second active restore signal ϕSP2 goes to a high level and transistor
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`Q115 is turned on so that the current Icca flowing through the driving
`transistor is increased. Id. at 29:21–34. Turning on transistor Q112
`activates a first pull-down path for pulling down the voltage at the gate of
`transistor Q110, and subsequently turning on transistor Q115 activates a
`second pull-down path for pulling down that same gate voltage. See
`Ex. 1002 ¶ 67.
`Independent claims 1 and 10
`3.
`Following the order of the Petition, we first discuss claim 10, and then
`claim 1. Claim 1 is directed to a memory device, whereas claim 10 is
`directed to a sense amplifier clock driver circuit, which makes up a portion
`of an integrated circuit memory. As such, the discussion of the limitations
`of claim 10 simplifies the discussion with respect to claim 1.
`a. Independent claim 10
`Petitioner asserts that Seo discloses a sensing clock driver 10 (“sense
`amplifier clock driver circuit”) for a CMOS DRAM cell (“integrated circuit
`memory”), the sensing clock driver 10 providing a clock signal at node LAG
`(“at least one clock signal”) for controlling operation of an NMOS transistor
`Ts (“sense amplifier driver transistor”), as shown in Fig. 5. Pet. 25–26
`(citing Ex. 1002 ¶¶ 77–78). Petitioner acknowledges that Seo fails to
`explicitly disclose multiple “sense amplifier driver transistors,” or that they
`are controlled by a single signal, as recited in claim 10, but argues that Min
`discloses multiple sense amplifier driver transistors, and that it would have
`been obvious to one of ordinary skill in the art to implement Seo’s sense
`amplifier clock driver to provide a signal for controlling the operation of
`multiple transistors, as disclosed in Min. Id. at 29–30. Although we
`conclude that the preamble of claim 10 does not limit the claimed driver
`
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`circuit to providing at least one clock signal for controlling the operation of
`multiple sense amplifier driver transistors, see Section II.C, we still credit
`Petitioner’s arguments and evidence that claims 10–12 are obvious over Seo
`and Min.
`Petitioner continues that one of ordinary skill in the art would have
`looked to Min for guidance regarding possible implementations and uses of
`sense amplifier driver circuits, where the latter discloses that the use of and
`control over multiple sense amplifiers would have been conventional, as
`illustrated in Min’s Figures 1A and 1B. Pet. 30–34 (citing Ex. 1002 ¶¶ 85–
`89; Ex. 1005, Figs. 1A, 1B). Additionally, Petitioner asserts that one of
`ordinary skill would have recognized that the modification would have
`improved the performance of Seo’s memory device by increasing the
`number of sense amplifiers as taught by Min, which would have enabled
`Seo’s technique of driving a sense amplifier to be implemented in a memory
`device having many columns of memory cells, as was common at the time
`of the alleged invention of the ’302 Patent. Id. at 35 (citing Ex. 1002 ¶ 91).
`Petitioner also asserts that Seo discloses that a node at the input to
`inverter IV10 (“sense control signal node”) receives sensing clock signal Qs
`(“externally generated sense control signal”) indicating when sensing is to
`occur. Id. at 36 (citing Ex. 1002 ¶¶ 92–95; Ex. 1004, 6:56–7:10). Petitioner
`also argues that one of ordinary skill would have understood that sensing
`clock signal Qs is an “externally generated sense control signal” because it
`is received by and generated externally relative to the sensing clock driver
`10 shown in FIG. 5 of Seo. Id. at 37 (citing Ex. 1002 ¶ 95).
`Petitioner also asserts that Seo discloses that the resistance (“first
`impedance”) of transistor Te has a terminal coupled to Vcc (“a selected logic
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`level signal”). Id. at 37–38 (citing Ex. 1002 ¶¶ 96–101). Petitioner asserts
`as well that one of ordinary skill would have known that every MOSFET has
`associated parasitic resistance and a channel resistance, so that the total
`device resistance of transistor Te is the sum of a parasitic impedance Rsd
`across the source and drain terminals of transistor Te and a channel
`resistance Rch, with the total device resistance of transistor Te equivalent to
`the “first impedance” recited in claim 10. Id. at 38–41 (citing Ex. 1002
`¶¶ 98–101; Ex. 1008, 205–06).
`Petitioner also asserts that Seo discloses that transistor Te (“a first
`switch”) has a source and drain (“current carrying electrodes”) coupled to
`drive the signal on line LAG (“clock signal”) to Vcc (“selected logic level”)
`when transistor Te is turned on by Qs (“sense control signal”) being at Vcc.
`Id. at 42–44 (citing Ex. 1002 ¶¶ 102–105; Ex. 1004, 6:56–66). Petitioner
`also asserts that Seo discloses that a resistance R3 (“delay unit”) that a
`skilled artisan would have understood is coupled, via node d, to the node at
`which Qs is received (“coupled to the sense control signal”), because when
`Qs is at Vcc (high), node d falls to Vss immediately. Id. at 44–46 (citing
`Ex. 1002 ¶¶ 106–109; Ex. 1004, 6:56–61, Fig. 5).
`Petitioner also asserts that Seo discloses that the resistance (“a second
`impedance”) of transistor Td has a terminal coupled to Vcc (“having a
`terminal coupled to the selected logic level signal”), relying on an intrinsic
`impedance of Td, similar to the impedance of Te, discussed above. Id. at
`46–49 (citing Ex. 1002 ¶¶ 110–112; Ex. 1004, Fig. 5). With respect to the
`second switch limitation, Petitioner asserts that Seo discloses that transistor
`Td (“a second switch”) has a source and drain (“current carrying
`electrodes”) coupled to drive the signal on line LAG (“clock signal”) to Vcc
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`(“selected logic level”) when transistor Td is turned on by the delayed sense
`control signal at node e. Id. at 49–52 (citing Ex. 1002 ¶¶ 113–115;
`Ex. 1004, 6:67–7:7, Fig. 5). With respect to the last element of claim 10,
`Petitioner asserts that the signal at node e (i.e., the gate of transistor Td) of
`Seo is a “delayed sense control signal,” as discussed above. Id. at 49–52
`(citing Ex. 1002 ¶¶ 116–118; Ex. 1004, Fig. 5).
`We have reviewed Petitioner’s arguments and the underlying evidence
`cited in support and are persuaded Petitioner sufficiently establishes that the
`combination of Seo and Min teaches all of the limitations of claim 10, and
`that Petitioner has also provided a sufficient rationale to combine Seo and
`Min to account for all the limitations of claim 10. Thus, we determine
`Petitioner has shown by a preponderance of the evidence that claim 10 is
`rendered obvious over the combination of Seo and Min.
`b. Independent claim 1
`With respect to claim 1, as discussed above, Seo discloses a memory
`device, and Min discloses a plurality of sense amplifiers, with each having a
`power node that receives current. Id. at 57–61 (citing Ex. 1002 ¶¶ 123–127;
`Ex. 1004, Abstract, 7:7–10; Ex. 1005, Fig. 1B). Petitioner asserts that one of
`ordinary skill would have understood that the sense amplifiers SA1-SAn of
`Min would have to be “distributed” about the memory device because these
`circuits would be provided in a distributed manner on a circuit chip, and that
`one of ordinary skill would have turned to Min for guidance regarding
`implementation of Seo’s sense amplifier driver circuitry to a plurality of
`sense amplifiers. Id. at 61–63 (citing Ex. 1002 ¶¶ 128–131).
`Further with respect to claim 1, Petitioner asserts that the line
`conducting Vss in both Seo (Ex. 1004, Fig. 5) and Min (Ex. 1005, Fig. 1B)
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`is a “power supply conductor” because one of ordinary skill understood that
`“Vcc” and “Vss” are traditionally used as labels for power supply lines
`corresponding to positive power and ground, respectively. Pet. 64 (citing
`Ex. 1002 ¶ 133). As well, Petitioner asserts that one of ordinary skill would
`have been motivated to use a “low-impedance” power supply conductor
`(e.g., a conductor with a lower parasitic resistance) for the Vss power supply
`conductor given that a high impedance conductor would have caused
`parasitic resistance issues discussed above. Id. at 66 (citing Ex. 1002 ¶ 135).
`The “at least one drive transistor” element of claim 1 is argued by
`Petitioner as being taught by a combination of Seo and Min as illustrated in
`an annotated version of Min’s Figure 1B, which is reproduced below:
`
`
`
`The annotated figure depicts Figure 1B of Min combined with elements of
`Seo. Id. at 67.
`Petitioner asserts that in the combined Seo-Min system, each of
`driving transistors Q21–Q2n (“at least one drive transistor”) has a source
`terminal (“first current carrying electrode”) coupled to Vss (“power supply
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`conductor”), and the drain terminal (“second current carrying electrode”) of
`each transistor Q21–Q2n is coupled to respective latch nodes LAN (“power
`nodes”) of n sense amplifiers SA1–SAn (“preselected number of the sense
`amplifiers”). Id. (citing Ex. 1002 ¶ 137). Petitioner also asserts that each
`transistor Q21–Q2n has a gate terminal (“control electrode”) coupled to the
`LAG signal. Id.
`Further with respect to “a control line,” of claim 1, Petitioner argues
`that the line along which the LAG signal is provided, in the combined Seo-
`Min system, is a “control line.” Id. at 68. With respect to the “timer unit”
`limitation, Petitioner argues that in the combined Seo-Min system, the signal
`at node LAG is generated by clock driver 10 shown in FIG. 5 of Seo that
`includes transistors Td and Te and resistor R3, which delays a signal at
`node d to generate a signal at node e. Id. at 68–69 (citing Ex. 1004, FIG. 5;
`Ex. 1002, ¶ 139). Petitioner regards the transistors Td and Te, and resistor
`R3, as the structure that constitutes the “timer unit,” as it causes a
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