Case IPR2016-01622
`Patent 6,850,414
`Attorney Docket No. 160831-002USIPR
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`KINGSTON TECHNOLOGY COMPANY, INC.,
`Petitioner
`
`v.
`
`POLARIS INNOVATIONS LTD.,
`Patent Owner
`____________
`
`Case IPR2016-01622
`Patent 6,850,414 B2
`____________
`
`PATENT OWNER POLARIS INNOVATIONS LTD.’S
`PRELIMINARY RESPONSE TO PETITION FOR
`INTER PARTES REVIEW OF UNITED STATES PATENT NO. 6,850,414
`PURSUANT TO 35 U.S.C. § 313, 37 C.F.R. § 42.107
`
`
`
`
`
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`
`

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`
`
`
`TABLE OF CONTENTS
`
`I.
`
`II.
`
`INTRODUCTION ....................................................................................... 1
`
`THE ’414 PATENT AND THE ASSERTED REFERENCES. .................... 6
`
`A.
`
`B.
`
`C.
`
`The ’414 Patent’s Goal Is Reducing A Memory Module’s Height. ....................... 6
`
`Simpson Is Directed Towards An Expandable, Flexible PCB With Fillable
`Sockets, Not Reducing The Height Of A PCB. ................................................... 12
`
`The Intel Specification Is Not Directed Towards PCB Height Or Module
`Orientation. ........................................................................................................ 15
`
`III.
`
`SIMPSON IN VIEW OF THE INTEL SPECIFICATION DOES NOT
`RENDER THE CLAIMS OBVIOUS..........................................................18
`
`A.
`
`A Person Of Ordinary Skill In The Art Would Not Be Motivated To Combine
`Simpson With The Intel Specification In A Manner That Would Remedy Their
`Deficiencies. ...................................................................................................... 20
`
`B.
`
`Simpson Does Not Render Claim 1 Obvious. ..................................................... 23
`
`1.
`
`2.
`
`3.
`
`Simpson’s Error Correction Chip Is Not “Identically Designed” With
`“Identically Designed” Housing Relative To The Memory Modules On
`The PCB. ................................................................................................24
`
`Simpson’s Alleged Error Correction Chip Is Not “Connected” To The
`PCB As Claimed. ....................................................................................31
`
`The Petition, Incorrectly Relying On Error “Detection,” Fails To Show
`That Simpson Discloses “One Of Said Semiconductor Memories Being
`Connected As An Error Correction Chip.” .............................................32
`
`C.
`
`D.
`
`E.
`
`Eliminating Simpson’s Second Row Of Sockets And Modules Is Not Obvious
`Because It Would Contravene Simpson’s Goal (Claim 2). .................................. 34
`
`Eliminating Simpson’s Second Row Of Sockets And Modules Is Not Obvious
`Because It Would Contravene Simpson’s Goal (Claim 3). .................................. 37
`
`The Petition Fails To Show That Simpson In View Of The Intel Specification
`Renders Claim 4 Obvious Because It Does Not Show That A POSITA Would
`Be Able To Fit Two Rows Of Sockets In A PCB With A Height Of 1.0-1.2
`Inches. ............................................................................................................... 39
`
`IV. THE INTEL SPECIFICATION DOES NOT RENDER THE CLAIMS
`OBVIOUS. .................................................................................................43
`
`A.
`
`The Board Should Deny Ground 3 Under 35 U.S.C. § 325(d) Because The
`Intel Specification Is Synonymous With The Prior Art Described In The Patent
`And Overcome In Prosecution............................................................................ 44
`
` i
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`

`
`
`
`B.
`
`C.
`
`D.
`
`E.
`
`Petitioner’s Intel Specification Arguments Are Founded On Hindsight Bias,
`And Do Not Articulate Why An Artisan Would Be Motivated To Modify The
`Reference. .......................................................................................................... 49
`
`The Intel Specification Does Not Render Claim 1 Obvious. ............................... 52
`
`The Intel Specification Does Not Render Claim 2 Obvious. ............................... 55
`
`The Intel Specification Does Not Render Claim 3 Obvious. ............................... 55
`
`V.
`
`VI.
`
`THE INTEL SPECIFICATION IN VIEW OF SIMPSON DOES NOT
`RENDER THE CLAIMS OBVIOUS..........................................................57
`
`IF THE BOARD DETERMINES INSTITUTION IS APPROPRIATE, IT
`SHOULD INSTITUTE ONLY ON NON-REDUNDANT GROUNDS. .....58
`
`VII. CONCLUSION...........................................................................................60
`
`
`
` ii
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`

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`
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`COURT DECISIONS
`
`TABLE OF AUTHORITIES
`
`Page(s)
`
`Cadence Pharms., Inc. v. Exela PharmSci Inc.,
`780 F.3d 1364 (Fed. Cir. 2015) ..........................................................................42
`
`Genzyme Corp. v. Transkaryotic Therapies, Inc.,
`346 F.3d 1094 (Fed. Cir. 2003) ..........................................................................42
`
`In re Dembiczak,
`175 F.3d 994 (Fed. Cir. 1999) ............................................................................45
`
`In re Fine,
`837 F.2d 1071 (Fed. Cir. 1988) .................................................................... 45, 47
`
`Interconnect Planning Corp. v. Feil,
`774 F.2d 1132 (Fed. Cir. 1985) .................................................................... 45, 48
`
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (U.S. 2007) ...................................................................................18
`
`
`
`ADMINISTRATIVE DECISIONS
`
`Apple Inc. v. Personalweb Technologies, LLC,
`IPR2013-00596, Paper 9 (P.T.A.B. Mar. 26, 2014)
`(per Turner, APJ) ...............................................................................................52
`
`Baxter Healthcare Corp. v. Millenium Biologix, LLC,
`IPR2013-00590, Paper 9 (P.T.A.B. Mar. 21, 2014)
`(per Osinski, APJ) ..............................................................................................52
`
`Canon Inc. v. Intellectual Ventures I, LLC,
`IPR2014-00535 to -00537, Paper 9 (P.T.A.B. Sep. 24, 2014)
`(per Boucher, APJ) .............................................................................................52
`
`Globus Med. Inc. v. FlexuSpine, Inc.,
`IPR2015-01721, Paper 11 (P.T.A.B. Feb. 24, 2016)
`(Saindon, APJ) ...................................................................................................31
`
` iii
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`

`
`
`
`Heart Failure Techs., LLC v. Cardiokinetix, Inc.,
`IPR2013-00183, Paper 12 (P.T.A.B. Jul. 31, 2013)
`(per Kamholz, APJ) ................................................................................ 19, 31, 43
`
`HTC Corp. v. E-Watch, Inc.,
`IPR2014-00987, Papers 6, 10 (P.T.A.B. Dec. 9, 2014)
`(per Clements, APJ) ...........................................................................................53
`
`Intellectual Ventures Management, LLC v. Xilinx, Inc.,
`IPR2012-00019, Paper 13 (P.T.A.B. Feb. 12, 2013)
`(per Arbes, APJ) .................................................................................................52
`
`OpenTV, Inc. v. Cisco Systems, Inc.,
`IPR2013-00330, Paper 9 (P.T.A.B. Nov. 29, 2013)
`(per Arbes, APJ) .................................................................................................19
`
`Safeway, Inc. v. Kroy IP Holdings, LLC,
`IPR2014-00685, Paper 11 (P.T.A.B. Sep. 11, 2014)
`(per Plenzler, APJ) .............................................................................................51
`
`Toyota Motor Corp. v. Am. Vehicular Scis. LLC,
`IPR2013-00421, Paper 15 (P.T.A.B. Jan. 13, 2014)
`(per Kim, APJ) ...................................................................................................53
`
`
`
`STATUTES
`
`35 U.S.C. § 325(d) ...................................................................................... 4, 37, 43
`
`REGULATIONS
`
`37 C.F.R. § 42.1 ....................................................................................................51
`
`
`
`
`
` iv
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`EXHIBIT LIST
`
`Exhibit 2001
`
`Cara Garretson. “More DRAM vendors involved in Justice
`Department probe.” IDG News Service July 21, 2002.
`Computer World, Inc. November 21, 2016.
`
`Exhibit 2002
`
`Exhibit 2003
`
`Exhibit 2004
`
`“Error Correction Code in SoC FPGA-Based Memory
`Systems.” Altera Corporation April 2012.
`“133 MHz PC SDRAM 64-Bit Non-ECC/Parity 144 Pin
`UNBUFFERED SO-DIMM SPECIFICATION.” Intel, Revision
`1.0C. August 2000
`“PC SDRAM Serial Presence Detect (SPD) Specification.”
`Intel, Revision 1.2B. November 1999.
`
` v
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`
`
`I.
`
`INTRODUCTION1
`
`The ’414 Patent’s entire focus is reducing the height of particular types of
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`memory modules. Specifically, the ’414 Patent concerns conventional memory
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`printed circuit boards (“PCB”) with at least nine identically designed integrated
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`semiconductor memories connected to it, one of which is an error correction chip.
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`The ’414 Patent teaches shifting the orientation of at least eight of the
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`semiconductor memories from a vertical to horizontal orientation while leaving the
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`error correction chip vertical. Rotating the at least eight semiconductor memories
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`horizontally allows for the horizontally oriented elements to be placed closer
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`together in the vertical direction, thereby resulting in an important reduction in the
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`overall PCB height.
`
`Petitioner’s grounds are based on two references: Simpson and the Intel
`
`Specification. Both are peculiar choices. Simpson, unlike the ’414 Patent, is not
`
`directed towards the height of the PCB or the orientation of modules on it. Rather,
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`Simpson’s concern is to supplement conventional PCBs with empty sockets so the
`
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`1 Patent owner presents in this Petition reasons that are more than sufficient
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`to deny institution. If, however, the Board determines that institution would be
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`appropriate, Patent Owner reserves the right to raise additional arguments, and
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`additional supporting evidence and law in support of existing arguments.
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` 1
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`
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`PCB memory can be later expanded by the user. The philosophy behind Simpson
`
`is that, at the time Simpson was filed in 1995, upgrading the DRAM memory on a
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`computer could cost twice as much as a whole computer. Ex. 1002 [Simpson] at
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`11:28-31. Simpson sought to ameliorate this problem by building a PCB packed
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`with as many empty sockets as possible which the user could use to expand the
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`memory or logic capacity of the module. Unlike the ’414 Patent, however,
`
`Simpson has no interest in reducing the height of the PCB or the orientation of the
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`modules. To the contrary, Simpson’s expansive use of sockets would tend to
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`increase the height of the PCB.
`
`Petitioner’s second reference, which it calls the “Intel Specification” is an
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`Intel technical reference document providing the mechanical and electrical
`
`specifications for a particular type of SDRAM (synchronous DRAM) to be
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`incorporated within an Intel based system design. Like Simpson, the Intel
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`Specification also is not concerned with reducing the height of the PCB. Rather,
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`the Intel Specification teaches that it is “important to place each SDRAM in the
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`optimum position to ensure meeting of trace length and topology requirements,”
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`and does not disclose any orientation, design or teaching directed at reducing the
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`height of the PCB. Furthermore, the Intel Specification is not concerned with—
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`and does not teach—orienting eight of nine memory components horizontally and
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`the ninth vertically. Rather, it teaches in various suggested implementations that
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` 2
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`
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`all components, including the error correction chip, are oriented in the same
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`direction.
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`Under its analysis for both grounds 1 (Simpson) and 2 (Simpson in view of
`
`the Intel Specification), the Petition asserts that Simpson alone renders claims 1, 2,
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`5-7 obvious. See Pet. at 16-27. As discussed in Section III.B, infra, the Petition
`
`fails to meet its burden of showing that Simpson renders claim 1—and
`
`consequently, claims 2-8—obvious because Simpson does not disclose that its
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`“error correction chip” is “identically designed” and in “identically designed”
`
`housings in comparison to at least eight other memory modules, that “each one of
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`said semiconductor memories… [is] individually connected to said printed circuit
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`board,” or that “one of said semiconductor memories [is] connected as an error
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`correction chip.” In addition, as discussed in Section III.C, infra, the Petition also
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`fails to meet its burden of showing that Simpson alone renders the additional
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`limitation of claim 2 obvious.
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`The Petition inserts citations from the Intel Specification into its analysis
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`relating to claims 3, 4 and 8 under grounds 1 and 2. See Pet. 31-38, 41-43. The
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`Petition, however, still fails to show that Simpson in view of the Intel Specification
`
`renders those claims obvious. First, as discussed in Section III.A, infra, a person
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`of ordinary skill in the art would not be motivated to combine Simpson with the
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`Intel Specification in a manner that would remedy their deficiencies. In particular,
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` 3
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`
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`for example, a POSITA would not have been motivated to design a system like
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`Simpson around the priority date of the ’414 Patent, because, by that time, the
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`price of DRAM, relative to the price of the rest of the computer, had dropped to
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`about 5% of the price of the computer, and the problem addressed by Simpson had
`
`thus become moot. Second, even if these two references were combined, the
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`Petition fails to show that the combination renders the Claims obvious. Claims 3,
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`4 and 8 depend from claim 1 and fail for the same reasons as claim 1.
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`Furthermore, as discussed in Section III.E, infra, the Petition also fails to show that
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`Simpson in view of the Intel Specification renders the additional limitation of
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`claim 4 obvious for the additional reason that the Petition does not even attempt to
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`show that a POSITA would be able to fit Simpson’s design on a PCB with a height
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`of 1.0-1.2 inches.
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`In its third proposed ground, see Pet. at 9, the Petition asserts that all claims
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`are rendered obvious by the Intel Specification alone. First, for the reasons
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`discussed in Section IV.A, infra, the Board should deny institution on ground(s)
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`based on the Intel Specification under 35 U.S.C. § 325(d) since “substantially the
`
`same” arguments and references were considered and rejected by the examiner
`
`during the prosecution of the ’414 Patent application. In particular, the examiner
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`reviewed and rejected at least seven essentially similar references in detail,
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`disclosing modules that were placed horizontally or vertically similar to the
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` 4
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`

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`
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`arrangements disclosed in the Intel Specification reference. The examiner further
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`considered and rejected at least two other Intel specification documents like the
`
`one presented by the Petition. In this extensive prior art analysis, the examiner
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`rejected arguments substantially the same as those advanced by the Petition here,
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`which were based on references with disclosures that were substantially the same
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`as the disclosures in the Intel Specification reference advanced in the Petition.
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`Consequently, Petitioner’s references and arguments are cumulative to those
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`already considered and rejected by the USPTO in granting the ’414 Patent and
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`should therefore be rejected by the Board.
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`But even if the Board were inclined to consider Petitioner’s grounds relating
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`to the Intel Specification, the Board should also decline to institute on these
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`grounds because they are entirely based on hindsight bias. See Section IV.B, infra.
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`The Petition does not discuss a single reason why a POSITA would be motivated
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`to modify the Intel Specification to disclose the claimed invention. The Petition’s
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`arguments, instead, rest in their entirety on the proposition that a POSITA could
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`make such modifications. That is not sufficient as a matter of law. That a
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`POSITA, given the blueprint of the problem and the blueprint of the solution,
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`could have made the claimed invention is not a proper obviousness analysis.
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`Finally, even if the Board were able to reach the merits of the Petition’s further
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` 5
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`
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`arguments regarding the Intel Specification, these arguments also fail on their
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`merits, as discussed in the Sections IV.C-E, infra.
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`Should the Board determine that institution is proper, it should institute only
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`one of the several requested grounds. The Petition does not even attempt to
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`explain why any of its three requested grounds, see Pet. at 9, may be stronger or
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`weaker compared to the other grounds. And the redundancy in the grounds is
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`manifest. First (in ground 2), the Petition seeks review based on Simpson in view
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`of the Intel Specification. Then (in ground 3), the Petition asserts that the Intel
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`Specification alone renders all claims obvious. The Petition does not even attempt
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`to address how these two grounds are not redundant and should both be instituted.
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`Therefore, the Petition has failed to meet its burden of showing that its requested
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`grounds are not redundant.
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`II.
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`THE ’414 PATENT AND THE ASSERTED REFERENCES.
`
`A. The ’414 Patent’s Goal Is Reducing A Memory Module’s Height.
`
`The ’414 Patent’s focus is reducing the height of particular types of memory
`
`modules. Specifically, the ’414 Patent tackles concerns over conventional memory
`
`printed circuit boards (“PCB”), where all semiconductor memories were
`
`conventionally oriented vertically. See Ex. 1001 [the ’414 Pat.] at, e.g., Fig. 1;
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`2:37-42 (“In the case of this conventional arrangement, in which the edges of the
`
`memory housings lined up along the contact strip are aligned, there is no more
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` 6
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`
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`leeway for a further reduction of the circuit board height”); 2:51-53 (The invention
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`permits “reduc[ing] the height of the printed circuit board still further while using
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`the same memory housings.”); 5:42 (“The dimensions of the housings are
`
`standardized”).
`
`The conventional memory printed circuit board addressed by the ’414 Patent
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`comprises at least nine identically designed integrated semiconductor memories
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`connected to it, and the Patent uses certain features of those circuits, as claimed in
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`combination, to reduce the PCB height beyond what was conventional. Id. at 1:9-
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`14. One of the at least nine identically designed semiconductor memories is
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`connected as an error correction chip. Id. at 1:15-17.
`
`The front side of a conventional, prior art memory PCB is schematically
`
`shown in Fig. 1A of the ’414 Patent, reproduced below. In the figure, yellow is
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`added to depict memory modules, green is added to depict the memory module
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`connected as an error correction chip, and red is added to depict resistors
`
`(discussed below).
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` 7
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`The ’414 Patent teaches that the reason that the semiconductor memories
`
`were oriented vertically in the conventional systems at the time was not accidental,
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`or a mere “design choice that the examiner [of the Patent] failed to recognize,” see
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`Pet. at 5; rather, the reason was that the error correction chip generally had to have
`
`been oriented vertically due to design specifications:
`
`The reason for this arrangement is that one of the semiconductor
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`memories is used as an error correction chip in order to perform error
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`checking on data that will be stored in the rest of the semiconductor
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`memories or that will be read from the memories. The error
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`correction chip is arranged approximately in the center of the contact
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`strip, is arranged above the contact strip, and is arranged vertically,
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`i.e. with the longer dimension of its housing at right angles to the
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`contact strip, because of prescribed lengths of the conductor tracks
`
`which connect the error correction chip to the contact strip.
`
` 8
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`

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`
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`Ex. 1001 [the ’414 Patent] at 1:51-61; see also, id. at 3:15-17 (“the error correction
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`chip is still arranged vertically in order to comply with the specifications for the
`
`conductor track lengths of its leads”).
`
`Separately, the ’414 Patent further recognized that design specifications
`
`required resistors to be placed under each memory module:
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`In each case [in the prior art arrangement], two of these resistors 8
`
`must be arranged between one semiconductor memory 4 and the
`
`contact strip 2, because the upper limit for the length of the leads of
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`the resistors from the contact strip 2 permits no other arrangement.
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`Id. at 5:67-6:4; See also, id. at 2:14-16 (“The resistors require a short connection to
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`corresponding contacts of the contact strip.”). These resistors 8 are schematically
`
`shown in Fig. 1A of the ’414 Patent, shaded in red.
`
`The ’414 Patent further recognized that the error correction chip is the only
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`one of the at least nine identically designed semiconductor memories where there
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`is no need to place passive components between its housing and the contact strip:
`
`However, this semiconductor memory [the error correction chip], and
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`this is something that is exploited according to the invention, is the
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`only one that can be brought still closer to the contact strip, since no
`
`resistors have to be arranged between it and the contact strip.
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`Id. at 3:28-32. See also, id. at 6:28-35 (“However, the housing of the error
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`correction chip is brought up to the contact strip 2 as close as possible. This is
`
`possible because, between the error correction chip or its housing 5b and the
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` 9
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`
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`contact strip 2, there is no need to arrange any passive components. In particular,
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`there is no need for any resistors 8, as in the case of all of the other identically
`
`designed semiconductor memories 4a that are configured horizontally.”).
`
`Incorporating all of the above, the ’414 Patent discloses a new arrangement
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`of components that allows the error correction chip to remain vertical as required
`
`by design specifications, while also reducing the height of the printed circuit board
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`beyond what was conventionally done:
`
`The semiconductor memory used as the error correction chip can be
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`brought up to the contact strip by the distance that is required by the
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`resistors arranged in the outer regions of the contact strip.
`
`This results in a certain, albeit small, narrowing of the printed circuit
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`board. In many cases, however, this suffices to actually enable the
`
`incorporation into network computers.
`
`Id. at 3:38-45. The front side of the preferred embodiment of the new, inventive
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`arrangement is schematically shown in Fig. 3 of the ’414 Patent, reproduced
`
`below, and contains a single row of chips in which four semiconductor memories
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`4a are oriented horizontally with an error correction oriented vertically where the
`
`error correction chip 4b extends vertically beyond the memory modules:
`
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` 10
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`Ex. 1001 [’414 Patent] at 6:41-42 (“As a result, the height of the printed circuit
`
`board can be reduced from a value H1 to a smaller value H2 …”).
`
`The novelty of the ’414 Patent’s invention was also confirmed by the
`
`examiner of the application that issued as the ’414 Patent. In his Notice of
`
`Allowance, the examiner discussed at least seven references in detail, explaining
`
`why they do not disclose the claimed limitations. Ex. 1007 [Prosecution History]
`
`at 10-12 (Notice of Allowance, mailed September 15, 2004). The references
`
`analyzed by the examiner disclosed various features, and in analyzing and rejecting
`
`them, the examiner squarely rejected similar arguments to what Petitioner
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` 11
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`
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`advances here. Id. at, e.g., 11 (rejecting reference (Kasatani) because all nine of its
`
`modules were placed horizontally, and further rejecting a second reference
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`(Michael) because none of its nine horizontally placed modules was connected as
`
`an error correction chip). See also Section IV.A, infra.
`
`B.
`
`Simpson Is Directed Towards An Expandable, Flexible PCB With
`Fillable Sockets, Not Reducing The Height Of A PCB.
`
`Unlike the ’414 Patent, Simpson is not directed at, or even concerned at all
`
`with, the orientation of modules or with the height of the PCB. Simpson’s primary
`
`concern is to supplement conventional PCBs with additional empty sockets so that
`
`the PCB memory can be later expanded by the user. Unlike the ’414 Patent, whose
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`preferred embodiments are directed towards DIMM modules, Simpson is directed
`
`towards SIMM modules. Ex. 1001 [’414 Patent] at 4:34-52; Ex. 1002 [Simpson]
`
`at 5:20-26.
`
`Simpson, a patent application filed in 1995, is from an earlier era of
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`computer DRAM memory relative to 2001 and 2002, the priority and filing dates
`
`of the ’414 Patent, or even 1998, the date of the Intel Specification. Between
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`Simpson’s era and those dates, much changed. Simpson states that at the time of
`
`its invention, “a 16Mb module may cost as much as a whole computer, so
`
`discarding it in favour of one with twice the capacity and price (32 Mb) will in
`
`total effectively cost three times the original.” Id. at 11:28-31. To avoid having to
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`replace a memory module at great cost, Simpson discloses as its invention, an
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` 12
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`
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`upgradable memory module with empty sockets that can later be filled in by the
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`user as their needs change over time. This could be done to increase the available
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`memory of the module, or to add logic components, thereby eliminating the need
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`to discard the old module in favor of a new one. Id. at 11:25-28 (Simpson teaching
`
`that: “Although providing sockets adds to the basic module cost, this additional
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`cost is negligible to that of discarding existing modules and replacing them with
`
`ones of higher capacity.”). See also, id. at 11:3-6 (Simpson teaching that: “A
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`module can be produced with a base level capacity which can then be added to by
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`the user until all sockets are filled, so eliminating the need to completely replace an
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`ordinary module at each stage of upgrading.”); 8:22-24 (teaching that “replacing
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`and throwing away modules each time memory capacity is increased is both costly
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`and wasteful of resources”); 11:8-10 (teaching that “The invention allows the user
`
`to customize the module at the point of use rather than having to use a specific
`
`module configured during its manufacture”).
`
`Simpson’s system is schematically shown in its figure 1 (front view) and
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`figure 3 (rear view), reproduced below, with the color yellow added to demonstrate
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`pre-installed memory modules, and the color green added to demonstrate fillable
`
`sockets:
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` 13
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`
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`In contrast to the ’414 Patent, which is directed towards reducing the height
`
`of the PCB (see ’414 Patent Figs. 2 and 3, Section II.A, supra), Simpson’s design
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`expands the height of the PCB through its use of two rows of sockets on the rear
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`side of the PCB, which together have the effect of increasing the height of
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`Simpson’s PCB as demonstrated in Simpson’s own Figures.
`
`Simpson teaches that, on its PCB front side (fig. 1), the eight horizontally
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`placed elements (in yellow) are eight memories 12a-12h, providing 4Mbits in
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`memory capacity. Id. at 13:18-20. Sockets 14a on the PCB front side, and 14b-14j
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`on the PCB rear side (fig. 3), may be later filled by the user with either memory or
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`logic devices, as the need arises. Id. at 9:34-35 (“Conveniently, the device
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`coupling means enable both memory and logic devices to be mounted.”).
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`As Simpson addresses its one and only concern—a flexible, expandable
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`PCB—it does not discuss or address the height of the PCB, much less seek to
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`reduce it. To the contrary, Simpson is concerned with fitting as many sockets as
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`possible on the PCB. Id. at 15:25-27 (teaching that, for Simpson, “the [module]
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`capacity is limited only by the physical ability to fit sockets or directly mounted
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`memory devices onto a module of given size.”).
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`C. The Intel Specification Is Not Directed Towards PCB Height Or
`Module Orientation.
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`Petitioner’s second asserted prior art reference (the “Intel Specification”)
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`provides the mechanical and electrical specifications for a particular type of
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`SDRAM memory module if such a memory module is to be used in an Intel
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`design. Ex. 1003 [“Intel Specification”] at 7 (“This specification defines the
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`electrical and mechanical requirements for 168-pin, 3.3 volt, 64-bit and 72-bit
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`wide, 4 clock, unbuffered Synchronous DRAM Dual In-Line Memory Module
`
`(SDRAM DIMMs). These SDRAM DIMMs are intended for use as main memory
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`installed on personal computer motherboards.”)
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`The Intel Specification does not address, reference, or relate to the issues
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`discussed in the ’414 Patent. It is not concerned with reducing the height of the
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`PCB. Rather, the Intel Specification teaches that it is “important to place each
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`SDRAM in the optimum position to ensure meeting of trace length and topology
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`requirements”—without disclosing any particular orientation and/or design
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`directed at reducing the height of the PCB. Id. at 34. Furthermore, if the Intel
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`Specification has any teachings concerning the directional orientation of
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`components, it teaches that all components, including the error correction chip, are
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`oriented in the same direction, as demonstrated in the Intel Specification figure on
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`page 34, reproduced below.
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`All Vertical
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`All Horizontal
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`
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`As can be seen from this Intel Specification figure, where there are nine
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`components (SDRAMs) in the case of x 8-bit SDRAMs, or five components in the
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`case of x 16-bit SDRAMS, the components are all placed vertically—including the
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`error correction chip. Where there are three components in the case of x 32-bit
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`SDRAMs, they are all placed horizontally.
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`In fact, the only time that the Intel Specification even hints at orienting the
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`components horizontally (in the case of x 32-bit SDRAMs) in its figure reproduced
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`above, it notes that “[m]odules constructed using x 32 bits SDRAMs are still under
`
`investigation. Additional information will be released when it becomes available.”
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`Id. In other words, the Intel Specification has not even fully studied the case of
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`horizontal placement of modules—let alone taught or suggested placing all
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`modules other than the error correction chip horizontally to reduce the height of the
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`PCB.
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`It is noted that the disclosures in the Intel Specification are similar to the
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`disclosures of numerous references before the examiner during prosecution,
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`including multiple other Intel technical specification documents. Notwithstanding
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`these disclosures, considered during prosecution, the examiner properly found that
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`a photo incidentally showing all modules in a horizontal position does not disclose
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`the detailed limitations of the ’414 Patent. Ex. 1007 [’414 Prosecution History] at
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`10-11.
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`III.
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`SIMPSON IN VIEW OF THE INTEL SPECIFICATION DOES NOT
`RENDER THE CLAIMS OBVIOUS.
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`Under its analysis for both grounds 1 (Simpson) and 2 (Simpson in view of
`
`the Intel Specification), the Petition asserts that Simpson alone renders claims 1, 2,
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`and 5-7 obvious. See Pet. at 16-27. As discussed in Section III.B, infra, the
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`Petition fails to meet its burden of showing that Simpson renders claim 1—and
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`consequently, dependent claims 2-8—obvious because Simpson does not disclose
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`nine “identically designed” memories with “identically designed” housings.
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`Simpson’s putative “error correction chip” is not a memory “identically designed”
`
`or “identically housed” to the other eight putative “identically designed integrated
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`semiconductor memories,” as would be required for Simpson to teach the
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`requirements of the Claims. Second, Simpson’s alleged “error correction chip”
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`would not be “connected” to the PCB as required by claim 1; rather, Simpson’s
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`alleged “error correction chip” is socketed rather than connected to the PCB in
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`order to permit a flexible system that would allow attachment and detachment of
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`memory modules to the sockets. Third, the Petition incorrectly relies on
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`Simpson’s disclosure of error detection to allege that Simpson discloses connecting
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`one of the at least nine semiconductor memories as an error correction chip.
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`As discussed in Section III.C, infra, the Petition fails to meet its burden of
`
`showing that Simpson renders claim 2 obvious for an additional reason, because a
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`POSITA would not be motivated to modify Simpson by removing half of its
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`memory modules and sockets and leave the PCB space unused.
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`In addition to citing Simpson, the Petition inserts citations from the Intel
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`Specification into its analysis relating to claims 3, 4 and 8. See Pet. 31-38, 41-43