`
`
`Case IPR2016-01623
`Patent 7,315,454
`Attorney Docket No. 160831-003USIPR
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`KINGSTON TECHNOLOGY COMPANY INC.,
`Petitioner
`
`v.
`
`POLARIS INNOVATIONS LTD.,
`Patent Owner
`____________
`
`Case IPR2016-01623
`Patent 7,315,454
`____________
`
`PATENT OWNER POLARIS INNOVATIONS LTD.’S
`RESPONSE TO PETITION FOR INTER PARTES REVIEW
`OF UNITED STATES PATENT NO. 7,315,454
`PURSUANT TO 35 U.S.C. §311 AND 37 C.F.R. §42.107
`
`1
`
`KINGSTON 1024
`Kingston v. Polaris
`IPR2016-01622
`
`
`
`
`
`I.
`
`II.
`
`Case IPR2016-01623
`Patent 7,315,454
`Attorney Docket No. 160831-003USIPR
`
`TABLE OF CONTENTS
`
`Pages
`
`INTRODUCTION ........................................................................................ 1
`
`THE ’454 PATENT CONFIRMS THAT CHIP PLACEMENT IS NOT
`A “TILE FITTING PROBLEM.” .............................................................. 4
`
`A. The ’454 Patent’s “Crystallized Objective” Includes Keeping
`Conductor Track Lengths Identical And/Or As Short As Possible. ..... 5
`
`B. DiGiacomo Makes Clear That Chip Placement Is Not A “Tile
`Fitting Problem.” ................................................................................... 7
`
`III. GROUND 1: KIEHL ALONE DOES NOT RENDER ANY OF
`CLAIMS 1-3, 5 OR 7 OBVIOUS. ............................................................. 10
`
`A. Kiehl Does Not Render Obvious The Key Limitation That Chips
`In A Row Be Arranged In An “Alternating Sequence Of Opposite
`Orientations.” ...................................................................................... 11
`
`1. Modifying Kiehl Would Involve Entirely Rebuilding
`Kiehl’s Module Including Moving Nearly Every
`Component On The Board And Rewiring The Entire
`Module. ..................................................................................... 13
`
`2.
`
`3.
`
`4.
`
`Petitioner Has Not Shown A POSITA Would Be Motivated
`To Modify Kiehl. ...................................................................... 18
`
`Kiehl Teaches Away From Any Modification. ........................ 20
`
`Petitioner’s “Rearrangement” And “Design Choice”
`Theories Fail Because Petitioner Fails To Prove That Its
`Radical Revamping Of Kiehl Would Not Affect “The
`Operation Of The Device.” ....................................................... 25
`
`5.
`
`“Common Sense” Cannot Substitute This Key Limitation. ..... 28
`
`
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`Case IPR2016-01623
`Patent 7,315,454
`Attorney Docket No. 160831-003USIPR
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`B. Kiehl’s Chips Are Not “Aligned In The Second Lateral
`Direction.” ........................................................................................... 30
`
`1.
`
`2.
`
`3.
`
`Petitioner Cannot Rely On The Layout Of A Module That It
`Just Dismantled. ........................................................................ 30
`
`Claim Construction: “Aligned In The Second Lateral
`Direction” Should Be Interpreted To Mean “Lying One
`Above Another.” ....................................................................... 32
`
`Petitioner’s Ground Under Kiehl Alone Should Be Rejected
`Because Kiehl’s Chips Are Not “Aligned”. .............................. 36
`
`IV. GROUND 2: KIEHL IN COMBINATION WITH BRIDGE DOES
`NOT RENDER THE PATENT OBVIOUS. ............................................ 37
`
`A. Bridge Is Not Analogous Art. ............................................................. 38
`
`B.
`
`Petitioner Fails To Show Why An Artisan Would Combine
`Bridge With Kiehl “In The Normal Course Of Research And
`Development.” ..................................................................................... 46
`
`C. Even If Bridge Were Combined With Kiehl, Petitioner Has Not
`Explained Why A POSITA Would Utilize The Pinwheel Design. .... 50
`
`V.
`
`GROUND 3: KIEHL IN VIEW OF BRIDGE AND BHAKTA DOES
`NOT RENDER CLAIMS 4 AND 7 OBVIOUS. ...................................... 52
`
`A. An Artisan Would Not Combine Kiehl Or Bridge With Bhakta. ....... 53
`
`B. Bhakta Fails To Disclose The Claimed Rows Of Chips
`“Connected In A Series” (Claim 4). .................................................... 59
`
`C.
`
`Petitioner Has Failed To Prove That Claim 7 Is Obvious Over
`Kiehl And/Or Bhakta. ......................................................................... 64
`
`VI.
`
`SECONDARY INDICIA OF NONOBVIOUSNESS. ............................. 68
`
`VII. CONCLUSION ........................................................................................... 71
`
`
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`ii
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`Case IPR2016-01623
`Patent 7,315,454
`Attorney Docket No. 160831-003USIPR
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`Table of Authorities
`
`Pages
`
`
`
`
`CASES
`
`Apple Inc. v. ITC,
`725 F.3d 1356 (Fed. Cir. 2013) ............................................................................ 68
`
`Arendi S.A.R.L. v. Apple Inc.,
`832 F.3d 1355 (Fed. Cir. 2016) ............................................................................ 29
`
`Belden Inc. v. Berk-Tek LLC,
`805 F.3d 1064 (Fed. Cir. 2015) ............................................................................ 18
`
`Circuit Check, Inc. v. QXQ Inc.,
`795 F.3d 1331 (Fed. Cir. 2015) ............................................................... 38, 39, 46
`
`In re Clay,
`966 F.2d 656 (Fed. Cir. 1992) ....................................................................... 40, 45
`
`In re ICON Health & Fitness,
`496 F.3d 1374 (Fed. Cir. 2007) ............................................................................ 45
`
`In re Japikse,
`181 F.2d 1019 (CCPA 1950) ............................................................................... 26
`
`In re Klein,
`647 F.3d 1343 (Fed. Cir. 2011) ............................................................................ 39
`
`In re Kuhle,
`526 F. 2d 553 (CCPA 1975) ................................................................................ 26
`
`In re Natural Alternatives, LLC,
`659 Fed. Appx. 608 (Fed. Cir. 2016) (nonprecedential) ...................................... 69
`
`In re Paulsen,
`30 F.3d 1475 (Fed. Cir. 1994) .............................................................................. 45
`iii
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`4
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`Case IPR2016-01623
`Patent 7,315,454
`Attorney Docket No. 160831-003USIPR
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`
`KSR Int'l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007). ............................................................................................ 46
`
`K-Tec, Inc. v. Vita-Mix Corp.,
`696 F.3d 1364 (Fed. Cir. 2012) ............................................................................ 38
`
`Leo Pharm. Prods. v. Rea,
`726 F.3d 1346 (Fed. Cir. 2013) ............................................................................ 68
`
`Mintz v. Dietz & Watson, Inc.,
`679 F.3d 1372 (Fed. Cir. 2012) ............................................................................ 68
`
`Panduit Corp. v. Dennison Mfg. Co.,
`810 F.2d 1561 (Fed. Cir. 1987) .............................................................................. 9
`
`Rolls Royce PLC v. United Techs Corp.,
`603 F.3d 1325 (Fed. Cir. 2010) ............................................................................ 14
`
`Unigene Labs., Inc. v. Apotex, Inc.,
`655 F.3d 1352 (Fed. Cir. 2011) ............................................................................ 46
`
`ADMINISTRATIVE DECISIONS
`
`Asetek Danmark A/S v. Coolit Systems, Inc.,
`IPR2015-01276, Paper 17 (PTAB Dec. 8, 2016) ................................................ 26
`
`Intri-Plex Techs., Inc. v. Saint-Gobain Performance Plastics Rencol Ltd.,
`IPR2014-00309, Paper 83 (PTAB Mar. 23, 2015) .............................................. 69
`
`Omron Oilfield & Marine, Inc. v. MD/Totco,
`IPR2013-00265, Paper 11 (PTAB Oct. 31, 2013) ............................................... 69
`
`Parrot SA v. Drone Techs.,
`IPR2014-00732, Paper 29 (PTAB Oct. 20, 2015). .............................................. 38
`
`Phigenix, Inc. v. Immunogen, Inc.,
`IPR2014-00676, Paper 39 (PTAB Oct. 27, 2015) ............................................... 69
`
`
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`Case IPR2016-01623
`Patent 7,315,454
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`
`
`UPDATED EXHIBIT LIST
`
`2001
`
`John P. Bridge, CERAMIC TILE SETTING (1992) [complete copy]
`
`2002
`
`JEDEC Standard No. 79C, Double Data Rate (DDR) SDRAM Specification
`(2003)
`
`2003 Shust & Cobb, “Understanding TI’s PCB Routing Rule-Based DDR Timing
`Specification,” Texas Instruments Application Rpt. (Jul. 2008)
`
`2004
`
`JEDEC Standard JESD79F, Double Data Rate (DDR) SDRAM, (Feb. 2008)
`
`2005 David L. Jones, PCB Design Tutorial, Rev. A (Jun. 29, 2004), available at
`http://alternatezone.com/electronics/files/PCBDesignTutorialRevA.pdf (last
`visited Nov. 18, 2016)
`
`2006 Declaration of William Gervasi
`
`2007 Atera Informatica product page, Kingston 8GB Registered DDR3 Memory
`Module Model KVR13R9D4/8I, available at
`http://www.atera.com.br/produto/13R9D4-
`8I/Mem%C3%B3ria+8GB+1333MHz+DDR3+reg.+ECC+Kingston+KVR13
`R9D4-8I (last visited Nov. 21, 2016)
`
`2008 Newegg product page, Kingston 16GB Registered DDR3 1600 Memory
`Module Model KVR16R11D4/16, available at
`http://www.newegg.com/Product/Product.aspx?Item=N82E16820239275
`(last visited Nov. 20, 2016)
`
`2009
`
`“[Market View] TrendForce Says Contract Price Decline Resulted in 9.1%
`Drop in Global DRAM Revenue for 4Q15,” DRAMeXchange (Feb. 15,
`2016), available at
`
`
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`v
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`6
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`Case IPR2016-01623
`Patent 7,315,454
`Attorney Docket No. 160831-003USIPR
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`http://www.dramexchange.com/WeeklyResearch/Post/2/4291.html
`
`2010 Declaration of Nathan Nobu Lowenstein in Support of Motion for Pro Hac
`Vice
`
`2011 Deposition Transcript of Dr. Vivek Subramanian
`
`2012 Declaration of Dr. Joseph B. Bernstein
`
`2013 Google patents search of “tile fitting problem”
`
`2014 Google search of “dram ‘tile fitting problem’”
`
`2016 Google search of “module ‘tile fitting problem’”
`
`2017 Google search of “semiconductor ‘tile fitting problem’”
`
`2018 Excerpt from THE CHAMBERS DICTIONARY (1998)
`
`2019 Excerpt from AMERICAN HERITAGE COLLEGE DICTIONARY (1997)
`
`2020 Merriam-Webster.com, Definition of “Align” (May 12, 2017), available at
`https://www.merriam-
`webster.com/dictionary/align?utm_campaign=sd&utm_medium=serp&utm_s
`ource=jsonld
`
`2021 Dictionary.com, Definition of “Align” (May 12, 2017), available at
`http://www.dictionary.com/browse/align?s=t
`
`
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`vi
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`Case IPR2016-01623
`Patent 7,315,454
`Attorney Docket No. 160831-003USIPR
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`JEDEC Standard No. 21C Annex E
`
`
`2022
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`vii
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`8
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`
`
`I.
`
`INTRODUCTION
`
`Claims 1-5 and 7 (the “Claims”) of the ’454 Patent should be found
`
`patentable because Petitioner has failed to present any combination of art that
`
`could render the Claims obvious. Among the limitations Petitioner fails to find
`
`prior art for is a key limitation of each claim: “memory chips in each row are
`
`arranged in an alternating sequence of opposite orientations.” Petitioner and its
`
`expert acknowledge that they have found no reference from the semiconductor
`
`field that discloses this limitation. Kiehl, their closest reference, contains two rows
`
`of chips in which all chips in a row are either vertical (the top row) or horizontal
`
`(the bottom row).
`
`Petitioner tells us it would have been obvious to modify Kiehl so as to
`
`practice the alternating orientation limitation because, it says, there are a “finite
`
`number” of ways to arrange chips on a PCB. But Petitioner never identifies what
`
`those ways are, how many there are, or provides any evidence that any of those
`
`ways were known in the art. The assertion is conclusory.
`
`Petitioner also chose to ignore what would be involved in modifying Kiehl.
`
`As Petitioner’s expert, Dr. Subramanian, admitted such a modification would
`
`involve moving almost every element on Kiehl’s module, including nearly every
`
`chip, resistor, and capacitor. Those changes would require a redesign and rewiring
`
`of the myriad electrical connections within the module as well.
`
` 1
`
`9
`
`
`
`
`
`Petitioner offers no convincing motivation for this task. Petitioner contends
`
`that an artisan would be motivated to add “more or larger” chips on memory
`
`module. This makes no sense. The modules in the ’454 Patent and Kiehl both
`
`allow for exactly 36 memory chips and Petitioner presents no evidence that the
`
`’454 Patent’s chips are larger than Kiehl’s.
`
`Petitioner also alleges that the chip layout claimed by the ’454 Patent is a
`
`mere “design choice” and that a novel arrangement of chips is not patentable.
`
`Petitioner skips over the fact that these dramatic architectural rearrangements
`
`fundamentally affect the “operation of the device,” a certainty given the wholesale
`
`reconstruction contemplated. And, if the modification had no operational effect,
`
`why do it in the first place? Petitioner does not address this paradox.
`
`Given the absence of relevant semiconductor art, Petitioner tries to fill the
`
`gap with an obscure reference on laying tiles (Bridge). Bridge is not “reasonably
`
`pertinent to the problem the inventor is trying to solve.” Whereas memory module
`
`designers must consider trace lengths, signal propagation, and a variety of other
`
`electrical and thermal considerations, ceramic tilers are concerned with appearance
`
`and texture considerations that are irrelevant for PCBs ensconced in opaque
`
`casings. Even if bathroom tiles were “analogous art” to memory module design,
`
`no artisan would combine Bridge with Kiehl in “the normal course of research and
`
`development.” Both experts agree: such a thing is unprecedented.
`
` 2
`
`10
`
`
`
`
`
`In search of a logical nexus, Petitioner then plucks a single phrase from
`
`DiGiacomo to suggest that chip placement is a “classical tile fitting problem.” It’s
`
`not. A “classical tile fitting problem” is a mathematical problem unrelated to tiles.
`
`Moreover, DiGiacomo itself makes clear in the next sentence that chip placement
`
`is not a tile fitting problem. There is no intellectually credible path from laying tile
`
`to memory module architecture.
`
`Even if Petitioner were able to get past the “alternating orientation” hurdle,
`
`its arguments would still fail, because they still fail to satisfy the limitation that the
`
`chips are “aligned in the second lateral direction.” As an initial matter,
`
`Petitioner’s entire argument should be rejected because it relies on Kiehl’s module
`
`in its original form before Petitioner dismantled and reassembled it entirely in an
`
`attempt to prove that the “alternating orientation” limitation is present. Having
`
`done that, Petitioner cannot resurrect Kiehl’s defunct layout to demonstrate that the
`
`chips are so “aligned” because, even if they were, that layout of chips no longer
`
`exists under Petitioner’s proffered modification. But even if Petitioner were
`
`permitted to go back and forth in this manner, Petitioner’s argument should still
`
`fail because the claims require that chips that “lie one above the other” do so with
`
`opposite orientations. Kiehl (which has twice as many chips in the top row as the
`
`bottom) does not teach chips in this formation and Petitioner does not contend this
`
`limitation is obvious. This is reason alone to confirm the Claims.
`
` 3
`
`11
`
`
`
`
`
`Petitioner adds Bhakta to its combination for Claims 4 & 7. But Bhakta’s
`
`and Kiehl’s teachings point decisively away from one another and even if Bhakta
`
`were combined with Kiehl, it could not render the missing limitations obvious.
`
`For these reasons, as explained in detail below, and as supported by the
`
`declaration of Professor Joseph Bernstein, an expert with decades of experience
`
`(Ex. 2012), the Board should confirm Claims 1-5 and 7 over Petitioner’s challenge.
`
`II. THE ’454 PATENT CONFIRMS THAT CHIP PLACEMENT IS
`NOT A “TILE FITTING PROBLEM.”
`
`Petitioner’s arguments rest upon the premise that redesigning memory
`
`modules is akin to laying bathroom tiles. This recurrent theme is pervasive in both
`
`the Petition and the accompanying Subramanian declaration:
`
`[T]he problem addressed by the ’454 Patent is not a highly technical
`problem related to semiconductor manufacturing, but a problem
`common to many human experiences related to arranging regularly
`shaped items in a pre-defined area.
`
`Pet. at 14-15 (comparing chip placement to “common tile laying.”); Ex. 1003
`
`[Subramanian Decl.] at ¶24 (“[T]he particular arrangement and orientation of the
`
`memory chips … in my opinion amounts to an elementary geometry problem that
`
`is common in everyday human experience.”).
`
`But memory chips are not bathroom tiles or abstract geometric objects.
`
`DRAM memory modules are exquisitely complicated devices that involve the
`
`balancing of electrical, thermal, structural, and reliability issues and have virtually
`
` 4
`
`12
`
`
`
`
`
`nothing in common with ceramic tiles. Ex. 2012 [Bernstein Decl.] at ¶37-40
`
`(modern printed circuit board designs can have 16 or more wiring layers and the
`
`wiring in the PCB can be more complex than inside a chip). This is made
`
`expressly clear by the ’454 Patent, and also in each of Petitioner’s semiconductor
`
`references. The notion that chip placement is a “tile fitting problem” is
`
`demonstrably false.
`
`A. The ’454 Patent’s “Crystallized Objective” Includes Keeping
`Conductor Track Lengths Identical And/Or As Short As Possible.
`
`Contradicting the “tile-laying” vision of memory module design, the ’454
`
`Patent teaches the importance of conductor track lengths between chips that are
`
`identical in length and as short as possible, not for the purpose of a visually
`
`pleasing unit, but to ensure uniform and short signal propagation times:
`
`Moreover, when arranging the memory chips, care must be
`taken to ensure that an arrangement is found which exhibits the
`occurrence of signal propagation times that are as uniform as
`possible to all of the semiconductor memory chips in conjunction with
`conductor track lengths that are, to the greatest extent possible,
`identical in length. Meanwhile, the conductor track lengths are also
`desired to be as short as possible to keep the signal propagation
`times as short as possible.
`Accordingly, it would be desirable to have a semiconductor
`memory module that can be equipped with comparatively large
`rectangular semiconductor memory chips, e.g., DDR3-DRAM
`
` 5
`
`13
`
`
`
`
`
`memory chips, in two rows lying one above another, with the
`conductor tracks to the respective semiconductor chips being
`identical in length and as short as possible.
`
`Ex. 1001 [’454 Patent] at 2:1-16. Petitioner’s expert recognized that the second
`
`paragraph quoted above states the “crystallized objective” of the ’454 patent. Ex.
`
`2011 [Subramanian Depo.] at 103:5-10; see also Ex. 2012 [Bernstein Decl.] at ¶49
`
`(“[T]he ’454 Patent has three objectives: 1) equip a standard-sized memory module
`
`with comparatively large rectangular memory chips, 2) keep conductor (line)
`
`tracks identical in length, and 3) keep conductor tracks as short as possible.”).
`
`
`
`The patent discloses several techniques to carry out these objectives. See,
`
`e.g., Ex. 1001 [’454 Pat.] at 7:36-8:13 (discussing the identical track lengths
`
`between chips in FIGs. 5-7). This is demonstrated in each of FIGs 5-7, which
`
`specify 21.0mm track lengths between chips:
`
`
`
`Notwithstanding these disclosures, Subramanian seemed unwilling to
`
`acknowledge the Patent’s focus on routing. Ex. 2011 [Subramanian Depo.] at
`
`
`
` 6
`
`14
`
`
`
`
`
`65:6-14 (testifying that the ’454 Patent “doesn’t really spend any discussion on …
`
`the routing issues.”).
`
`
`
`The significance of track length is a key consideration in memory module
`
`design. See Ex. 2012 [Bernstein Decl.] at ¶41-42 (describing the role line tracks
`
`play in memory design). This is apparent not just from reviewing the ’454 Patent,
`
`but also from Petitioner’s references Kiehl, Bhakta, and DiGiacomo. See, e.g., Ex.
`
`1014 [Kiehl] at ¶0008 (“The problem addressed by the present invention is of
`
`providing a memory module, wherein a plurality of DRAMs can be accommodated
`
`while preserving low height and short signal paths.”); Ex. 1007 [Bhakta] at 4:37-
`
`44 (“[T]he trace lengths to the data pins on the integrated circuits 102 in the first
`
`(upper) row have substantially the same length as the signal traces to the data pins
`
`on the integrated circuits 102 in the second lower row.”); see also, id. at 4:54-60,
`
`4:66-5:14, and 7:46-49; Ex. 1011 [DiGiacomo] at 7:56-8:12 (“Components have to
`
`be placed in such a way that the probability of wiring those components based on
`
`the resultant placement is optimized… . Due to physical and electronical
`
`constraints, some nets are more critical than others and must be kept as short as
`
`possible.”).
`
`B. DiGiacomo Makes Clear That Chip Placement Is Not A “Tile Fitting
`Problem.”
`
`Petitioner and its expert assert that “fitting computer chips within the fixed
`
`confines of a printed circuit board is known as the ‘tile fitting problem.’” Pet. at
`
` 7
`
`15
`
`
`
`
`
`13. Petitioner’s expert justified his reliance upon a book on ceramic tiles for a
`
`kitchen or bathroom based upon the notion that the “industry uses the phrase ‘tile
`
`fitting problem’…” Ex. 1003 [Subramanian Decl.] at ¶32.
`
`This is not true. So far as the record shows, the only time this phrase has
`
`ever been used in connection with semiconductors or memory modules is a single
`
`statement in DiGiacomo. See Pet. at 13-14, 15, 17, 27 and 47 (citing only
`
`DiGiacomo); Ex. 1003 [Subramanian Decl.] at ¶32 (same); Ex. 2011 [Subramanian
`
`Depo.] at 29:21-30:1 (“Q. And the only instance in the semiconductor arts where
`
`you’ve ever identified a reference to placing elements on a board as a tile-fitting
`
`problem is DiGiacomo, correct? A. That is the art I cite to that says that. That’s
`
`true.”); see also Ex. 2012 [Bernstein Decl.] at ¶55 (“I have no personal recollection
`
`of anyone referring to the placement of components on a PCB as a ‘tile-fitting
`
`problem.’”).
`
`DiGiacomo is the only reference cited to support the “tile fitting” assertion
`
`because it appears to be the only time the phrase “tile fitting problem” has been
`
`used in connection with semiconductors. Ex. 2013 [Google Patents Search]
`
`(revealing DiGiacomo as the only patent using the phrase “tile fitting problem”);
`
`see also Ex. 2011 [Subramanian Depo] at 30:2-16 (cannot recall reading any
`
`articles on the “tile fitting” problem of placing chips on a board); 103:17-104:5
`
`(not aware of any other patents referring to a “tile fitting problem”). Google
`
` 8
`
`16
`
`
`
`
`
`searches for “tile fitting problem” and any of “DRAM,” “module,” and
`
`“semiconductor” only drew up a link to the Institution Decision in this IPR,
`
`DiGiacomo, and scores of ads for home repair and tile contracting services. Exs.
`
`2014-2016.
`
`Remarkably, DiGiacomo itself expressly rejects the notion that placing
`
`components on a board is a “classical tile fitting” problem. Instead, DiGiacomo
`
`recognizes the technical difficulties inherent in module design and affirmatively
`
`states that “placing components on a card is more complex than the classical tile
`
`fitting problem.” Ex. 1011 [DiGiacomo] at 7:56-57; see also Ex. 2012 [Bernstein
`
`Decl.] at ¶99. In an obviousness analysis, references must be read as a whole, not
`
`in a manner at odds with the reference itself. Panduit Corp. v. Dennison Mfg. Co.,
`
`810 F.2d 1561, 1568 (Fed. Cir. 1987) (“[A] prior patent must be considered in its
`
`entirety, i.e., as a whole, including portions that would lead away from the
`
`invention in suit.”).
`
`DiGiacomo continues to explain that placing components on a board
`
`involves the considerations, inter alia, of optimizing the wiring and ensuring that
`
`critical nets are “as short as possible” and ensuring that components are placed
`
`“where a correct voltage is supplied.” Ex. 1011 [DiGiacomo] at 7:52-8:20.
`
`Indeed, much of DiGiacomo is devoted to discussing such considerations. See,
`
`e.g., id. at 8:13-29; 8: 29-49; 10:54-64; 11:22-13:16; 13:30-53; 14:54-15:2;18:11-
`
` 9
`
`17
`
`
`
`
`
`43; see also, Ex. 2012 [Bernstein Decl.] at ¶100; id. at ¶106-107 (wiring of line
`
`tracks is critical to DiGiacomo).
`
`Even DiGiacomo’s definition of a “classical tile fitting problem” confirms
`
`its inapplicability. DiGiacomo defines a “classical tile fitting problem” as “the
`
`problem of optimally packing a plurality of differently shaped tiles 31 into a
`
`predefined area 32.” Ex. 1011 [DiGiacomo] at 7:52-55. Both Kiehl and the ’454
`
`Patent concern DRAM memory modules with identically (not differently) shaped
`
`memory chips (not tiles).
`
`Much of Petitioner’s analysis is founded on the premise that chip placement
`
`and module design, at least as far as the ’454 Patent is concerned, are mere “tile
`
`fitting problems.” As discussed, this foundation is infirm.
`
`III. GROUND 1: KIEHL ALONE DOES NOT RENDER ANY OF
`CLAIMS 1-3, 5 OR 7 OBVIOUS.
`
`Kiehl alone does not render the ’454 Patent obvious because it lacks two
`
`fundamental limitations of the Claims and fails to prove they are obvious: (a) “the
`
`memory chips in each row are arranged in an alternating sequence of opposite
`
`orientations with the longer dimension of each memory chip being parallel with
`
`the shorter dimension of adjacent memory chips in the same row…”; and (b)
`
`“aligned in the second lateral direction.” These failings are addressed below.
`
` 10
`
`18
`
`
`
`
`
`A. Kiehl Does Not Render Obvious The Key Limitation That Chips In
`A Row Be Arranged In An “Alternating Sequence Of Opposite
`Orientations.”
`
`Perhaps the central limitation of the Claims is the limitation requiring that
`
`“the memory chips in each row are arranged in an alternating sequence of
`
`opposite orientations with the longer dimension of each memory chip being
`
`parallel with the shorter dimension of adjacent memory chips in the same row…”
`
`Ex. 1001 [’454 Pat.] cl. 1; see also, id. at 2:48-58; Ex. 2012 [Bernstein Decl.] at
`
`¶50.
`
`This limitation is demonstrated in each embodiment of the ’454 Patent.
`
`Figure 2 is exemplary:
`
`
`
`Petitioner’s expert begrudgingly acknowledges that this is a potentially
`
`“new” aspect of the invention and agreed that this limitation is a focal point of the
`
`parties’ dispute or “where the action is.” Ex. 1003 [Subramanian Decl.] at ¶24; Ex.
`
`2011 [Subramanian Depo.] at 99:25-100:10.
`
` 11
`
`19
`
`
`
`
`
`Kiehl clearly does not teach this limitation, as it places all of the chips in
`
`particular rows oriented in the same direction. Ex. 2012 [Bernstein Decl.] at ¶75.
`
`Petitioner concedes that this limitation is not met in its lead reference, Kiehl. Pet.
`
`at 24; Ex. 1003 [Subramanian Decl.] at ¶56; Institution Decision at 9; Ex. 2011
`
`[Subramanian Depo.] at 25:14-22.
`
`As shown below, Kiehl’s top row of chips are all vertical and its bottom row
`
`are all horizontal:
`
`Top row: all vertical
`
`Bottom row: all horizontal
`
`
`
`Ex. 1014 [Kiehl] at Fig. 1; Ex. 2012 [Bernstein Decl.] at ¶76-77 (describing Kiehl).
`
`Petitioner and its expert were unable to locate any prior art from the
`
`semiconductor field that teaches chips in a row with alternating orientations:
`
`Q
`
`[Y]ou have not identified any reference in the semiconductor
`field that teaches memory chips in a row with alternating
`orientations, correct?
`
` 12
`
`20
`
`
`
`
`
`A. That’s correct. I have not done that with memory chips in a
`row.
`See, e.g., Ex. 2011 [Subramanian Depo.] at 28:11-15. The only reference that
`
`allegedly demonstrates this arrangement is a 25-year-old do-it-yourself home
`
`ceramic tiling book authored by Bridge, a ceramic tile contractor. Id. at 28:16-22.
`
`While Petitioner concedes this key limitation is new, Petitioner nonetheless
`
`contends that the limitation is obvious over Kiehl alone. For the reasons detailed
`
`below, Petitioner’s arguments fail.
`
`1. Modifying Kiehl Would Involve Entirely Rebuilding Kiehl’s
`Module Including Moving Nearly Every Component On The
`Board And Rewiring The Entire Module.
`
`Petitioner contends that “the problem addressed by the ’454 Patent is not a
`
`highly technical problem … but a problem common to many human experiences
`
`related to arranging regularly shaped items in a pre-defined area.” See Pet. at 14
`
`This is not true. As discussed in Section II.A, supra, the ’454 Patent teaches that
`
`one of its “core objectives” is maintaining conductor tracks between
`
`semiconductor chips that are “identical in length and as short as possible.” In the
`
`face of the ’454 Patent’s teachings, and those in other cited semiconductor patents,
`
`Petitioner’s attempt to trivialize the issues implicated in the architecture of memory
`
`modules makes it impossible to take seriously Petitioner’s assurance that it would
`
`have been obvious to modify Kiehl to find the key limitation of the ’454 Patent.
`
` 13
`
`21
`
`
`
`
`
`Petitioner sheds no light on what would actually be involved in modifying
`
`Kiehl. Instead, it offers the following conclusory statement:
`
`[I]t would have been obvious to a skilled artisan to rearrange the
`memory chips in Kiehl’s memory module into such a configuration
`because there are only a finite number patterns [sic] in which
`rectangular chips can be arranged on a PCB.
`
`Pet. at 24. Petitioner’s expert copies this statement—including the typographical
`
`error—verbatim. Compare with Ex. 1003 [Subramanian Decl.] at ¶56.
`
`As an initial matter, the suggestion that there are a “finite number of
`
`patterns” in which to place chips is empty rhetoric. Patentees are not required to
`
`prove that alternatives are infinite. Petitioner is obliged to prove that they are
`
`finite—indeed, that there are a very small number of identified and predictable
`
`solutions. See Rolls Royce PLC v. United Techs Corp., 603 F.3d 1325, 1339 (Fed.
`
`Cir. 2010) (“The important question is whether the invention is an ‘identified,
`
`predictable solution’ and an ‘anticipated success.’”) (rejecting a finding of
`
`obviousness when possible solutions were not known or finite).
`
`Petitioner and Subramanian do not tell the Board what this “finite number of
`
`patterns” might be, much less identify them, nor do they discuss what the
`
`advantages or disadvantages of different arrangements are. They most certainly do
`
`not demonstrate that these arrangements were already “known” in the art. Dr.
`
`Bernstein conducted his own analysis comparing hypothetical modules based off
`
` 14
`
`22
`
`
`
`
`
`Kiehl, Bhakta, and the ’454 and concluded that it would not have been possible to
`
`determine which was optimal without trying each arrangement. Ex. 2012
`
`[Bernstein Decl.] at ¶¶59-66.
`
`And this rearrangement was most certainly not known because rearranging
`
`Kiehl so as to place chips in a row with alternating orientations would involve
`
`moving nearly every element on Kiehl’s module, including nearly every chip
`
`package, resistor, and capacitor. Ex. 2012 [Bernstein Decl.] at ¶44 (“Each small
`
`change in placement results in a near complete re-design of the whole board.”); id.
`
`at ¶83 (“[T]o place [Kiehl’s] chips in a row in an alternating orientation, nearly
`
`every chip, capacitor and resistor would need to be moved and nearly every
`
`element would need to be rewired.”).
`
`Dr. Subramanian was forced to admit as much and acknowledged that,
`
`considering just the left portion of one side of Kiehl, every element other than chips
`
`2 and 7 would need to be moved to have Kiehl practice the pinwheel pattern. Ex.
`
`2011 [Subramanian Depo.] at 63:24-64:15; at 60:4-8 (resistors would move); at
`
`61:15-62:11 (same); at 40:3-41:13 (capacitors would move); see also Ex. 2012
`
`[Bernstein Decl.] at ¶84 (moving pins); ¶85 (moving line tracks); ¶86-87 (moving
`
`passive components).
`
`
`
`
`
` 15
`
`23
`
`
`
`
`
`
`
`
`
`Subramanian’s Testimony: Elements in Kiehl’s left side of the
`module that would need to move to create the “pinwheel”
`
`
`
`The same effort would need to be taken on Kiehl’s right as well. Ex. 2011
`
`[Subramanian Depo.] at 88:10-89:21. The chain reaction caused by moving just
`
`one chip is revealing:
`
`Q.
`
`A.
`Q.
`
`A.
`
`So just to move this one chip, chip 3, you’re going to have to
`also move chip 6, correct?
`In this layout, yes, that’s right.
`So you’re going to have to move the capacitors that are placed
`between chip 3 and chip 6, and you’re going to have to move
`chip 6 just to move chip 3 horizontally, correct?
`In your hypothetical where I’m rotating chip 3, yes, that’s true.
`
` 16
`
`24
`
`
`
`
`
`Ex. 2011 [Subramanian Depo.] at 40:16-41:13.
`
`Dr. Subramanian also acknowledged that these changes would necessitate a
`
`rewiring of the PCB. See, e.g., id. at 64:16-24. Shifting chips from a ve
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