United States Patent
`[19]
`[11] Patent Number:
`5,973,951
`
`Bechtolsheim et al.
`[45] Date of Patent:
`*Oct. 26, 1999
`
`U8005973951A
`
`[54]
`
`SINGLE IN-LINE MEMORY MODULE
`
`FOREIGN PATENT DOCUMENTS
`
`[75]
`
`Inventors: Andreas Bechtolsheim, Stanford;
`Edward Frank, Portola Valley, James
`TeStaz Mountam V16)”; Shawn Storm
`ML VleW: all Of Cahf
`
`[73] Assignee: Sun Microsystems, Inc., Palo Alto,
`Calif.
`
`[*l
`
`NOtiCCI
`
`This patent issued on a continued pros-
`ecution application filed under 37 CFR
`1.53(d), and is subject to the twenty year
`patent
`term provisions of 35 U.S.C.
`154(a)(2).
`
`This patent is subject tO a terminal dis-
`claimer.
`
`[21] Appl. No.: 08/878,705
`
`[22]
`
`Filed:
`
`Jun. 19, 1997
`
`Related US. Application Data
`
`[63] Continuation of application No. (18/643,094, May 2, 1996,
`abandoned, which is a continuation of application No.
`08/473,073, Jun. 7, 1995, Pat. No. 5,532,954, which is a
`continuation of application No. 08/345,477, Nov. 28, 1994,
`Pat. No. 5,465,229, which is a continuation of application
`No. 08/279,824, Jul. 25,. 1994, Pat. No. 5,383,148, which is
`a continuation Of application NO. 08/115,438, Sep. 1, 1993,
`abandoned, which is a continuation of application No.
`07/886,413, May 19, 1992, Pat. No. 5,270,964.
`
`
`""""" G11C 13/00
`
`365/52; 365/51; 365/59;
`365/63
`[58] Fleld of Search .................................. 365/52, 51, 58,
`365/63» 59
`
`[56]
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`.
`.
`Przmary Exammer—Tan T. Nguyen
`Attorney, Agent, or Firm—Conley, Rose & Tayon, PC, B.
`Noel KiVlil‘l
`
`[57]
`
`ABSTRACT
`
`for memory
`A single in-line memory module (SIMM)
`expansion in a computer system. The SIMM includes a
`plurality of memory chips surface-mounted on a printed
`circuit board. The printed circuit board includes a dual
`read—out connector edge adapted for
`insertion within a
`socket of the computer system. One or more driver chips
`may further be mounted on the printed circuit board and
`connected to distribute control signals to the memory chips.
`Afull-width data path may further be connected between the
`dual read-01H connector edge and the plurality of memory
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`
`(List continued on next page.)
`
`51 Claims, 6 Drawing Sheets
`
`KINGSTON 1018
`
`Kingston v. Polaris
`|PR2016-01622
`
`/5
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`1PIN #199
`
`
`50A
`50R
`
` 1
`
`1
`
`KINGSTON 1018
`Kingston v. Polaris
`IPR2016-01622
`
`

`

`5,973,951
`
`Page 2
`
`U.S. PATENT DOCUMENTS
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`
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`'
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`
`

`

`5,973,951
`
`Page 3
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`
`3
`
`

`

`5,973,951
`Page 4
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`(May 1991), (4 pages).
`AMP Product Specification (Tentative
`pages).
`AMP Customer Drawing 90—1439—24, (2 pages).
`AMP Customer Drawing 91—1793—1, (2 pages).
`Top, bottom and side views of Atari CX853 Memory Mod-
`ule (color copy), (:1 page).
`Top and bottom views Printed Circuit Board of Atari CX853
`(color copy), (1 page).
`Sams Computerfacts Technical Service Data, Atari Model
`800 Computer, (41 pages).
`Rockwell R650X and R651X Microprocessors (CPU) Data
`Sheet, (16 pages).
`54ACQ/74ACQ244—54ACTQ/
`National Semiconductor
`74ACTQ244 Quiet Series Octal Buffer/Line Driver with
`Tri—State Outputs, (10 pages).
`Texas Instruments, SN54157 Data Sheet, (8 pages).
`Texas Instruments, SN5410 Data Sheet, (1 page).
`Texas Instruments, TMS4116 16, 348—Bit Dynamic Ran-
`dom—Access Memory Data Sheet, (14 pages).
`Top and bottom views of Commodore VIC—1111 16K RAM
`Cartridge, (1 page).
`Top and bottom views of printed circuit board of Commo-
`dore VIC—1111 16K RAM Cartridge, (1 page).
`Sams Computerfacts Commodore Model VIC 20, 1984, (22
`pages).
`Sams Computerfacts Commodore Model VIC 20 (Early
`Version), 1985, (17 pages).
`National Semiconductor 54LS138 Decoders/Demultiplexers
`Data Sheet, (8 pages),
`Hitachi HM6116 Series Data Sheet, (5 pages).
`Front and back views of DEC MS44—AA memory module
`(color copy), (1 page).
`Texas Instruments SN54AL81034 Hex Drivers Data Sheet,
`(6 pages).
`Siemens HYB 511000BJ—50/60/70 Data Sheet, (22 pages).
`Digital DECdirect Desktop Edition, Winter/Spring 1991
`(excerpts), (14 pages).
`Front and back views of Kingston Technology memory
`boards for HP Apollo 9000 Series 700 computers, (2 pages).
`Kingston Technology KTH700/16, /32, /64 & /128 memory
`upgrade kits, documentation, (3 pages).
`CE Handbook HP Apollo 9000 Series 700 Workstation/
`Servers, (247 pages).
`
`4
`
`

`

`US. Patent
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`Oct. 26, 1999
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`US. Patent
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`Oct. 26, 1999
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`Sheet 3 0f 6
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`5,973,951
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`US. Patent
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`Oct. 26, 1999
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`US. Patent
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`Oct. 26, 1999
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`US. Patent
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`Oct. 26, 1999
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`Sheet 6 0f 6
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`5,973,951
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`

`5,973,951
`
`1
`SINGLE IN-LINE MEMORY MODULE
`
`This is a continuation application of Ser. No. 08/643,094,
`filed May 2, 1996 now abandoned which is a continuation of
`Ser. No. 08/473,073, filed Jun. 7, 1995, now U.S. Pat. No.
`5,532,954 issued Jul. 2, 1996, which is a continuation of Ser.
`No. 08/345,477 filed Nov. 28, 1994, now U.S. Pat. No.
`5,465,229 issued Nov. 7, 1995, which is a continuation of
`Ser. No. 08/279,824, filed Jul. 25, 1994, now U.S. Pat. No.
`5,383,148 issued Jan. 17, 1995, which a continuation of Ser.
`No. 08/115,438, filed Sep. 1, 1993, now abandoned, which
`is a continuation of Ser. No. 07/886,413, filed May 19, 1992,
`now U.S. Pat. No. 5,270,964, issued on Dec. 14, 1993.
`BACKGROUND OF THE INVENTION
`
`1. Related Applications
`This application is related to U.S. Pat. No. 5,260,892,
`entitled “High Speed Electrical Signal Interconnect
`Structure”, issued Nov. 9, 1993 and U.S. Pat. No. 5,265,218,
`entitled ‘Bus Architecture for Integrated Data and Video
`Memory’, issued Nov. 23, 1993.
`2. Field of the Invention
`
`The present invention relates to the field of computer
`systems and memory hardware. More particularly,
`the
`present invention relates to modular circuit boards which
`may be combined to form a memory structure within a
`computer system.
`3. Art Background
`Single In-Line Memory Modules (“SIMMs") are compact
`circuit boards designed to accommodate surface mount
`memory chips. SIMMs were developed to provide compact
`and easy to manage modular memory components for user
`installation in computer systems designed to accept such
`SIMMs. SIMMs generally are easily inserted into a connec-
`tor within the computer system, the SIMM thereby deriving
`all necessary power, ground, and logic signals therefrom.
`A SIMM typically comprises a multiplicity of random
`access memory (“RAM") chips mounted to a printed circuit
`board. Depending on the user’s needs, the RAM memory
`chips may be dynamic RAM (DRAM), non volatile static
`RAM (SRAM) or video RAM (VRAM). Because DRAM
`memories are larger and cheaper than memory cells for
`SRAMs, DRAMs are widely used as the principal building
`block for main memories in computer systems. SRAM and
`VRAM SIMMs have more limited application for special
`purposes such as extremely fast cache memories and video
`frame buffers, respectively. Because DRAMs form the larg-
`est portion of a computer system memory, it is therefore
`desirable that memory modules flexibly accommodate the
`computation needs of a user as the users’
`rcquircmcnts
`change over time. Moreover, it is desirable that the SIMM
`modules may be added to the computer system with a
`minimum user difficulty, specifically in terms of configura—
`tion of a SIMM within a particular memory structure. In the
`past, SIMMs have generally been designed to provide
`memory increments of one or more megabytes (MB), but
`where the memory addition comprises only a portion of the
`full data path used in the computer system. A leading
`example of the prior art organization and structure is that
`disclosed in U.S. Pat. No. 4,656,605, issued Apr. 7, 1987 to
`Clayton. Clayton discloses a compact modular memory
`circuit board to which are mounted nine memory chips
`which are arranged to provide memory increments in eight
`bit (one byte) data widths, plus parity bits. Thus, because
`most computer systems use data paths of 32, 64 or more bits,
`the SIMM constructed according to Clayton cannot provide
`
`5
`
`10
`
`15
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`a memory increment for the entire data path. Instead the user
`must obtain and install multiple SIMMs,
`in combination
`with performing any additional configuration requirements
`necessary to make the separate SIMMs modules function as
`a single memory unit, such as setting base addresses for the
`SIMM modules installed.
`
`As a result, a user seeking to increase his usable main
`memory by adding SIMMs constructed according to the
`prior art, typically must insert multiple SIMMs to achieve a
`memory expansion for the entire data path of his computer.
`The foregoing is a consequence of typical prior art SIMM
`architecture, wherein the SIMM is arranged around DRAM
`parts which comprise one byte wide memory increments.
`Thus in a data path having a width of 32 bits, there being
`eight bits per byte, a 1 megabyte expansion of main memory
`using SIMMs constructed according to the prior art would
`require four SIMM modules each of one megabyte capacity
`in order to obtain a full data path expansion of one mega-
`byte.
`in the following
`As will be described in more detail
`detailed description, the present invention provides, among
`other attributes, facility for providing memory expansion in
`full data path widths, thereby relieving the user of config-
`uring and installing multiple SIMMs modules to obtain any
`desired memory increment.
`SUMMARY OF THE INVENTION
`
`A full width single in-line memory module (SIMM) for
`dynamic random access memory (DRAM) memory expan-
`sions is disclosed. A printed circuit board having a multi-
`plicity of DRAM memory elements mounted thereto is
`arranged in a data path having a width of 144 bits. The
`SIMM of the present invention further includes on-board
`drivers to buffer and drive signals in close proximity to the
`memory elements. In addition, electrically conductive traces
`are routed on the circuit board in such a manner to reduce
`
`loading and trace capacitance to minimize signal skew to the
`distributed memory elements. The SIMM further includes a
`high pin density dual read-out connector structure receiving
`electrical traces from both sides of the circuit board for
`enhanced functionality. The SIMM is installed in comple-
`mentary sockets one SIMM at a time to provide memory
`expansion in full width increments. Finally, symmetrical
`power and ground routings to the connector structure insure
`that
`the SIMM cannot be inserted incorrectly, wherein
`physically reversing the SIMM in the connector slot will not
`reverse power the SIMM.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The obj ccts, features and advantages of the present inven-
`tion will be apparent from the following detailed description
`given below and from the accompanying drawings of the
`preferred embodiment of the invention in which:
`FIG. 1a illustrates the electrical schematic of a first side
`
`of the single in-line memory module (SIMM) according to
`the teachings of the present invention.
`FIG. 1b illustrates the electrical schematic for a left-to-
`right mirror image layout of memory elements on a second
`side of the SIMM.
`
`FIG. 2a illustrates the physical layout of the memory
`elements and drivers placed on the SIMM.
`FIG. 2b is a magnified view of the dual read-out connector
`structure on the SIMM.
`
`FIG. 3 illustrates the stacked conductive layers separated
`by insulating dielectric necessary to build up the intercon-
`nections for the electrical schematic shown in FIGS. 1a and
`1b.
`
`11
`
`11
`
`

`

`5,973,951
`
`3
`FIGS. 4a and 4b are a connector diagram illustrating data,
`address and control signals routed to a SIMM.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`A bus architecture for integrated data and video memory
`is disclosed. In the following description, for purposes of
`explanation, specific numbers, times, signals etc., are set
`forth in order to provide a thorough understanding of the
`present invention. However, it will be apparent to one skilled
`in the art that the present invention may be practiced without
`these specific details. In other instances, well known circuits
`and devices are shown in block diagram form in order not to
`obscure the present invention unnecessarily.
`'Ihe preferred embodiment of the SIMM described herein
`is designed and intended to be used with the integrated data
`and video memory bus disclosed in copending U.S. patent
`application Ser. No. 07/886,671, filed May 19, 1992, now
`U.S. Pat. No. 5,265,218, issued Nov. 23, 1993 entitled “A
`Bus Architccturc For Intcgratcd Data and Video Mcmory”.
`It will be apparent, however, to those skilled in the art that
`the specifications disclosed herein can or may be changed
`without departing from the scope of the present invention.
`Although the preferred embodiment of the present invention
`is disclosed in terms of the data path width matching that of
`the integrated data and video memory bus disclosed in the
`above-referenced U.S. patent application, it will be appre-
`ciated that changing the design of the bus is within the scope
`of the present invention, wherein the SIMM may be matched
`to the data path width of the integrated memory bus.
`Reference is now made to FIG. 1a wherein an electrical
`
`block diagram of memory elements mounted to a first,
`obverse side of the SIMM is shown. In FIG. 1a, a multi-
`plicity of dynamic RAM (DRAMs) are grouped into two
`clusters 10a and 10b. There are nine DRAMs 10 in each
`
`cluster. A driver 15 receives control signals, and address
`signals from an external bus arrangement
`(not shown)
`through a dual sided connector 30. A multiplicity of control
`lines 20 route RAS-(row access strobe), CAS- (column
`access strobe), WE- (write enable), and OE- (output enable),
`control signals from driver 15 to all the DRAMs 10 mounted
`to SIMM 5. Moreover, driver 15 buffers and subsequently
`distributes address signals 21 to all DRAMs 10 mounted to
`SIMM 5. For purposes of clarity in the present figure, the
`specific routing of data, address and control lines to all the
`DRAMs 10 i