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`Attorney Docket No.: 37307-0007IP1
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`In re Patent of: Benisek et al.
`US Patent No.: 6,850,414
`Issue Date:
`February 1, 2005
`Appl. Serial No.: 10/187,763
`§ 371 (c)(1) Date: July 2, 2002
`Title:
`ELECTRONIC PRINTED CIRCUIT BOARD HAVING A
`PLURALITY OF IDENTICALLY DESIGNED, HOUSING-
`ENCAPSULATED SEMICONDUCTOR MEMORIES
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`Attorney Docket No.: 37307-0007IP1
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`
`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`DECLARATION OF VIVEK SUBRAMANIAN
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`I, Vivek Subramanian, declare as follows:
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`I.
`1.
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`Introduction.
`I am making this declaration at the request of the Real Party in Interest
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`(Kingston Technology Company, Inc.) in the matter of Inter Partes Review of U.S.
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`Patent No. 6,850,414 (the “’414 patent”).
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`2.
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`I am being compensated for my work. My compensation does not depend on
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`the outcome of this proceeding.
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`3.
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`I have been asked to consider whether certain references disclose or render
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`obvious the claims of the ’414 Patent, either alone or in combination with each
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`other.
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`KINGSTON 1006
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`KINGSTON 1016
`Kingston v. Polaris
`IPR2016-01622
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`Attorney Docket No.: 37307-0007IP1
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`4.
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`I have been advised that a patent claim may be invalid as obvious if the
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`differences between the subject matter patented and the prior art are such that the
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`subject matter as a whole would have been obvious at the time of the invention to a
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`person having ordinary skill in the art. I have also been advised that several factual
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`inquiries underlie a determination of obviousness. These inquiries include the
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`scope and content of the prior art, the level of ordinary skill in the field of the
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`invention, the differences between the claimed invention and the prior art, and any
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`objective evidence of non-obviousness.
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`5.
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`I have been advised that objective evidence of non-obviousness directly
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`attributable to the claimed invention, known as “secondary considerations of non-
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`obviousness,” may include commercial success, satisfaction of a long-felt but
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`unsolved need, failure of others, copying, skepticism or disbelief before the
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`invention, and unexpected results. I am not aware of any such objective evidence
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`of non-obviousness that is directly attributable to the subject matter claimed in the
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`’414 patent at this time.
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`6.
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`In addition, I have been advised that the law requires a “common sense”
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`approach of examining whether the claimed invention is obvious to a person
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`skilled in the art. For example, I have been advised that combining familiar
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`elements according to known methods is likely to be obvious when it does no more
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`than yield predictable results. I have further been advised that this is especially true
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`in instances where there are a limited numbers of possible solutions to technical
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`problems or challenges.
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`7.
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`I have been informed that all claims of the ’414 Patent are subject to this
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`inter partes review.
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`II. Materials Reviewed
`8.
`In forming the opinions that I express below, I considered my own
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`knowledge of the art plus at least the following references:
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`a. The ’414 Patent
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`b. UK Patent Application GB 2 289 573 A (“Simpson”)
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`c. U.S. Patent Application Publication No. 2002/0006032 A1
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`(“Karabatsos”)
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`d. U.S. Patent No. 5,973,951 (“Bechtolsheim”)
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`e. U.S. Patent No. 6,038,132 (“Tokunaga”)
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`f. PC SDRAM Unbuffered DIMM Specification, Revision 1.0
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`(“Intel DIMM Specification”)
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`g. The File History of U.S. Patent No. 6,850,414
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`III. Qualifications
`9.
`I summarize my relevant knowledge and experience below. My Curriculum
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`Vitae contains additional information and is attached as Exhibit 1010.
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`10. I received a B.S. in electrical engineering from Louisiana State University in
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`1994, an M.S. in electrical engineering from Stanford University in 1996, and a
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`Ph.D. in electrical engineering from Stanford University in 1998.
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`11. I co-founded Matrix Semiconductor, Inc. in 1998 to develop high density
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`memory technology.
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`12. I have been teaching in the Electrical Engineering and Computer Sciences
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`Department at the University of California, Berkeley since 2000. I was an
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`Assistant Professor from 2000 to 2005, an Associate Professor from 2005 to 2011,
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`and a Professor from 2011 to the present.
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`13. I have been an adjunct professor at the Sunchon National University in
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`Sunchon, Korea since 2009, leading research in printed electronics.
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`14. I have been an independent consultant in the semiconductor industry since
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`2000, focusing on memory technology, flexible electronics, and RFID technology.
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`15. I have published more than 200 technical papers in journals and at
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`conferences.
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`16. I am a named inventor on over 40 U.S. Patents, many of which are in the
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`field of memory design.
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`IV. Person of Ordinary Skill in the Art and State of The Art
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`17. In my opinion, a person of ordinary skill in the art as of the time of the ’414
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`Patent would have a Bachelor’s degree in Electrical Engineering and at least 2
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`years’ experience working in the field of semiconductor memory design. I believe
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`this to be a reasonable statement of the level of ordinary skill in the art for the
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`patent and claims at issue. I also believe that I was one of ordinary skill in the art
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`through my education and work experience during the time that I was in
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`University.
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`18. The opinions that I provide in this declaration are consistent with the
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`knowledge and experience of one of ordinary skill in the art at the priority date of
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`the ’414 Patent.
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`19. At the time of the ’414 Patent’s priority date, those of ordinary skill in the
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`art recognized that, within specified design dimensions and tolerances, memory
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`modules and/or error correction devices could be interchanged and oriented in a
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`finite number of ways within the physical size constraints set forth by the industry
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`standards. See Ex. 1002, Simpson, 2:10-15 and Ex. 1003 (Karabatsos).
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`V. Overview of the ’414 Patent
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`20. The ’414 Patent is directed to a printed circuit board (“PCB”) that has at
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`least nine memories chips that are arranged to appreciably reduce the height of the
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`printed circuit board. Ex. 1001, 2:45-3:10. The specification discloses that one of
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`the at least nine chips be an error correction chip and that one be arranged
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`vertically on the printed circuit board, such that the error correction chip
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`determines the maximum height of the printed circuit board, while the other
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`semiconductor memories are arranged horizontally. Ex. 1001, 3:11-27, 6:1-4.
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`21. The supposed invention “is achieved by virtue of the fact that, in the case of
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`the printed circuit board of the generic type, the housings of the identically
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`designed semiconductor memories, other than the error correction chip, are
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`arranged on the printed circuit board in a manner such that they are oriented with
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`their longer dimension parallel to the contact strip.” Ex. 1001, 3:4-10. According to
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`the patent, this allows “a certain, albeit small, narrowing of the printed circuit
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`board.” Ex. 1001, 3:44-46.
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`22. Notably, though as seen in Fig. 1A (front side) and 1B (rear side), the prior
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`art is admitted by the applicant for the patent to disclose a printed circuit board
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`with all semiconductor memories 4 arranged vertically, including the error
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`correction chip 5. Ex. 1001, Figs. 1A and 1B. The purportedly inventive printed
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`circuit board, disclosed by the ’414 Patent, with an error correction chip 5 arranged
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`vertically and remaining semiconductor memories 4 arranged horizontally. Ex.
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`1001, Figs. 2 and 3.
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`23. Furthermore, there is no indication in the ’414 patent that orienting the error
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`correction chip 5, rather than a memory or other type of semiconductor chip,
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`vertically is anything other than a design choice. In other words, I have not seen
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`anything within the ’414 patent that would indicate that the decision to orient the
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`error correction chip 5 vertically is critical to the design or operation of the ’414
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`patent’s memory module.
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`FIG. 1A shows the front side of a
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`FIG. 2 shows the front side of an
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`conventional printed circuit board.
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`inventive printed circuit board.
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`FIG. 1B shows the rear side of the
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`conventional printed circuit board.
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`FIG. 3 shows the rear side of the
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`printed circuit board shown in FIG. 2.
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`24. The specification of the patent asserts that the prior art design of Figs. 1A
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`and 1B predetermines the size of the printed circuit board because two resistors
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`“must be arranged between one semiconductor memory 4 and the contact strip 2,
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`because the upper limit for the length of the leads of the resistors from the contact
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`strip 2 permits no other arrangement.” Ex. 1001, 5:59-6:4.
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`25. The specification also explains that by arranging the semiconductor modules
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`horizontally, there is “no need for any resistors” between the housing and the
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`contact strip, and thus “the actual printed circuit board height is determined only
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`by the error correction chip 4b that is brought up to the contact strip 2.” Ex. 1001,
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`6:19-39. Accordingly, this small “reduction of the printed circuit board height
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`enables incorporation into even flatter elements of e.g. network computers.” Ex.
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`1001, 6:47-49. As I describe further below, turning a DRAM chip on its side was
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`well within the skill level of a person even not versed in the art—a person skilled
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`in the art would certainly not find this change inventive.
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`VI. Claim Construction
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`26. The specification of the ’414 does not specifically define the term “error
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`correction,” as recited in the claims of the ’414 patent. However, the specification
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`of the patent does explain that the error correction chip “checks the correctness of
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`the data before the data are passed on.” Ex. 1001 at 7:2-5. It further describes that
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`“the reason for this arrangement is that one of the semiconductor memories is used
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`as an error correction chip in order to perform error checking on data that will be
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`stored in the rest of the semiconductor memories or that will be read from the
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`memories.” Ex. 1001 at 1:51-54. There is no further description in the ’414 patent
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`as to how the error correction chip would correct errors beyond error checking.
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`The remainder of the description related to the error correction chip is directed to
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`its location and physical orientation. The use of the term within the claim itself
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`provides no additional guidance.
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`27. One or ordinary skill in the art would understand that error detection is
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`typically a part error of error correction. In view of the specification, one of
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`ordinary skill in the art would further understand that the broadest reasonable
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`construction of “error correction chip” based on the specification to mean “a chip
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`that is able to perform at least error checking on data stored in other semiconductor
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`memories.”
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`VII. Simpson
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`28. I have been advised, and my understanding is, that Simpson is eligible to
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`serve as prior art for the ’414 Patent under 35 U.S.C. § 102(a). Simpson was
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`published on November 22, 1995 in the United Kingdom, at least five years before
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`the priority date of the ‘414 patent. See Ex. 1002, Simpson. Based on my review of
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`the ’414 patent file history, Simpson was not cited by the USPTO or considered by
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`the Examiner during prosecution of the ’414 Patent. See Ex. 1007.
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`29. Simpson teaches a memory module that “allows the user to customize the
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`module at the point of use rather than having to use the module configured during
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`its manufacture.” Ex. 1002, Simpson, at 7:8-10. Figs. 1 and 3 below illustrate a
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`first face and a second face, respectively, of the preferred embodiment of the
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`invention and design of a printed circuit board.
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`30.
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`31.
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`32. In Simpson, the printed circuit board 2 has a connection terminal 10 for
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`insertion into a module receptacle. Ex. 1002, Simpson, at 10:21-28. The printed
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`circuit board 2 also has memory devices 12A-12H on one face of the printed
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`circuit board 2 that are electrically and mechanically connected. Ex. 1002,
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`Simpson, at 10:1-5, Fig. 2. Both faces include sockets 14A-J to add additional
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`memory or logic devices as needed. Ex. 1002, Simpson, at 10:5-12, Fig. 3.
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`Additional memory devices 18A-H can be added using sockets 14C-J. Ex. 1002,
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`Simpson, at 10:21-30.
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`33. Further, parity memory devices 16 are situated on both faces of the printed
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`circuit board. Ex. 1002, Simpson, at 10:32-11:13. Fig. 1 illustrates the parity
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`memory device 16A arranged perpendicular to the connection terminal 10. Ex.
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`1002, Simpson, at Fig. 1. And, also as illustrated in Fig. 1, sockets 14C-H are
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`arranged parallel to the connection terminal 10. Id. Simpson appreciates that any
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`devices can be added or replaced by sockets as long as the module has a sufficient
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`amount of memory devices to function. Ex. 1002, Simpson, at 8:5-11.
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`VIII. Karabatsos
`34. I have been advised, and my understanding is, that Karabatsos is eligible to
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`serve as prior art for the ’414 patent under 35 U.S.C. § 102(e). Karabatsos has a
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`was filed in the United States on January 11, 2001. See Ex. 1003, Karabatsos.
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`Based on my review of the ’414 patent file history, Karabatsos was not cited by the
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`USPTO or considered by the Examiner during prosecution. See Ex. 1007, the ’414
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`Patent File History.
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`35. Karabatsos describes “[a] low profile, registered DIMM [that] has a height
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`of about 1.2 inches, and a width of about 5.25 inches.” Ex. 1003, Karabatsos at
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`Abstract, FIG. 1C. Karabatsos describes that the market demand for higher
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`capacity memory at the time resulted in manufacturers producing many memory
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`modules (e.g., DIMMs) that had “profiles of 1.5 inches or greater.” Id. at ¶¶
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`[0004]-[0020]. Karabatsos recognized that the “unavailability of DIMMs with
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`lower profiles [had] had a serious, negative effect on many computer designs.” Id.
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`at ¶ [0020]. Karabatsos further explains the negative effect of tall DIMMs on
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`computer designs lead to server manufacturers designing enclosures around the
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`height of the memory modules or taking “extraordinary steps” to “slant[] . . .
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`DIMM sockets at 22½ degrees.” Id. at ¶¶ [0021], [0022].
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`36.
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`In order to address this problem, Karabatsos proposes in FIGS. 1A-1C
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`several different configurations and orientations for mounting memory chips
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`(SDRAMs) to reduce the profile height of memory modules. See Id. at FIGS. 1A-
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`1C (reproduced below). Karabatsos’s designs incorporate a dense arrangement of
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`SDRAMs and, as shown in FIG. 1C, a rearrangement of SDRAM orientation with
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`a center SDRAM oriented perpendicular to the other SDRAMs. Id.
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`37.
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`38.
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`39.
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`40. Karabatsos demonstrates that there was a recognized need within the art at
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`the time of the priority date of the ’414 patent to reduce the height of memory
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`modules. Furthermore, Karabatsos also illustrates that it was indeed well-known in
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`the art at the time to re-arrange the layout of memory chips on a memory module
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`to achieve desired dimensions for a memory module.
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`IX. Bechtolsheim
`41. I have been advised, and my understanding is, that Bechtolsheim is eligible
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`to serve as prior art for the ’414 Patent under 35 U.S.C. § 102(b). Bechtolsheim
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`was published on October 26, 1999 in the United States, more than a year before
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`the priority date of the ‘414 patent. See Ex. 1004, Bechtolsheim. Based on my
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`review of the ’414 patent file history, Bechtolsheim was not cited by the USPTO or
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`considered by the Examiner during prosecution of the ’414 Patent. See Ex. 1007.
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`42. Bechtolsheim teaches a “single in-line memory module (SIMM) for memory
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`expansion in a computer system.” Ex. 1004, Bechtolsheim at Abstract. “The SIMM
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`includes a plurality of memory chips surface-mounted on a printed circuit board.”
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`Id. Figs. 1a, 1b, and 2a below illustrate a first face and a second face, Figs. 1a and
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`1b respectively, and an arrangement of the “dynamic random access memory
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`(DRAM)” chips on the first face of a printed circuit board. See e.g., Id. at 2:27-32;
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`3:32-4:31; 5:13-15.
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`43.
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`44.
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`45. In Bechtolsheim, the SIMM has a contact regions 50A and 50B for
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`“insertion within a socket of [a] computer system.” Id. at Abstract; 5:13-23. The
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`SIMM 5 also has DRAM 10 memory devices mounted on both faces of the SIMM
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`5 that are electrically and mechanically connected. Id. at 3:32-4:31, Figs. 1a, 1b,
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`2a. As shown in Fig. 2a, the DRAMs 10 are mounted with a longer edge parallel to
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`the contact regions 50A and 50B. In Bechtolsheim the “DRAMs 10 [are] any of
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`several commercially available DRAMs arranged in a ‘by-four’ configuration” and
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`can include “error correction.” Id. at 3:48-50; 3:65-67.
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`46. Further, Bechtolsheim includes an additional chip, a driver 15, mounted on
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`the front face of the SIMM 5 and oriented such that a longer edge is perpendicular
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`to the contact regions 50A and 50B. Id. at 3:32-55; 5:13-15; Figs. 1a and 2a.
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`X. Tokunaga
`47. I have been advised, and my understanding is, that Tokunaga is eligible to
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`serve as prior art for the ’414 Patent under 35 U.S.C. § 102(b). Tokunaga was
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`published on March 14, 2000 in the United States, more than a year before the
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`priority date of the ‘414 patent. See Ex. 1005, Tokunaga. Based on my review of
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`the ’414 patent file history, Tokunaga was not cited by the USPTO or considered
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`by the Examiner during prosecution of the ’414 Patent. See Ex. 1007.
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`48. Tokunaga teaches a computer “memory module” that includes a plurality of
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`“semiconductor memory devices.” Ex. 1005, Tokunaga at Abstract. Tokunaga
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`demonstrates that it was well-known before the priority date of the ’414 patent to
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`use typical semiconductor memory devices for “ECC function[s] and/or parity
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`function[s]” to “check errors in input/output data” of the memory devices and
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`ultimately the memory module. Id. at 4:62-67; 9:11-16.
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`XI. Simpson and Karabatsos at the Time of the Invention
`49. Simpson alone or in combination with Karabatsos discloses the same
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`technology that is allegedly the invention of the ’414 Patent.
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`50. It would have been obvious to modify the printed circuit board and memory
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`module design of Simpson to incorporate the constraints disclosed in Karabatsos.
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`In the resulting design, Simpson would be constrained to a profile height of 1.2
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`inches in order to address the problem of the “unavailability of DIMMs with lower
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`profiles” as identified by Karabatsos. One of ordinary skill in the art would have
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`been motivated to modify Simpson based on the design dimensions of Karabatsos
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`to meet this market demand and would have had a reasonable expectation of
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`success when doing so.
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`51. Furthermore, because Simpson does not explicitly provide a height of the
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`memory module 2, it would have been obvious to produce Simpson’s memory
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`module 2 with a “height of between 1.125 and 1.250 inches” as taught by
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`Karabatsos in order to meet the industry need identified by Karabatsos. Ex. 1003,
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`Karabatsos at ¶ [0027].
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`52.
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`In addition, it would have been readily apparent to one of skill in the art that
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`Simpson’s layout of semiconductor memory modules (as shown in FIG. 1,
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`reproduced below) was readily adaptable, if needed, to meet Karabatsos’s
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`suggested design height by, for example, simply eliminating the row of memory
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`devices (e.g., memory devices 12g, 12e, 12c, and 12a) to reduce the profile height
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`of the printed circuit board 2. Note that Simpson is clearly cognizant of this design
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`flexibility. Ex. 1002, Simpson at 10:10-12 (“The quantity, position and type [of
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`memory devices, error correction devices, or other semiconductor devices] are
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`dependent upon the design preferences of the module designer and the organization
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`of module chosen.”).
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`53.
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`54. Furthermore, a reduction in the number of memory devices on a board
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`would not be a concern to one of skill in the art because, as evidenced by the Intel
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`DIMM specification, it was known to replace lower rank memory devices (e.g., x8
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`devices) with fewer higher rank memory devices (e.g., x16 or x32). See e.g., Ex.
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`1008 Intel DIMM Specification at 34. A figure from page 34 of the Intel DIMM
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`Specification that illustrates the use of various rank memory devices is reproduced
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`below. Here, rank is used as would be known to one of skill in the art as
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`terminology describing the configuration of a bit width of 64 bits (not counting any
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`error correction bits), which can be accessed at the same time. Therefore, an x8
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`rank would consist of 8 chips, each being 8 bits wide, while an x16 rank would
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`consist of 4 chips, each being 16 bits wide. In other words, the ‘xX’ designation of
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`the rank indicates the bit width of the individual chips used to achieve the overall
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`64 bit wide rank. Note that bits used for ECC implementation are not included in
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`the bit count. It would be straightforward to replace, for example, 8 x8 chips with 4
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`x16 chips to maintain the same overall width.
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`55.
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`56. One of ordinary skill in the art would recognize that modifying Simpson to
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`reduce the overall profile height of a memory module as taught by Karabatsos
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`would address a growing industry need and meet a previously unmet market
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`demand. The motivation to combine the references was obvious.
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`57. Rearranging memory devices on a memory module to reduce the height of
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`Simpson’s memory module was well within the knowledge of a person of ordinary
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`skill by the priority date of the ’414 patent. This can be seen at least by the section
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`from the Intel Specification shown above, which illustrates three different designs
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`with two different orientations for memory chips. The Intel Specification evidences
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`that one of ordinary skill in the art would be know how to rearrange chips on a
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`DIMM Board and could readily do so, if there was a design requirement, such as
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`standard compliance or a design requirement that mandated a particular dimension
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`of printed circuit board, such as a target height.
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`XII. Bechtolsheim, Karabatsos, and Tokunaga at the Time of the Invention
`58. Bechtolsheim in combination with Karabatsos and Tokunaga discloses the
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`same technology that is allegedly the invention of the ’414 Patent.
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`59. It would have been obvious to modify the printed circuit board and memory
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`module design of Bechtolsheim to incorporate the constraints disclosed in
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`Karabatsos. In the resulting design, Bechtolsheim would be constrained to a profile
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`“height of between 1.125 and 1.250 inches” in order to address the problem of the
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`“unavailability of DIMMs with lower profiles” as identified by Karabatsos. One of
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`ordinary skill in the art would have been motivated to modify Bechtolsheim based
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`on the design dimensions of Karabatsos to meet this market demand and would
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`have had a reasonable expectation of success when doing so.
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`60. Furthermore, because Bechtolsheim does not explicitly provide a height of
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`the SIMM 5, it would have been obvious to produce Bechtolsheim’s SIMM with a
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`“height of between 1.125 and 1.250 inches” as taught by Karabatsos in order to
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`meet the industry need identified by Karabatsos. Ex. 1003, Karabatsos at ¶ [0027].
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`61. Moreover, it would have been readily apparent to one of skill in the art that
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`Bechtolsheim’s layout of semiconductor memory modules (as shown in FIG. 2a,
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`reproduced below) was readily adaptable, if needed, to meet Karabatsos’s
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`suggested design height by, for example, simply eliminating the row of memory
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`devices to reduce the profile height of the SIMM 5.
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`62.
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`63. Furthermore, a reduction in the number of memory devices on a board
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`would not be a concern to one of skill in the art because, as evidenced by the Intel
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`DIMM specification, it was known to replace lower rank memory devices (e.g., x8
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`devices) with fewer higher rank memory devices (e.g., x16 or x32). See e.g., Ex.
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`1008 Intel DIMM Specification at 34. A figure from page 34 of the Intel DIMM
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`Specification that illustrates the use of various rank memory devices is reproduced
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`below. See the discussion of memory rank above.
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`64.
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`65. One of ordinary skill in the art would recognize that modifying
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`Bechtolsheim to reduce the overall profile height of a memory module as taught by
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`Karabatsos would address a growing industry need and meet a previously unmet
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`market demand. The motivation to combine the references was obvious.
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`66. Rearranging memory devices on a memory module to reduce the height of
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`Bechtolsheim’s memory module was well within the knowledge of a person of
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`ordinary skill by the priority date of the ’414 patent.
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`67.
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`It would also have been obvious to one of skill in the art before the priority
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`date of the ’414 patent to combine the teachings of Tokunaga with those of either
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`or both Bechtolsheim and Karabatsos. As noted above, Tokunaga demonstrates
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`that it was well-known before the priority date of the ’414 patent to use typical
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`semiconductor memory devices for “ECC function[s] and/or parity function[s]” to
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`“check errors in input/output data” of the memory devices and ultimately the
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`memory module. Ex. 1005, Tokunaga at 4:62-67; 9:11-16. One of skill in the art
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`would be motivated to configure one of the memory devices of either
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`Bechtolsheim or Karabatsos to provide improved memory modules with error
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`checking capability.
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`68. Furthermore, although Bechtolsheim shows a driver 15 as being arranged
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`perpendicular to contact regions 50A and 50B, instead of an error correction chip,
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`as disclosed by the ’414 patent, Bechtolsheim’s Fig. 2a explicitly illustrates that
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`the general arrangement of a plurality of horizontally oriented chips and one
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`vertically oriented chips on a printed circuit board was well-known. As noted
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`above, there is no indication in the ’414 patent that orienting the error correction
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`chip 5, rather than a memory or other type of semiconductor chip, vertically is
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`anything other than a design choice. Consequently, it is my opinion that orienting a
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`memory device configured to perform error checking, as discussed in Tokunaga,
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`vertically on Bechtolsheim’s SIMM 5 would have been an obvious design choice
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`to one of skill in the art. For example, one may choose to place such a vertically
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`oriented error checking memory device in place of Bechtolsheim’s driver 15 and
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`move the driver 15 under one of the horizontally oriented memory devices, as
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`shown by the location of register chip 6 and PLL chip 8 in Fig. 1C of Karabatsos
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`(reproduced and annotated below).
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`69.
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`70. As another example, one may choose to place a vertically oriented error
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`caching memory device in the center of the back side of Bechtolsheim’s SIMM 5,
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`as shown in Bechtolsheim’s Fig. 1b as annotated below.
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`71.
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`XIII. Certain References Disclose And/Or Render Obvious All Elements of
`Claims 1 and 4 of the ‘414 Patent.
`A. Simpson alone or in combination with the Intel Specification,
`renders obvious all elements of Claims 1 and 4 of the ’414 Patent
`1.
`Claim 1
`a. “An electronic printed circuit board configuration,
`comprising:”
`72. In my opinion, Simpson discloses an electronic printed circuit board
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`configuration. See Ex. 1002, Simpson, at 1:10-23, 2:17-20, and 4:28-5:5. Marked-
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`up Figure 1 of Simpson clearly illustrates an electronic printed circuit board. Id.
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`73.
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`b. “An electronic printed circuit board having a contact
`strip for insertion into another electronic unit; and”
`74. In my opinion, Simpson discloses an electronic printed circuit board having
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`a contact strip for insertion into another electronic unit. See Ex. 1002 at 2:24-30,
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`9:8-16, 10:21-30, and 12:10-14. Specifically, Simpson chooses to use the term
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`“connector terminal strip 10” rather than “contact strip;” however, the terms are
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`interchangeable as one of ordinary skill in the art would recognize.
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`75. This marked-up figure below illustrates how Simpson teaches this element.
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`Id.
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`76.
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`c. “A memory module having at least nine identically
`designed integrated semiconductor memories;”
`77. In my opinion, Simpson discloses a memory module having at least nine
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`identically designed integrated semiconductor memories. See Ex. 1002, Simpson,
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`at Figures 1 and 3, 5:12-18, 5:34-35, 7:8-12, 8:5-11, 9:18-27, 10:10-19, 13:7-12,
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`and 13:28-32.
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`78. As shown in Figure 1, on a single side, Simpson discloses a base module 2
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`that “consists of an array of memory devices 12A-12H[.]” Ex. 1002, Simpson,
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`9:18-20; Fig. 1. Module 2 of Simpson also includes a ninth semiconductor memory
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`16A on that same side. Ex. 1002, 10:14-25 (referring to each of the chips 12A-12H
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`and 16A as memory devices). Those of ordinary skill in the art would understand
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`that the memory device 16A is identical to each of memory devices 12A-12H. See
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`Ex. 1002, Simpson at 11:22-28 (referring to power and signals collectively for all
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`of the memory devices) and 12:10-14 (describing common capacitors used to
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`supply power to each of the memory devices).
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`79. However, the ’414 patent are not limited to having chips on a single side of
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`the PCB. Simpson makes clear that “memory devices 12 may be mounted on both
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`sides of the module 2.” Ex. 1002, Simpson, 13:7-12. The illustrated embodiments
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`of Simpson envision empty sockets 14C-14J populated with memory devices 18A-
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`18H plugged in for added memory. Simpson, Ex. 1002, 10:14-19; Fig. 3. One of
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`ordinary skill in the art would also plainly recognize that replaceable memory
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`devices 18A-18H could be identical to memory devices 12A-12H, as this decision
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`would merely depend on in order to enable the addition of those eight chips to
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`increase “the module designer memory capacity from 4Mbits to 8Mbits in length
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`by plugging into sockets 14C-14J memory devices 18A-18H. See Ex. 1002,
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`Simpson, 10:10-12; Figs. 1-3. Additionally, sockets 14A-14B could also be filled
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`with memory devices identical to memory devices 12A-12H as one of ordinary
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`skill in the art would recognize. Id.
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`80. This marked-up figure below illustrates how Simpson teaches this element.
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`Id.
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`81.
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`d. “Each one of said semiconductor memories being
`encapsulated in a rectangular housing having a
`shorter dimension and a longer dimension;”
`82. In my opinion, Simpson discloses that each one of said semiconductor
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`memories are encapsulated in a rectangular housing having a shorter dimension
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`and a longer dimension. See Ex. 1002, Simpson, at Figures 1 and 2.
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`83. Marked-up Figure 1 illustrates how Simpson teaches this element. Id.
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`84.
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`85. Also, Marked-up Figure 2 illustrates this element. Id.
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`86.
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`87. Further, in my opinion, a person of ordinary skill in the art would have
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`understood that Figures 1-3 illustrate memory devices 12, 16, and 18 as being—or
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`could be modified to be—encapsulated in housings, as there is nothing inventive
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`about this limitation. Also, Simpson discloses that “memory devices 12A-12H are
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`electrically an