UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`KINGSTON TECHNOLOGY COMPANY, INC.,
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`Petitioner
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`v.
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`POLARIS INNOVATIONS LTD.,
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`Patent Owner
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`Case No. IPR2017-00974
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`Patent 6,850,414
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`PETITION FOR INTER PARTES REVIEW OF
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`U.S. PATENT NO. 6,850,414
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`
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`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`1
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`1
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`KINGSTON 1015
`Kingston v. Polaris
`IPR2016-01622
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`

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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`TABLE OF CONTENTS
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`Page
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`INTRODUCTION AND RELIEF REQUESTED .................................... 1 
`I. 
`II.  GROUNDS FOR STANDING .................................................................... 1 
`III.  MANDATORY NOTICES .......................................................................... 2 
`IV.  BACKGROUND ........................................................................................... 3 
`A. 
`Description of the ’414 Patent ............................................................. 3 
`B. 
`Prosecution History .............................................................................. 5 
`C. 
`Person of Ordinary Skill in the Art ...................................................... 6 
`D. 
`State of the Art ..................................................................................... 6 
`V.  CLAIM CONSTRUCTION ........................................................................ 7 
`A. 
`“Error Correction Chip” ....................................................................... 8 
`B. 
`“Connected” ......................................................................................... 9 
`VI.  PROPOSED GROUNDS OF UNPATENTABILITY .............................. 9 
`A. 
`Summary of Grounds of Rejection ...................................................... 9 
`B. 
`Prior Art Offered for the Present Unpatentability Challenges .......... 10 
`C. 
`This Petition Presents Substantially New Arguments and Prior Art
`from that Previously Before the Board .............................................. 11 
`VII.  THE PRIOR ART RENDERS OBVIOUS CLAIM 4 OF THE ’414
`PATENT ...................................................................................................... 14 
`Claim 4 is Rendered Obvious by Simpson in view of the Karabatsos
` ............................................................................................................ 15 
`Summary of Simpson ........................................................................ 15 
`Eligibility of Simpson As Prior Art .................................................. 17 
`Summary of Karabatsos .................................................................... 17 
`Eligibility of Karabatsos as Prior Art ............................................... 19 
`The Proposed Combination of Simpson and Karabatsos ................ 19 
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`2. 
`3. 
`4. 
`5. 
`6. 
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`A. 
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`7. 
`8. 
`B. 
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`Claim 1 (upon which claim 4 depends) ............................................ 23 
`Claim 4 ............................................................................................... 34 
`Bechtolsheim in combination with Tokunaga and Karabatsos, renders
`obvious all elements of Claim 4 4 of the ’414 Patent ........................ 39 
`Claim 1 from which Claim 4 Depends ............................................. 39 
`9. 
`Claim 4 ............................................................................................... 50 
`10. 
`VIII.  CONCLUSION ........................................................................................... 55 
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`ii
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`3
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`
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`Exhibit
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`EXHIBIT LIST
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`Description
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`1001 U.S. Patent 6,850,414 to Benisek (’414 patent)
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`1002 UK Patent Application GB 2 289 573 A to Simpson
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`1003 U.S. Patent Application Publication No. 2002/0006032 to
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`Karabatsos
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`1004 U.S. Patent No. 5,973,951 to Bechtolsheim
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`1005 U.S. Patent No. 6,038,132 to Tokunaga
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`1006 Declaration of Professor Vivek Subramanian (“Subramanian”)
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`1007
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`ʼ414 Patent File History
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`1008
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`PC133 SDRAM Registered DIMM Design Specification
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`1009 District Court Complaint with Proof of Service Executed and filed
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`by Plaintiff
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`1010
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`Professor Vivek Subramanian’s Curriculum Vitae
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`iii
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`4
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`I.
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`INTRODUCTION AND RELIEF REQUESTED
`Kingston Technology Company, Inc. (“Petitioner”) hereby petitions for
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`institution of inter partes review of claim 4 of U.S. Patent No. 6,850,414 (the “’414
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`Patent”) (Ex. 1001). The ’414 Patent issued on February 1, 2005. Polaris
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`Innovations Limited (“Patent Owner”) is the assignee of record with the United
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`States Patent & Trademark Office (“USPTO”). Petitioner respectfully requests
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`cancellation of claim 4 of the ’414 Patent on the grounds of unpatentability herein.
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`The prior art and other evidence offered with this Petition—which were not before
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`the USPTO during original prosecution—establish that all elements in the
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`challenged claim of the ’414 Patent were well known prior to the earliest alleged
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`priority date, and that the claimed methods and systems recited in the ’414 Patent
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`are invalid as obvious under 35 U.S.C. § 103.
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`II. GROUNDS FOR STANDING
`Petitioner certifies that the ’414 Patent is available for review under 35 U.S.C.
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`§ 311(c) and that Petitioner is not estopped from requesting an inter partes review
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`challenging claim 4 on the grounds identified herein.
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`Petitioner certifies that the ’414 Patent is available for IPR. The present
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`petition is being filed within one year of service of a complaint against Kingston
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`Technology Company, Inc. in Civil Action No. 8:16-cv-300, filed February 19, 2016
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`in the Central District of California. Petitioner is not barred or estopped from
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`1
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`requesting this review challenging the Challenged Claims on the below-identified
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`grounds.
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`III. MANDATORY NOTICES
`Real Party in Interest: Petitioner Kingston Technology Company, Inc.
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`Related Matters: Inter partes review IPR2016-01622 of claims 1 and 5-8 of
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`the ’414 Patent was instituted on February 15, 2017. The Patent Owner alleges
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`infringement of the ’414 Patent in the parallel litigation styled Polaris Innovations
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`Ltd. v. Kingston Tech. Co., Inc., Case No. 8:16-cv-300 (C.D. Cal.), filed February
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`19, 2016 (“Co-Pending District Court Action”). Petitioner was served with the
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`complaint in that litigation on February 25, 2016. Ex. 1009.
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`Designation of Counsel: Petitioner designates the following Lead and Back-
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`up Counsel. Concurrently filed with this Petition is a Power of Attorney per 37
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`C.F.R. § 42.10(b). Service via hand-delivery may be made at the postal mailing
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`address below. Petitioner consents to electronic service by e-mail.
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`Lead Counsel
`David Hoffman (Reg. No. 54,174)
`3200 RBC Plaza
`60 South Sixth Street
`Minneapolis, MN 55402
`Tel: (512) 472-8154
`Fax: (202) 783-2331
`IPR37307-0007IP2@fr.com
`
`Back-Up Counsel
`Martha Hopkins (Reg. No. 46,277)
`Law Offices of S.J. Christine Yang
`17220 Newhope St., Suites 101-102
`Fountain Valley, CA 92708
`Tel: (714) 641-4022
`Fax: (714) 641-2082
`IPR@sjclawpc.com
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`2
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`Payment of Fees (37 C.F.R. § 42.103): Petitioner authorizes the Patent and
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`Trademark Office to charge Deposit Account No. 06-1050 for the petition fee and
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`for any other required fees.
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`IV. BACKGROUND
`A. Description of the ’414 Patent
`The ’414 Patent relates to a printed circuit board that has at least nine
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`identically designed, integrated semiconductor memories with housings that are
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`arranged to reduce the height of the printed circuit board. Ex. 1001 at 2:45-3:10;
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`Subramanian at ¶20. The specification discloses that one of the at least nine
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`semiconductor memories be allocated for error correction and arranged vertically on
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`the printed circuit board, such that the error correction chip determines the maximum
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`height of the printed circuit board, while the other semiconductor memories are
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`arranged horizontally. Ex. 1001 at 3:11-27, 6:1-4; Subramanian at ¶20.
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`The purported invention here “is achieved by virtue of the fact that, in the case
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`of the printed circuit board of the generic type, the housings of the identically
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`designed semiconductor memories, other than the error correction chip, are arranged
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`on the printed circuit board in a manner such that they are oriented with their longer
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`dimension parallel to the contact strip.” Ex. 1001 at 3:4-10. Accordingly, this allows
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`“a certain, albeit small, narrowing of the printed circuit board.” Ex. 1001 at 3:44-
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`46.
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`3
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`However, as seen in Figs. 1A (front side) and 1B (rear side) of the ’414 Patent,
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`the prior art discloses a printed circuit board with all semiconductor memories 4
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`arranged vertically, including the error correction chip 5, such that the sole purported
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`improvement claimed in the ’414 Patent is a simple 90-degree rotation of the
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`memory chip orientation found in the prior art. See Ex. 1001 at Figs. 1A and 1B;
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`Subramanian at ¶22. In contrast, Figs. 2 and 3 illustrate the purportedly inventive
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`printed circuit board, disclosed by the ’414 Patent, with an error correction chip 5
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`arranged vertically and remaining semiconductor memories 4 arranged horizontally,
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`as opposed to vertically as in the prior art. Ex. 1001 at Figs. 2 and 3; Subramanian
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`at ¶22.
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`FIG. 2 shows the front side of an
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`inventive printed circuit board.
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`FIG. 1A shows the front side of a
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`conventional printed circuit board.
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`FIG. 1B shows the rear side of the
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`FIG. 3 shows the rear side of the printed
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`4
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`conventional printed circuit board.
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`circuit board shown in FIG. 2.
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`The specification discloses that the prior art design of Figs. 1A and 1B
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`predetermines the size of the printed circuit board because two resistors “must be
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`arranged between one semiconductor memory 4 and the contact strip 2, because the
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`upper limit for the length of the leads of the resistors from the contact strip 2 permits
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`no other arrangement.” Ex. 1001 at 5:59-6:4.
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`On the other hand, the specification explains that by arranging the
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`semiconductor modules horizontally, there is “no need for any resistors” between
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`the housing and the contact strip, and thus “the actual printed circuit board height is
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`determined only by the error correction chip 4b that is brought up to the contact strip
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`2.” Ex. 1001 at 6:19-39. Accordingly, this small “reduction of the printed circuit
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`board height enables incorporation into even flatter elements of e.g. network
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`computers.” Ex. 1001 at 6:47-49; Subramanian at ¶25.
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`B. Prosecution History
`On July 2, 2002, the ’414 Patent was filed as Application No. 10/187,763 (“the
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`’763 Application”) entitled “Electronic Printed Circuit Board Having a Plurality of
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`Identically Designed, Housing-Encapsulated Semiconductor Memories.” Ex. 1007.
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`A foreign German application, to which the ’414 patent claims priority, was filed on
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`July 2, 2001. Ex. 1001.
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`5
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`As with the issued patent, the ’763 Application contained eight claims. Ex.
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`1007. On September 15, 2004, a Notice of Allowance and Fees issued. Id. The
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`Notice of Allowance discussed only seven references. Id. And, at least two of those
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`references—Kasatani and Michael—disclosed nearly every limitation according to
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`the examiner—but missing were an error correction chip and horizontal positioning,
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`respectively. Id. Both of which are obvious design choices that the examiner failed
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`to recognize. The eight claims remained unchanged from the original application.
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`Id. The examiner did not address obviousness under 35 U.S.C. § 103. Id.
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`C. Person of Ordinary Skill in the Art
`A person of ordinary skill in the art as of the time of the ’414 Patent would
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`have a Bachelor’s degree in Electrical Engineering and at least 2 years’ experience
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`working in the field of semiconductor memory design. Ex. 1002, at ¶17.
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`D. State of the Art
`By the early 2000’s, design choices for the orientation of memory chips on
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`printed circuit boards were well known to those of ordinary skill in the art, at least
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`because of industry standards. Ex. 1002, at ¶19. For example, by 1995, Simpson
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`recognized that “several variations of the basic design [of printed circuit boards] had
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`been implemented by others to provide different organisations [sic] of memory with
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`a standardised [sic] connection specification so that modules of the same type from
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`one vendor can be freely interchanged with those from another.” Simpson 2:10-15.
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`By 1999, JEDEC1, as well as companies like Intel, had detailed the exact
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`dimensional design constraints from which a printed circuit board could, and should,
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`be designed, to allow interchangeability across devices and companies. See, e.g.,
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`Intel DIMM Specification. Those of ordinary skill in the art thus recognized that,
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`within specified design dimensions and tolerances, memory modules and/or error
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`correction devices could be interchanged in only a limited number of ways within
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`the constraints set forth by the industry standards. Ex. 1002, at ¶19.
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`Thus there is nothing novel or nonobvious about the simple re-arrangement
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`of memory chips on a memory module as disclosed and claimed in the ’414 Patent.
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`Id., generally.
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`V. CLAIM CONSTRUCTION
`In the PTO, a claim in an unexpired patent receives its broadest reasonable
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`interpretation (“BRI”) in light of the specification—i.e., a claim term gets its plain
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`meaning unless it is inconsistent with the specification. See 37 C.F.R. § 42.100(b);
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`Cuozzo Speed Techs., LLC v. Lee, 136 S. Ct. 2131, 2142 (2016). The BRI standard
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`1 JEDEC stands for the “Joint Electron Device Engineering Council.” JEDEC is a
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`recognized standard setting body within the industry. Specifically, the JEDEC
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`memory standards are the specifications for semiconductor memory circuits and
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`similar storage devices promulgated by JEDEC.
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`7
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`is different from the claim construction standard applied in litigation. Id. Kingston
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`submits, for purposes of this IPR only, that the broadest reasonable interpretation
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`should govern the meaning of the claim terms and provides the following specific
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`construction.
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`A.
`“Error Correction Chip”
`The specification of the ’414 Patent does not specifically define the term
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`“error correction,” as recited in the claims of the ’414 Patent. However, the
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`specification does explain that the error correction chip “checks the correctness of
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`the data before the data are passed on.” Ex. 1001 at 7:2-5. It further describes that
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`“the reason for this arrangement is that one of the semiconductor memories is used
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`as an error correction chip in order to perform error checking on data that will be
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`stored in the rest of the semiconductor memories or that will be read from the
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`memories.” Ex. 1001 at 1:51-54. There is no further description in the ’414 Patent
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`as to how the error correction chip would correct errors beyond error checking. The
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`remainder of the description of the error correction chip is directed to its location
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`and physical orientation. The use of the term within the claim itself provides no
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`additional guidance.
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`Accordingly, based on the specification, one or ordinary skill in the art would
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`understand the “error correction chip” to mean “a chip that is able to perform at least
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`12
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`error checking on data stored in other semiconductor memories.” See Ex. 1002, at
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`¶¶26-27.
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`B.
`“Connected”
`In the related Inter partes review (IPR2016-01622) of the ’414 Patent of the
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`Board interpreted the term “connected” in claim 1 as “encompass[ing] being
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`connected to the printed circuit board via a socket.” Case IPR2016-01266, Paper 7,
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`8 (P.T.A.B. February 15, 2017). The term “connected” should be interpreted
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`similarly here, for the same reasons discussed by the Board in the institution decision
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`of IPR2016-01622. Id.
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`VI. PROPOSED GROUNDS OF UNPATENTABILITY
`A. Summary of Grounds of Rejection
`The following chart demonstrates the grounds of rejection and the prior art
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`applied against the challenged claims. With the present grounds of obviousness and
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`the evidence submitted herein, Petitioner has established a reasonable likelihood that
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`it will prevail in establishing unpatentability of claim 4 and requests institution of
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`inter partes review and cancellation of these claims.
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`Ground Claim
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`Basis for Rejection
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`1
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`4
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`Obvious over Simpson in view of Karabatsos, 35 U.S.C. §103
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`9
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`13
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`Obvious over Bechtolsheim in view of Tokunaga and
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`Karabatsos, 35 U.S.C. §103
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` 4
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`
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`2
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`
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`B. Prior Art Offered for the Present Unpatentability Challenges
`The present petition states invalidity grounds under 35 U.S.C. § 103 using the
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`following patents and printed publication prior art:
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` UK Patent Application GB 2 289 573 A to Simpson (“Simpson,” Ex.
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`1002), published on November 22, 1995, filed on May 19, 1995; this
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`reference is prior art under pre-AIA 35 U.S.C. § 102(a).
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` US Patent Application Publication No. 2002/0006032 A1 to Karabatsos
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`(“Karabatsos,” Ex. 1003), was filed in the United States on January 11,
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`2001; this reference is prior art under pre-AIA 35 U.S.C. § 102(e).
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` US Patent No. 5,973,951 to Bechtolsheim et. al. (“Bechtolsheim,” Ex.
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`1004), was published on October 26, 1999; this reference is prior art
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`under pre-AIA 35 U.S.C. § 102(b).
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` US Patent No. 6,038,132 to Tokunaga et. al. (“Tokunaga,” Ex. 1005),
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`was published on March 14, 2000; this reference is prior art under pre-
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`AIA 35 U.S.C. § 102(b).
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` Intel: PC SDRAM Unbuffered DIMM Specification Revision 1.0 (“Intel
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`DIMM Specification,” Ex. 1008), Copyright Dated 1997, published in
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`February of 1998; this reference is prior art under pre-AIA 35 U.S.C. §
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`102(a).
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`C. This Petition Presents Substantially New Arguments and Prior
`Art from that Previously Before the Board
`Petitioner previously filed a petition for IPR of the ’414 patent (hereinafter
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`the “Previous Petition”) upon which the Board instituted an IPR proceeding on
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`claims 1 and 5-8, but declined to institute an IPR proceeding on claims 2-4. See
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`Case IPR2016-01266, Paper 7. The present Petition, however, presents new and
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`substantially different arguments and prior art that illustrate why the ’414 patent
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`should not have been granted. Accordingly, the Board should consider afresh the
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`many new issues raised by the arguments and prior art presented herein.
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`With only one exception, the prior art in the present Petition is wholly new.
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`All of this prior art (four new references) was unknown to Petitioner at the time of
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`the Previous Petition’s filing, and is the product of continued searching. Further, as
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`will be detailed in the grounds below, the memory modules of the new
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`references−Bechtolsheim and Karabatsos−are substantially different in many ways
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`from that of the art, for example Simpson, included in the Previous Petition. For
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`example, Bechtolsheim expressly illustrates a memory module having a vertically
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`oriented semiconductor chip (e.g., oriented perpendicular to the contact strip) that
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`extends a greater distance from the contact strip than other, horizontally oriented
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`semiconductor memory chips. Infra, Ground 2. In addition, Karabatsos expressly
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`discloses a memory module with a “height of between 1.125 and 1.250 inches.”
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`Infra, Grounds 1 and 2. These new references clearly demonstrate that the features
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`of claim 4 of the ’414 Patent, on which the Previous Petition, was not instituted,
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`were not inventive. Thus, the memory modules described herein present different
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`mappings and new, different issues.
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`Although the present Petition does include one prior art reference addressed
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`in the Previous Petition, the application of teachings from within Simpson are now
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`integrated with an entirely new reference, Karabatsos. These new arguments could
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`not have been properly raised in the prior proceeding, such as in a request for
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`rehearing, and thus it was necessary for Petitioner to file this subsequent Petition.
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`Other panels have found that a second petition is a proper vehicle for presenting such
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`new arguments. See Medtronic, Inc. v. Mark A. Barry, IPR2015-00780, Paper 7 at
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`9 n.4 (Sept. 9, 2015) (“Petitioner responds to a noted deficiency in the prior petition
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`with new arguments and supporting evidence that cannot be raised in a request for
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`rehearing.”). Furthermore, the Board has repeatedly found petitions that
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`demonstrate a reasonable likelihood of unpatentability should prevail over § 325(d).
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`See, e.g., First Quality Baby Prods., LLC v. Kimberly-Clark Worldwide, Inc.,
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`IPR2014-01021, Paper 9 at 10 (Dec. 15, 2014) (“We decline to exercise this
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`discretion [under § 325(d)] because we determine that Petitioner has demonstrated
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`a reasonable likelihood that the challenged claims are unpatentable.”); see also SK
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`Innovation Co. v. Celgard, LLC, IPR2014-00680, Paper 11 at 22-23 (Sept. 29,
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`2014); SK Innovation Co. v. Celgard, LLC, IPR2014-00679, Paper 11 at 19 (Sept.
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`29, 2014); Amneal Pharms., LLC v. Supernus Pharms., Inc., IPR2013-00372, Paper
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`8 at 14 (Dec. 17, 2013). Accordingly, Petitioner’s re-use of Simpson is not a basis
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`for denial of the present Petition under § 325(d).
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`Accordingly, in light of the comprehensive nature of the prior art grounds and
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`arguments in the present Petition, the Board should consider the merits of the new
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`arguments and prior art presented herein. This is especially the case as the Patent
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`Owner is asserting claim 4 in litigation against Petitioner and institution of an IPR
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`on claim 4 will potentially streamline that proceeding and allow uniform
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`consideration of whether the bare recitation of a circuit board height in a dependent
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`claim is truly a patentable aspect when the Board has found that the independent
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`claim features warrant institution of an IPR.
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`Finally, Congress chose to put concrete limitations on petitioners’ filings, and
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`chose only to apply the one-year-from-service bar to such filings. See 35 U.S.C. §
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`315(b), (d). The one-year bar plainly affords conscientious petitioners who file early
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`(like Kingston) time to thereafter supplement with an additional filing in the case
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`where, as here, new prior art is discovered through continued due diligence within
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`the one-year period. Declining to review the merits of a Petition presented under
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`such circumstances and declining institution based on § 325(d) would discourage
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`parties from filing early when they have found prior art that they believe to
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`adequately address the claims, for fear that doing so would foreclose presentation of
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`prior art surfaced later within the one-year window. Discouraging early filing,
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`would thus leave civil litigation to continue longer than necessary in frustration of
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`Congressional intent. Furthermore, in the instant case, public policy favors a
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`substantive consideration of the present Petition, because a denial based on § 325(d)
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`under these circumstances would leave the patentability of the ’414 patent in
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`question in view of prior art and arguments in the present Petition, leaving
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`consideration of the same to civil litigation between the parties, and leaving future
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`defendants to also face the expense and time of civil litigation or another
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`separate/future inter partes review.
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`Therefore, the present Petition should be heard on its merits, and the
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`unpatentability of the ’414 patent tested–not dismissed based on § 325(d).
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`VII. THE PRIOR ART RENDERS OBVIOUS CLAIM 4 OF THE ’414
`PATENT
`The discussion below identifies each challenged claim and where the prior art
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`teaches or suggests each portion of the claim, as well as where each portion of the
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`claim is further analyzed in the Subramanian Declaration, and why a person of
`
`ordinary skill would be motivated to modify the base reference as outlined in the
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`relevant obviousness combinations.
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`A. Claim 4 is Rendered Obvious by Simpson in view of the
`Karabatsos
`1.
`Summary of Simpson
`Simpson teaches a memory module that “allows the user to customize the
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`module at the point of use rather than having to use the module configured during
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`its manufacture.” Simpson at 7:8-10. Figs. 1 and 3 below illustrate a first face and
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`a second face, respectively, of the preferred embodiment of the invention and design
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`of a printed circuit board. As is depicted, both Figs. 1 and 3 include nine identical
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`memory chips, which eight in parallel and one in a vertical arrangement.
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`In Simpson, the printed circuit board 2 has a connection terminal 10 for
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`insertion into a module receptacle. Simpson at 10:21-28. The printed circuit board
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`2 also has memory devices 12A-12H on one face of the printed circuit board 2 that
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`are electrically and mechanically connected. Simpson at 10:1-5, Fig. 2. Both faces
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`include sockets 14A-J to add additional memory or logic devices as needed.
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`Simpson at 10:5-12, Fig. 3. Additional memory devices 18A-H can be added using
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`sockets 14C-J. Simpson at 10:21-30.
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`Further, parity memory devices 16 are situated on both faces of the printed
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`circuit board. Simpson at 10:32-11:13. Fig. 1 illustrates the parity memory device
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`16A—parity memory checking being a form of error correction—arranged
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`perpendicular to the connection terminal 10 (i.e. contact strip). Simpson at Fig. 1.
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`And, also as illustrated in Fig. 1, the long sides of sockets 14C-H are arranged
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`parallel to the connection terminal 10 (i.e. contact strip). Id. Simpson appreciates
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`that any devices can be added or replaced by sockets as long as the module has a
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`sufficient amount of memory devices to function. Simpson at 8:5-11.
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`2.
`Eligibility of Simpson As Prior Art
`Simpson is eligible to serve as prior art for the ’414 Patent under 35 U.S.C.
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`§ 102(a) and §102(b). Simpson was published on November 22, 1995 in the United
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`Kingdom, at least five years before the priority date of the ’414 Patent. See Ex.
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`1002, Simpson. Moreover, Simpson was not cited by the USPTO or considered by
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`the Examiner during prosecution of the ’414 Patent. See Ex. 1007.
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`3.
`Summary of Karabatsos
`Karabatsos describes “[a] low profile, registered DIMM [that] has a height of
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`about 1.2 inches, and a width of about 5.25 inches.” Karabatsos at Abstract, FIG.
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`1C. Karabatsos describes that the market demand for higher capacity memory at the
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`time resulted in manufacturers producing many memory modules (e.g., DIMMs) that
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`had “profiles of 1.5 inches or greater.” Id. at ¶¶[0004]-[0020]. Karabatsos
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`recognized that the “unavailability of DIMMs with lower profiles [had] had a
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`serious, negative effect on many computer designs.” Id. at ¶[0020]. Karabatsos
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`further explains the negative effect of tall DIMMs on computer designs lead to server
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`manufacturers designing enclosures around the height of the memory modules or
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`taking “extraordinary steps” to “slant[] . . . DIMM sockets at 22½ degrees.” Id. at
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`¶¶[0021], [0022].
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`In order to address this problem, Karabatsos proposes in FIGS. 1A-1C several
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`different configurations and orientations for mounting memory chips (SDRAMs) to
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`reduce the profile height of memory modules to “between 1.125 and 1.250 inches.”
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`See Id. at ¶[0027], Figures 1A-1C (reproduced below). Karabatsos’s designs
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`incorporate a dense arrangement of SDRAMs and, as shown in FIG. 1C, a
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`rearrangement of SDRAM orientation with a center SDRAM oriented perpendicular
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`to the other SDRAMs. Id.
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`Karabatsos demonstrates that there was a recognized need within the art at the
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`time of the priority date of the ’414 patent to reduce the height of memory modules.
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`Furthermore, Karabatsos also illustrates that it was indeed well-known in the art at
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`the time to re-arrange the layout of memory chips on a memory module to achieve
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`desired dimensions for a memory module. See Subramanian at ¶¶34-40.
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`4.
`Eligibility of Karabatsos as Prior Art
`Karabatsos is eligible to serve as prior art for the ’414 Patent under 35 U.S.C.
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`§ 102(e). Karabatsos was filed on January 11, 2000 in the United States before the
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`priority date of the ’414 Patent. See Ex. 1001. Moreover, Karabatsos was not cited
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`by the USPTO or considered by the Examiner during prosecution of the ’414 Patent.
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`See Ex. 1007.
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`5.
`The Proposed Combination of Simpson and Karabatsos
`Petitioner contends that Simpson in view of Karabatsos renders claim 4 of the
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`’414 Patent obvious. It would have been obvious to modify the printed circuit board
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`and memory module design of Simpson to incorporate the height constraints
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`disclosed by Karabatsos. In the resulting design, Simpson would be constrained and
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`adapted would be constrained to a profile height of “between 1.125 and 1.250
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`inches” in order to address the problem of the “unavailability of DIMMs with lower
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`profiles” as identified by Karabatsos. Karabatsos at ¶¶[0020], [0027]. As described
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`below, one of ordinary skill in the art at the priority date of the ’414 Patent would
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`have been motivated to modify Simpson based on the design dimensions of
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`Karabatsos and would have had a reasonable expectation of success when doing so.
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`See Subramanian at ¶¶50-51. Petitioner provides further details about the proposed
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`combination of Simpson and the Karabatsos, as appropriate, in the sections that
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`follow.
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`
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`a)
`Reasons to Combine
`Simpson does not explicitly provide a height for the disclosed memory
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`module, therefore leaving Simpson open to adaptation, especially since it was well-
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`known in the art at the time to re-arrange the layout of memory chips on a memory
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`module to achieve desired dimensions for a memory module or to follow
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`standardized design choice. See Subramanian at ¶¶19, 23, 52, 104. Further, one of
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`ordinary skill in the art would have been motivated to modify Simpson based on the
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`design dimensions disclosed in Karabatsos to meet the market demand for lower
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`Petition for Inter Partes Review of US Patent No. 6,850,414
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`height memory modules at the time. See Subramanian at ¶50. More specifically,
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`Karabatsos describes that the market demand for higher capacity memory at the time
`
`resulted in manufacturers producing many memory modules (e.g., DIMMs) that had
`
`“profiles of 1.5 inches or greater.” Karabatsos at ¶¶[0004]-[0020]. Karabatsos
`
`recognized that the “unavailability of DIMMs with lower profiles [had] had a
`
`serious, negative effect on many computer designs.” Id. at ¶[0020]. Karabatsos
`
`further explains the negative effect of tall DIMMs on computer designs lead to server
`
`manufacturers designing enclosures around the height of the memory modules or
`
`taking “extraordinary steps” to “slant[] . . . DIMM sockets at 22½ degrees.” Id. at
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`¶¶[0021], [0022]. One of ordinary skill would be aware of this discussion and the
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`solution being solved by Karabatsos and would recognize that the problem of DIMM
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`profile height applied generally