D
`
`Small Outline
`Package Guide
`
`1999
`
`1
`
`KINGSTON 1011
`Kingston v. Polaris
`IPR2016-01622
`
`

`

`Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
`otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions
`of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating
`to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability,
`or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical,
`life saving, or life sustaining applications.
`Intel may make changes to specifications and product descriptions at any time, without notice.
`The 28F800F3, 28F160F3 may contain design defects or errors known as errata which may cause the product to deviate
`from published specifications. Current characterized errata are available on request.
`Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product
`order.
`Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
`obtained from:
`
`Intel Corporation
`P.O. Box 5937
`Denver, CO 80217-9808
`
`or call 1-800-548-4725
`or visit Intel’s Website at http://www.intel.com
`
`COPYRIGHT © INTEL CORPORATION 1996 -1999
`
`*Other brands and names are the property of their respective owners.
`
`CG-041493
`
`2
`
`

`

`-
`
`TABLE OF CONTENTS
`
`CHAPTER 1
`PACKAGE DESCRIPTION
`1.1.
`INTRODUCTION..................................................................................................... 1-1
`1.2.
`PACKAGE INFORMATION...................................................................................... 1-3
`
`CHAPTER 2
`SOP LAYOUT FEATURES AND APPLICATIONS
`2.1.
`SOP SPACE SAVING FEATURES .......................................................................... 2-1
`2.2.
`SOP APPLICATIONS.............................................................................................2-17
`
`CHAPTER 3
`SOP PHYSICAL DIMENSIONS
`3.1.
`SOP CASE OUTLINES............................................................................................ 3-1
`3.2.
`SOP BOARD FOOTPRINTS.................................................................................... 3-9
`3.3.
`SOP COMPONENT VOLUME AND WEIGHT .........................................................3-11
`
`CHAPTER 4
`SOP PACKAGE CHARACTERISTICS
`4.1.
`SOP ELECTRICAL DATA........................................................................................ 4-1
`4.2.
`SOP PACKAGE THERMAL DATA........................................................................... 4-2
`
`CHAPTER 5
`SOP MANUFACTURING
`5.1.
`SOP ASSEMBLY PROCESS FLOW........................................................................ 5-1
`5.2.
`SOP PACKAGE MATERIALS AND METHODS........................................................ 5-2
`5.3.
`SOP TESTING ........................................................................................................ 5-6
`5.3.1.
`Electrical Test...................................................................................................... 5-6
`5.3.2.
`Solderability......................................................................................................... 5-6
`5.3.3.
`Mechanical Inspection ......................................................................................... 5-6
`
`CHAPTER 6
`SOP RELIABILITY STRESSES
`6.1.
`INTRODUCTION..................................................................................................... 6-1
`6.2.
`TEMPERATURE CYCLING CONDITION “C” ........................................................... 6-1
`6.3.
`THERMAL SHOCK CONDITION “C”........................................................................ 6-1
`6.4.
`STEAM (AUTOCLAVE) ........................................................................................... 6-2
`6.5.
`85°C/85% RH.......................................................................................................... 6-2
`6.6.
`HIGH TEMPERATURE DYNAMIC LIFE TEST......................................................... 6-2
`6.7.
`TSOP/PSOP SOLDER JOINT RELIABILITY...........................................................6-13
`6.7.1.
`SMT Considerations ...........................................................................................6-14
`6.7.2.
`About the Data ...................................................................................................6-14
`6.7.3.
`Conclusion..........................................................................................................6-14
`
`iii
`
`3
`
`

`

`CONTENTS
`
`-
`
`CHAPTER 7
`SOP HANDLING
`7.1.
`SOP SHIPPING FORMATS/INFORMATION (TRAYS, TAPE, TUBES)..................... 7-1
`7.1.1.
`SOP Trays........................................................................................................... 7-1
`7.1.2.
`Tray Recycling..................................................................................................... 7-6
`7.1.3.
`Tray Supplier/Brokers .......................................................................................... 7-8
`7.1.4.
`SOP Tape and Reel............................................................................................. 7-8
`7.1.5.
`PSOP Tubes ......................................................................................................7-17
`7.2.
`SOP PACKING REQUIREMENTS..........................................................................7-18
`
`CHAPTER 8
`SOP SMT ASSEMBLY CONSIDERATIONS
`8.1.
`STORAGE AND HANDLING.................................................................................... 8-1
`8.2.
`SCREEN PRINTING................................................................................................ 8-1
`8.2.1.
`Solder Paste........................................................................................................ 8-1
`8.2.2.
`Solder Volume..................................................................................................... 8-1
`8.2.3.
`Solder Mask ........................................................................................................ 8-2
`8.2.4.
`Stencil ................................................................................................................. 8-2
`8.2.5.
`Vision System...................................................................................................... 8-2
`8.2.6.
`Squeegee............................................................................................................ 8-2
`8.3.
`PLACEMENT .......................................................................................................... 8-3
`8.4.
`CLEANING.............................................................................................................. 8-3
`8.5.
`IR FURNACE .......................................................................................................... 8-4
`8.6.
`DESIGN CONSIDERATIONS .................................................................................. 8-4
`8.7.
`PASS/FAILURE MODE EXAMPLES........................................................................ 8-5
`8.8.
`REWORK ISSUES .................................................................................................. 8-7
`
`CHAPTER 9
`SOP ORDERING INFORMATION
`
`CHAPTER 10
`REFERENCES AND ADDITIONAL INFORMATION
`
`APPENDIX A
`SOP SUPPORT TOOLS
`
`APPENDIX B
`REFERENCES
`
`APPENDIX C
`SOP STANDARDS BODIES
`
`iv
`
`4
`
`

`

`-
`inte|®
`
`Package Description
`Package Description
`
`1
`
`5
`
`

`

`6
`
`

`

`-
`
`CHAPTER 1
`PACKAGE DESCRIPTION
`
`INTRODUCTION
`1.1.
`Throughout the electronics industry, a worldwide push towards increased mobility, lower
`power, and higher functionality is placing higher demands on semiconductor devices.
`Today’s form factor driven requirements are leading to new breeds of fine pitch integrated
`circuit packages. Currently, submicron feature size at the die level are driving package
`feature sizes down to the design-rule level of the early technologies. To meet these demands,
`package technology must deliver higher lead counts, reduced lead pitch, minimum footprint
`area, and significant overall volume reduction.
`The Plastic Small Outline Package (PSOP), Thin Small Outline Package (TSOP), and Shrink
`Small Outline Package (SSOP) are the surface mount memory packaging from Intel. These
`Small Outline Packages give users strong packaging choices for all types of applications. In
`addition they support the widest range of nonvolatile memory component densities and
`features for the user’s applications.
`Key features of the Plastic Small Outline Package (PSOP) include:
`• JEDEC standard compliance
`• Footprint and height 50% of DIP
`• Two side leaded for routing simplicity
`• 50 mil (1.27 mm) pitch for SMT simplicity and ease of use
`• Gull wing formed leads for improved SMT manufacturing
`• Supports future flash density and feature growth
`• Outstanding in any temperature application
`Key features of the Thin Small Outline Package (TSOP) include:
`• JEDEC and EIAJ standard dimensions
`• Smallest leaded package from factor for flash
`• 0.5 mm (19.7 mil) lead pitch
`• Reduced total package height, 1.20 mm maximum
`• Gull wing formed leads for improved SMT manufacturing
`• Supports future flash density and feature growth
`
`1-1
`
`7
`
`

`

`PACKAGE DESCRIPTION
`
`-
`
`Key features of the Shrink Small Outline Package (SSOP) include:
`• JEDEC standard compliance
`• Direction for Intel’s higher density flash architectures
`• 0.8 mm (31.5 mil) lead pitch offers handling characteristics similar to 50 mil pitch
`packages
`• Excellent performance in wide temperature applications
`• Two sided and gull wing lead package design
`
`1-2
`
`8
`
`

`

`-
`
`PACKAGE DESCRIPTION
`
`Figure 1-1. Intel’s Flash Memory Small Outline Family
`
`297297-1
`
`1.2. PACKAGE INFORMATION
`The TSOP package is offered in 32-lead, 40-lead, 48-lead and 56-lead versions in JEDEC
`and EIAJ registered standard dimensions. The PSOP and SSOP are JEDEC standard
`compliant.
`
`1-3
`
`9
`
`

`

`PACKAGE DESCRIPTION
`
`-
`
`Figure 1-2. 32-Lead TSOP Package
`
`297297-2
`
`Intel’s 32-lead TSOP package accommodates Intel’s first generation, the 28F010 1-megabit
`and 28F020 2-megabit flash memory devices, in an EPROM-compatible pinout with an easy
`single pin density upgrade path. The 28F001BX 1-megabit Boot Block flash memory is also
`available in the 32-lead TSOP package.
`
`1-4
`
`10
`
`

`

`-
`
`PACKAGE DESCRIPTION
`
`Figure 1-3. 40-Lead TSOP Package
`
`297297-3
`
`Intel’s 28F004SC 4-megabit, 28F008SC 8-megabit and 28F016SC 16-megabit FlashFile™
`memories are offered in a 40-lead TSOP. The 28F002BV/X 2-megabit, 28F004BV/X 4-
`megabit and 28F008BV 8-megabit Boot Block Flash memories are also offered in the 40-
`lead TSOP package. The FlashFile products support an easy single pin upgrade path from the
`4-megabit density to the 16-megabit density. The Boot Block products support a similar
`upgrade path from the 2-megabit density to the 8-megabit density. The package pin count
`also allows for the implementation of Intel’s SmartVoltage architecture. This is designed in
`the SC FlashFile components and the BV Boot Block components. This gives the user the
`choice of low power read, single 5V operation or 12V high speed programming and erase. In
`addition, Intel’s 28F002BC 2-megabit memory is offered in the 40-lead TSOP.
`
`1-5
`
`11
`
`

`

`PACKAGE DESCRIPTION
`
`-
`
`Figure 1-4. 48-Lead TSOP Package
`
`297297-4
`
`Intel’s 48-lead TSOP package is Intel’s latest offering in extremely small form factor
`packaging. Intel’s 28F200CV 2-megabit, 28F400CV 4-megabit and 28F800CV 8-megabit
`Boot Block Flash memories are offered in the 48-lead TSOP package. Like 40-lead TSOP
`there is an easy pinout upgrade path from the 2-megabit Book Block to 4-megabit Boot
`Block density and from the 4-megabit Boot Block to the 8-megabit Boot Block Density. The
`48-lead Boot Block components allow the user to configure in a x8 or x16 organization and
`has Intel’s SmartVoltage technology.
`
`1-6
`
`12
`
`

`

`-
`
`PACKAGE DESCRIPTION
`
`Figure 1-5. 56-Lead TSOP Package
`
`297297-5
`
`1-7
`
`13
`
`

`

`PACKAGE DESCRIPTION
`
`-
`
`The 56-lead TSOP pinout allows for a user configurable x8 or x16 organization in a small
`form factor, and offers room to grow as memory density and features dictate. Intel’s
`28F200BV1 and BX 2-megabit and 28F400BV1 and BX 4-megabit Boot Block Flash
`memories are offered in the 56-lead TSOP package. In addition Intel’s higher density
`products also are offered in a 56-lead TSOP package. They include the 28F016SA and
`28F016SV1 16-megabit FlashFile memories and the DD28F032SA 32-megabit FlashFile
`memory. The DD28F032SA is the result of an advanced packaging innovation that
`encapsulates two 28F016SA die in a single Dual Die Thin Small Outline Package
`(DDTSOP). Intel’s latest offering in 56-lead TSOP are the 28F016XD (x16 architecture only)
`and 28F016XS1.
`These two devices are part of Intel’s High Performance family and were designed with
`optimized system interfaces. The XD device offers a DRAM interface, while the XS device
`offers a synchronous interface.
`
`1 SmartVoltage technology
`
`1-8
`
`14
`
`

`

`-
`
`PACKAGE DESCRIPTION
`
`Figure 1-6. 44-Lead PSOP Package
`
`297297-6
`
`The 44-lead PSOP dimensions are a registered JEDEC standard. Intel’s 28F004SC 4-
`megabit, 28F008SC 8-megabit and 28F016SC 16-megabit FlashFile memories are offered in
`the 44-lead PSOP. The 28F200BV/X 2-megabit, 28F400BV/X 4-megabit and 28F800BV 8-
`megabit Boot Block flash memories are also offered in the 44-lead PSOP. The Boot Block
`flash memories feature a ROM-compatible pinout in a user configurable x8 or x16
`organization. The 28F002BC 2-megabit memory is also offered in the 44-lead PSOP.
`
`1-9
`
`15
`
`

`

`PACKAGE DESCRIPTION
`
`-
`
`Figure 1-7. 56-Lead SSOP Package
`
`297297-7
`
`The 56-lead SSOP is a recent SOP offering from Intel. The package dimensions are in
`compliance with JEDEC standards. The SSOP is the direction for Intel’s higher density flash
`architectures in high reliability applications. Intel currently offers the 28F016SA and has
`plans to put the 28F016SV2 16-megabit FlashFile and the 28F016XS2 16-megabit Embedded
`Flash RAM in the package.
`
`2 SmartVoltage technology
`
`1-10
`
`16
`
`

`

`-
`
`SOP Layout Features
`and Applications
`
`2
`
`17
`
`

`

`18
`
`18
`
`

`

`-
`
`CHAPTER 2
`SOP LAYOUT FEATURES AND APPLICATIONS
`
`2.1. SOP SPACE SAVING FEATURES
`The PSOP (Plastic Small Outline Package), SSOP (Shrink Small Outline Package), and
`TSOP (Thin Small Outline Package) offer several features that minimize the total volume
`consumed by memory components in a system design. The 1.2 mm thickness of the TSOP is
`one-third to one-half that of the SOICs, SOJs and PLCCs. The TSOP package’s two sided
`pinouts and standard/reverse pinout offerings minimize both board area and circuit board
`layers consumed by memory. The 2.80 mm thickness of the PSOP and 1.80 mm thickness of
`the SSOP are less than half that of standard Plastic DIP (PDIP) packages.
`The PSOP and SSOP feature 1.27 mm (50 mil) and 0.8 mm pitch gull wing leads
`respectively. The leads on the PSOP and SSOP are located on the two long sides of the
`package. The TSOP features 0.5 mm pitch gull wing leads located on the two short sides of
`the package. Positioning the leads in this manner leaves two sides of the package open. The
`open sides of the package can be used to route traces under the component, thus saving board
`layers and simplifying board layout. Because the leads are on two sides of the package rather
`than four, all three packages can be placed much closer to each other and to other
`components on the board.
`
`2-1
`
`19
`
`

`

`SOP LAYOUT FEATURES AND APPLICATIONS -
`
`Figure 2-1. 32-Lead TSOP Package Pinout
`for 28F001BX, 28F010 and 28F020—Standard Pinout
`
`297298-1
`
`297298-2
`
`Figure 2-2. 32-Lead TSOP Package Pinout
`for 28F001BX, 28F010 and 28F020—Reverse Pinout
`
`2-2
`
`20
`
`

`

`- SOP LAYOUT FEATURES AND APPLICATIONS
`
`Figure 2-3. 40-Lead TSOP Package Pinout for 28F008SA—Standard Pinout
`
`Figure 2-4. 40-Lead TSOP Package Pinout for 28F008SA—Reverse Pinout
`
`297298-3
`
`297298-4
`
`2-3
`
`21
`
`

`

`SOP LAYOUT FEATURES AND APPLICATIONS -
`
`297298-14
`
`297298-25
`
`NOTE:
`Pinout above is SmartVoltage BV version.
`Pin 12 is DU for BX/BL 12V VPP versions.
`Figure 2-5. The 40-Lead TSOP Pinout for
`28F002BV and BX, 28F004BV and BX, and 28F008BV
`
`Figure 2-6. The 40-Lead TSOP Pinout for
`28F004SC, 28F008SC, and 28F016SC
`
`2-4
`
`22
`
`

`

`- SOP LAYOUT FEATURES AND APPLICATIONS
`
`Figure 2-7. The 40-Lead TSOP Pinout for
`X01 2M BIOS, 28F002BV, 28F002BC, and 28F002BX
`
`297298-26
`
`2-5
`
`23
`
`

`

`SOP LAYOUT FEATURES AND APPLICATIONS -
`
`Figure 2-8. The 44-Lead PSOP Pinout for
`X01 2M BIOS Chip, 28F200BV, 28F002BC, 28F200BX vs. AMD 29F200
`
`297298-27
`
`2-6
`
`24
`
`

`

`- SOP LAYOUT FEATURES AND APPLICATIONS
`
`Figure 2-9. The 44-Lead PSOP Pinout for
`28F004SC, 28F008SC, and 28F016SC
`
`297298-28
`
`2-7
`
`25
`
`

`

`SOP LAYOUT FEATURES AND APPLICATIONS -
`
`NOTE:
`Pinout above is SmartVoltage BV version.
`Pin 2 is DU for BX/BL 12V VPP versions, but for the 8-Mbit device, pin 2 has been changed to A18 (WP# on
`2/4 Mbit). Designs planning on upgrading to the 8-Mbit density from the 2/4-Mbit density in this package
`should design pin 2 to control WP# functionality at the 2/4-Mbit level and allow for pin 2 to control A18 after
`upgrading to the 8-Mbit density.
`Figure 2-10. The 44-Lead PSOP Pinout for
`28F200BV and BX, 28F400BV and BX, and 28F800BV
`
`297298-15
`
`2-8
`
`26
`
`

`

`- SOP LAYOUT FEATURES AND APPLICATIONS
`
`Figure 2-11. 44-Lead PSOP Package Pinout for 28F008SA
`
`297298-6
`
`2-9
`
`27
`
`

`

`SOP LAYOUT FEATURES AND APPLICATIONS -
`
`48
`47
`46
`45
`44
`43
`42
`41
`40
`39
`38
`37
`36
`35
`34
`33
`32
`31
`30
`29
`28
`27
`26
`25
`
`28F400CV
`A16
`BYTE#
`GND
`DQ15/A-1
`DQ7
`
`DQ14DQ6DQ13
`DQ5DQ12
`DQ4
`VCC
`DQ11
`DQ3
`DQ10DQ2
`DQ9
`DQ1
`DQ8
`DQ0
`OE#
`GND
`CE#
`A0
`
`A16
`BYTE#
`GND
`DQ15/A-1
`DQ7
`
`DQ14DQ6DQ13
`DQ5DQ12
`DQ4
`VCC
`DQ11
`DQ3
`DQ10DQ2
`DQ9
`DQ1
`DQ8
`DQ0
`OE#
`GND
`CE#
`A0
`
`28F800CV
`A16
`BYTE#
`GND
`DQ15 /A-1
`DQ7
`
`DQ14DQ6DQ13
`DQ5DQ12
`DQ4
`VCC
`DQ11
`DQ3
`DQ10DQ2
`DQ9
`DQ1
`DQ8
`DQ0
`OE#
`GND
`CE#
`A0
`
`297298-19
`
`28F200CV
`48-LEAD TSOP
`12 mm x 20 mm
`
`TOP VIEW
`
`Boot Block
`
`123456789
`
`10
`11
`12
`13
`14
`15
`16
`17
`18
`19
`20
`21
`22
`23
`24
`
`28F800CV
`A15
`A14
`A13
`A12
`A11
`A10
`A9
`A8
`NC
`NC
`WE#
`RP#
`VPP
`WP#
`NC
`A18
`A17
`A7A6
`A5A4
`A3
`A2
`A1
`
`28F400CV
`A15
`A14
`A13
`A12
`A11
`A10
`A9
`A8
`NC
`NC
`WE#
`RP#
`VPP
`WP#
`NC
`NC
`A17
`A7A6
`A5A4
`A3
`A2
`A1
`
`A15
`A14
`A13
`A12
`A11
`A10
`A9
`A8
`NC
`NC
`WE#
`RP#
`VPP
`WP#
`NC
`NC
`NC
`
`A7A6
`A5A4
`A3
`A2
`A1
`
`NOTE:
`CV Pinout is SmartVoltage technology.
`Figure 2-12. The 48-Lead TSOP Pinout
`for 28F200CV, 28F400CV and 28F800CV
`
`2-10
`
`28
`
`

`

`- SOP LAYOUT FEATURES AND APPLICATIONS
`
`NOTE:
`Pinout above is SmartVoltage BV version.
`Pin 18 is DU for BX/BL 12V VPP versions.
`Figure 2-13. The 56-Lead TSOP Pinout
`for 28F200BV and BX, and 28F400BV and BX
`
`297298-20
`
`2-11
`
`29
`
`

`

`SOP LAYOUT FEATURES AND APPLICATIONS -
`
`NOTE:
`E28F016SV is SmartVoltage technology.
`Figure 2-14. 28F016SV 56-Lead TSOP Pinout Configuration
`Shows Compatibility with 28F016SA/28F032SA
`
`297298-16
`
`2-12
`
`30
`
`

`

`- SOP LAYOUT FEATURES AND APPLICATIONS
`
`Figure 2-15. 28F016XS 56-Lead TSOP Pinout Configuration Shows
`Compatibility with the 28F016SA/SV, Allowing for
`Easy Performance Upgrades from Existing 16-Mbit Designs
`
`297298-17
`
`2-13
`
`31
`
`

`

`SOP LAYOUT FEATURES AND APPLICATIONS -
`
`Figure 2-16. 28F016XD 56-Lead TSOP Type I Pinout Configuration
`
`297298-18
`
`2-14
`
`32
`
`

`

`- SOP LAYOUT FEATURES AND APPLICATIONS
`
`NOTE:
`DA28F016SV is SmartVoltage technology.
`Figure 2-17. 56-Lead SSOP Pinout Configuration
`
`297298-23
`
`2-15
`
`33
`
`

`

`SOP LAYOUT FEATURES AND APPLICATIONS -
`
`Figure 2-18. 28F016XS 56-Lead SSOP Pinout Configuration
`Shows Compatibility with the 28F016SA/SV, Allowing for
`Easy Performance Upgrades from Existing 16-Mbit Designs
`
`297298-24
`
`2-16
`
`34
`
`

`

`- SOP LAYOUT FEATURES AND APPLICATIONS
`
`2.2. SOP APPLICATIONS
`SOP packages support the trend toward miniaturization by consuming one-third to one-half
`the volume of earlier packaging alternatives. SOP components are a logical choice for the
`small form factor of handheld instruments, portable communication devices, laptop and
`notebook PCs, disk drives, and numerous other applications.
`In particular, TSOP components can be used to maximize the memory packing density for a
`given volume constraint. This extra memory can expand the amount of data collected in data
`acquisition applications or add density to solid state code storage in embedded control, data
`files and reprogrammable environments. An excellent example is the storage of embedded
`firmware or application code on a flash-based solid state disk drive or in resident flash
`memory arrays. The use of flash memory enhances product performance by eliminating the
`slow, power hungry disk to DRAM software down-loads, thereby decreasing system power
`up and response time and increasing battery life.
`Intel’s TSOP packages open up a number of applications. One example is the memory card.
`The 1.2 mm package height of the TSOP package allows the packing of a board with TSOP
`devices mounted on both sides with the 3.3 mm PCMCIA/JEIDA standard memory card
`thickness. Many of Intel’s flash architectures are also offered in die form in Intel’s
`SmartDie™ family of products. The SmartDie products allow for direct chip attachment.
`Intel’s flash components in TSOP package and Intel’s flash products in the SmartDie family
`see a complete test flow prior to board mounting. Complete product testing prior to assembly
`allows arrays of devices to be mounted with predictable reliability and manufacturing yields.
`
`2-17
`
`35
`
`

`

`SOP LAYOUT FEATURES AND APPLICATIONS -
`
`Figure 2-19. TSOP Is Ideal for Memory Card Applications
`
`Figure 2-20. TSOP Enables New Form Factor Designs and New Innovations
`
`297298-21
`
`2-18
`
`36
`
`

`

`- SOP LAYOUT FEATURES AND APPLICATIONS
`
`Intel components in PSOP are ideally suited for a number of areas and in particular work
`well in environments that currently use the PLCC package in applications. User benefits
`include increased flexibility. This is a result of present and future densities and features that
`the PSOP enables. Intel’s Boot Block architecture is available in PSOP which features Intel’s
`SmartVoltage technology. This allows the user to choose low power 3.3V read, 5V only
`operation, or high speed programming or erase with 12V. The 12V option is ideally suited for
`users who pre-program the component prior to assembly. The faster programming capability
`saves time and equipment in manufacturing. The PSOP’s 50 mil lead pitch also allows the
`user to make an easy transition to SOP. The package is easily adopted in today’s 50 mil
`programming and board assembly environment that supports PLCC. In particular PSOP is a
`good choice for office automation, industrial control, networking and consumer applications.
`PSOP pitch and lead height make it an excellent choice for any application that will be
`exposed to a wide or even extreme temperature condition. Likewise SSOP with its 0.8 mm
`pitch and similar lead height to PSOP makes it perform similar to PSOP and PLCC. SSOP is
`the high reliability package direction for Intel’s higher density architectures and is an
`excellent choice in applications that will be exposed to a wide range of temperature
`conditions. SSOP can be easily implemented into the 50 mil pitch assembly environment.
`One other SOP benefit for assembly is the package’s gull wing leads. The exposed lead
`design allows for easier inspection of the leads solder joints.
`
`Figure 2-21. PSOP Is Easy to Implement and Enables Unique Capabilities
`
`297298-22
`
`2-19
`
`37
`
`

`

`38
`
`38
`
`

`

`E
`
`SOP Physical
`Dimensions
`
`3
`
`39
`
`

`

`40
`
`40
`
`

`

`E
`
`CHAPTER 3
`SOP PHYSICAL DIMENSIONS
`SOP CASE OUTLINES
`3.1.
`Intel’s 32-lead TSOP meets the EIAJ and JEDEC registered standard.
`
`Z
`
`Pin 1
`
`See Note 1 and 3
`
`See Note 2
`
`A2
`
`See Detail B
`
`e
`
`Y
`
`A1
`Seating
`Plane
`
`D1
`D
`
`See Detail A
`
`Detail B
`
`Detail A
`
`A2
`
`b
`
`E
`
`A
`
`C
`
`0
`
`L
`
`Figure 3-1. 32-Lead TSOP Package Drawing and Specifications
`
`[231369-65]
`A5567-01
`
`Package Height
`Standoff
`Package Body Thickness
`Lead Width
`Lead Thickness
`Package Body Length
`Package Body Width
`Lead Pitch
`Terminal Dimension
`Lead Tip Length
`Lead Count
`Lead Tip Angle
`Seating Plane Coplanarity
`Lead to Package Offset
`
`Symbol Min
`A
`A1
`A2
`b
`c
`D1
`E
`e
`D
`L
`N
`Ø
`Y
`Z
`
`0°
`
`0.150
`
`0.250
`
`0.050
`1.025
`0.995
`0.965
`0.300
`0.200
`0.150
`0.200
`0.150
`0.100
`18.200 18.400 18.600
`7.800
`8.000
`8.200
`0.500
`19.800 20.000 20.200
`0.500
`0.600
`0.700
`32
`3°
`
`Millimeters
`Nom
`
`Max
`1.200
`
`Notes
`
`Min
`
`Inches
`Nom
`
`0.039
`0.008
`0.006
`0.724
`0.315
`0.0197
`0.787
`0.024
`32
`3°
`
`4
`4
`
`0.002
`0.038
`0.006
`0.004
`0.717
`0.307
`
`0.780
`0.020
`
`0°
`
`0.006
`
`0.010
`
`Max
`0.047
`
`0.040
`0.012
`0.008
`0.732
`0.323
`
`0.795
`0.028
`
`5°
`0.004
`0.014
`
`Notes
`
`4
`4
`
`3-1
`
`5°
`0.100
`0.350
`
`41
`
`

`

`SOP PHYSICAL DIMENSIONS
`
`Intel’s 40-lead TSOP meets the EIAJ and JEDEC registered standard.
`
`E
`
`Z
`
`Pin 1
`
`See Note 1 and 3
`
`See Note 2
`
`A2
`
`D1
`D
`
`Detail B
`
`Detail A
`
`b
`
`E
`
`A
`
`L
`
`C
`
`0
`
`e
`
`Y
`
`A1
`Seating
`Plane
`
`Figure 3-2. 40-Lead TSOP Package Drawing and Specifications
`
`231369-81
`A5570-01
`
`Millimeters
`
`Nom
`
`0.995
`0.200
`0.150
`
`Max
`1.200
`
`1.025
`0.300
`0.200
`
`0.050
`0.965
`0.150
`0.100
`
`Notes
`
`4
`4
`
`Inches
`
`Notes
`
`Min
`
`Nom
`
`4
`4
`
`0.002
`0.038
`0.006
`0.004
`
`0.717
`0.386
`
`0.780
`0.020
`
`0°
`
`0.039
`0.008
`0.006
`
`0.724
`0.394
`0.0197
`0.787
`0.024
`40
`3°
`
`0.006
`
`0.010
`
`Max
`0.047
`
`0.040
`0.012
`0.008
`
`0.732
`0.402
`
`0.795
`0.028
`
`5°
`0.004
`0.014
`
`20.200
`0.700
`
`5°
`0.100
`0.350
`
`Package Height
`Standoff
`Package Body Thickness
`Lead Width
`Lead Thickness
`Package Body Length
`Package Body Width
`Lead Pitch
`Terminal Dimension
`Lead Tip Length
`Lead Count
`Lead Tip Angle
`Seating Plane Coplanarity
`Lead to Package Offset
`
`3-2
`
`Symbol Min
`A
`A1
`A2
`b
`c
`D1
`E
`e
`D
`L
`N
`Ø
`Y
`Z
`
`18.200 18.400 18.600
`9.800
`10.000 10.200
`0.500
`20.00
`0.600
`40
`3°
`
`19.800
`0.500
`
`0°
`
`0.150
`
`0.250
`
`42
`
`

`

`E
`
`SOP PHYSICAL DIMENSIONS
`
`Z
`
`Pin 1
`
`See Notes 1, 2 and 3
`
`A2
`
`E
`
`e
`
`See Detail B
`
`Y
`
`A1
`Seating
`Plane
`
`A
`
`Detail A
`
`C
`
`0
`
`L
`
`D1
`D
`
`See Detail A
`
`Detail B
`
`b
`
`Figure 3-3. 48-Lead TSOP Package Drawing and Specifications
`
`[231369-98]
`A5568-01
`
`Package Height
`Standoff
`Package Body Thickness
`Lead Width
`Lead Thickness
`Package Body Length
`Package Body Width
`Lead Pitch
`Terminal Dimension
`Lead Tip Length
`Lead Count
`Lead Tip Angle
`Seating Plane Coplanarity
`Lead to Package Offset
`
`Symbol Min
`A
`A1
`A2
`b
`c
`D1
`E
`e
`D
`L
`N
`Ø
`Y
`Z
`
`0°
`
`0.150
`
`0.250
`
`Millimeters
`
`Nom
`
`Max
`1.200
`
`Inches
`
`Notes
`
`Min
`
`Nom
`
`4
`4
`
`0.002
`0.037
`0.006
`0.004
`0.717
`0.465
`
`0.780
`0.020
`
`0°
`
`0.039
`0.008
`0.006
`0.724
`0.472
`0.0197
`0.787
`0.024
`48
`3°
`
`0.006
`
`0.010
`
`5°
`0.100
`0.350
`
`0.050
`1.050
`1.000
`0.950
`0.300
`0.200
`0.150
`0.200
`0.150
`0.100
`18.200 18.400 18.600
`11.800 12.000 12.200
`0.500
`19.800 20.000 20.200
`0.500
`0.600
`0.700
`48
`3°
`
`Max
`0.047
`
`0.041
`0.012
`0.008
`0.732
`0.480
`
`0.795
`0.028
`
`5°
`0.004
`0.014
`
`Notes
`
`4
`4
`
`3-3
`
`43
`
`

`

`SOP PHYSICAL DIMENSIONS
`
`The 56-Lead TSOP meets the JEDEC registered standard. The same standard is being circulated
`for approval by EIAJ.
`
`Z
`
`Pin 1
`
`See Notes 1 and 3
`
`See Note 2
`
`A2
`
`e
`
`E
`
`See Detail B
`
`Y
`
`A1
`Seating
`Plane
`
`A
`
`Detail B
`
`b
`
`D1
`D
`
`See Detail A
`
`Detail A
`
`C
`
`0
`
`L
`
`[231369-90]
`A5569-01
`
`Package Height
`Standoff
`Package Body Thickness
`Lead Width
`Lead Thicknes
`Package Body Length
`Package Body Width
`Lead Pitch
`Terminal Dimension
`Lead Tip Length
`Lead Count
`Lead Tip Angle
`Seating Plane Coplanarity
`Lead to Package Offset
`
`Millimeters
`
`Inches
`
`Sym
`
`Min
`
`Nom
`
`A
`A1
`A2
`b
`c
`D1
`E
`e
`D
`L
`N
`∅
`
`Y
`Z
`
`0.050
`0.965
`0.100
`0.100
`18.200
`13.800
`
`19.800
`0.500
`
`0°
`
`0.995
`0.150
`0.150
`18.400
`14.000
`0.500
`20.00
`0.600
`56
`3°
`
`0.150
`
`0.250
`
`Max
`
`1.200
`
`1.025
`0.200
`0.200
`18.600
`14.200
`
`20.200
`0.700
`
`5°
`0.100
`0.350
`
`Notes
`
`Min
`
`Nom
`
`4
`4
`
`0.002
`0.038
`0.004
`0.004
`0.717
`0.543
`
`0.780
`0.020
`
`0°
`
`0.039
`0.006
`0.006
`0.724
`0.551
`0.0197
`0.787
`0.024
`56
`3°
`
`0.006
`
`0.010
`
`Max
`
`0.047
`
`0.040
`0.008
`0.008
`0.732
`0.559
`
`0.795
`0.028
`
`5°
`0.004
`0.014
`
`Notes
`
`4
`4
`
`Figure 3-4. 56-Lead TSOP Package Drawing and Specifications
`
`3-4
`
`44
`
`

`

`E
`
`SOP PHYSICAL DIMENSIONS
`
`Thin Small Outline Package (TSOP)
`Table 3-1. Symbol List for Thin Small Outline Package Family
`Letter or Symbol
`Description of Dimensions
`A
`A1
`A2
`A3
`b
`c
`D1
`E
`e
`D
`L
`N
`Y
`Z
`Ø
`
`Overall Height
`Standoff
`Package Body Thickness
`Lead Height
`Width of Terminal Leads
`Thickness of Terminal Leads
`Plastic Body Length
`Package Body Width
`Lead Pitch
`Terminal Dimension
`Lead Foot Length
`Total Number of Potentially Usable Lead Positions
`Seating Plane Coplanarity
`Lead to Package Offset
`Lead Tip Angle
`
`Packaging Family Attributes
`Thin Small Outline Package
`TSOP
`Dual-In-Line, Type I
`32, 40, 48, 56
`Solder Plate
`0.5 mm
`Surface Mount
`
`Category
`Acronym
`Lead Configuration
`Lead Counts
`Lead Finish
`Lead Pitch
`Board Assembly Type
`NOTES:
`1-3. (1) If a dimple and a triangle are both present, the triangle denotes pin 1. (2) If only a dimple is present,
` it denotes pin 1. (3) If two dimples are present, the larger dimple denotes pin 1.
`Profile Tolerance zones for D1 and E do not include mold protrusion. (Allowable mold protrusion on
`D1 is 0.25 mm per side and on E is 0.25 mm per side.
`5. Lead Plating Thickness is 0.007 mm–0.015 mm. (Not part of b or c dimensions).
`6.
`32-, 40-, 48-, 56-Lead TSOP: Copper Alloy.
`7. Novalac Body.
`
`4.
`
`3-5
`
`45
`
`

`

`SOP PHYSICAL DIMENSIONS
`
`E
`
`The 44-Lead PSOP meets the EIAJ registered standard. The same standard is being circulated
`for approval by JEDEC.
`
`44
`
`1
`
`23
`
`22
`
`DE
`
`A
`
`A1
`
`D1
`
`Y
`
`C
`
`0
`
`Detail A
`
`L
`
`A2
`
`A
`
`e
`
`b
`
`See Detail A
`
`[231369-80]
`A5565-01
`
`Figure 3-5. 44-Lead PSOP Package Drawing and Specifications
`
`0.050
`2.20
`0.35
`0.13
`28.00
`13.10
`
`Symbol Min
`A
`A1
`A2
`b
`c
`D1
`E
`e
`D
`L
`Y
`Ø
`
`15.75
`0.75
`
`Inches
`
`Notes
`
`Min
`
`Nom
`
`0.020
`0.087
`0.014
`0.005
`1.102
`0.516
`
`0.620
`0.030
`
`0.091
`0.016
`0.006
`1.110
`0.524
`0.050
`0.630
`0.031
`
`3
`3
`
`Millimeters
`
`Nom
`
`2.30
`0.40
`0.150
`28.20
`13.30
`1.27
`16.00
`0.80
`
`Max
`2.95
`
`2.40
`0.50
`0.20
`28.40
`13.50
`
`16.25
`0.85
`0.10
`8°
`
`Notes
`
`3
`3
`
`Max
`0.116
`
`0.094
`0.020
`0.008
`1.118
`0.531
`
`0.640
`0.33
`0.004
`8°
`
`Package Height
`Standoff
`Package Body Thickness
`Lead Width
`Lead Thickness
`Package Body Length
`Package Body Width
`Lead Pitch
`Terminal Dimension
`Lead Tip Length
`Seating Plane Coplanarity
`Lead Tip Angle
`
`3-6
`
`46
`
`

`

`E
`
`See Note 1
`
`SOP PHYSICAL DIMENSIONS
`
`A2
`
`A3
`
`DE
`
`Detail A
`
`0
`
`L
`
`D1
`
`b
`
`e
`
`e
`
`A
`
`A1
`
`Y
`
`See Detail A
`
`NOTE:
`1. One dimple on package denotes Pin 1. If two dimples exist, Pin 1 will always be in the lower left corner
`of the package, in reference to the product mark.
`
`A6741-01
`
`Figure 3-6. 56-Lead SSOP Package Drawing and Specifications
`
`Package Height
`Standoff
`Package Body Thickness
`Lead Width
`Lead Thickness
`Package Body Length
`Package Body Width
`Lead Pitch
`Terminal Dimension
`Lead Count
`Lead Tip Length
`Seating Plane Coplanarity
`Lead Height
`Lead Tip Angle
`
`0.47
`1.18
`0.25
`0.13
`23.40
`13.10
`
`15.70
`
`0.750
`
`Symbol Min
`A
`A1
`A2
`b
`c
`D1
`E
`e
`D
`N
`L
`Y
`A3
`Ø
`
`1.30
`
`1.28
`0.30
`0.15
`23.70
`13.30
`0.80
`16.000
`56
`0.80
`
`1.40
`
`1.38
`0.40
`0.20
`24.00
`13.50
`
`16.30
`
`0.85
`0.10
`1.50
`5°
`
`Millimeters
`
`Nom
`1.80
`
`Max
`1.90
`
`Notes
`
`Min
`
`Inches
`
`Nom
`0.070
`
`0.050
`0.012
`0.006
`0.933
`0.524
`0.0315
`0.630
`56
`0.315
`
`3
`3
`
`0.018
`0.046
`0.010
`0.005
`0.921
`0.516
`
`0.618
`
`0.030
`
`0.051
`
`0.055
`
`Max
`0.075
`
`0.054
`0.016
`0.008
`0.945
`0.531
`
`0.642
`
`0.033
`0.004
`0.059
`5°
`
`Notes
`
`3
`3
`
`3-7
`
`47
`
`

`

`SOP PHYSICAL DIMENSIONS
`
`E
`
`Plastic Small Outline Package/Shrink Small Outline Package
`(PSOP/SSOP)
`Table 3-2. Symbol List for PSOP and SSOP Packages
`Letter or Symbol
`Description of Dimensions
`A
`A1
`A2
`b
`c
`D1
`E
`e
`D
`L
`N
`Y
`Z
`Ø
`
`Overall Height
`Standoff
`Package Body Thickness
`Width of Terminal Leads
`Thickness of Terminal Leads
`Plastic Body Length
`Package Body Width
`Lead Pitch
`Terminal Dimension
`Lead Tip Length
`Total Number of Leads
`Seating Plane Coplanarity
`Lead to Package Offset
`Lead Tip Angle
`
`Packaging Family Attributes
`Plastic Small Outline Package/Shrink Small Outline Package
`PSOP/SSOP
`44/56
`Solder Plate
`1.27 mm/0.8 mm
`Surface Mount
`JEDEC and EIAJ
`
`Category
`Acronym
`Lead Counts
`Lead Finish
`Lead Pitch
`Board Assembly Type
`Standard Registration
`NOTES:
`1. Copper Alloy 194.
`2. Novalac Body.
`3. Profile Tolerance zones for D1 and E do not include mold protrusion. (Allowable mold protrusion on D1
`is 0.25 mm per side and on E is 0.15 mm per side.
`Lead Plating Thickness is 0.007 mm–0.015 mm. (Not part of b or c dimensions).
`
`4.
`
`3-8
`
`48
`
`

`

`E
`
`SOP PHYSICAL DIMENSIONS
`
`3.2.
`
`SOP BOARD FOOTPRINTS
`NOTE:
`The WWW version of this document varies from the hard copy. Figures 3-7
`through 3-9 have been deleted and replaced by the following figure and table
`in order to clarify the dimensions of typical TSOP, PSOP and SSOP land pads
`on line.
`
`B
`
`A
`
`NOTE:
`Dimensions in mm (mils)
`
`C
`
`D
`
`E
`
`SOPGuide
`
`Typical Land Pad Diagram
`
`Package Type
`32-L TSOP
`40-L TSOP
`48-L TSOP
`56-L TSOP
`56-L SSOP
`44-L PSOP
`
`A
`7.80 (307.1)
`9.80 (385.8)
`11.80 (464.6)
`13.80 (543.3)
`22.00 (866.1)
`27.17 (1069.7)
`
`B
`20.80 (818.9)
`20.80 (818.9)
`20.80 (818.9)
`20.80 (818.9)
`16.90 (665.4)
`16.90 (665.4)
`
`C
`0.50 (19.7)
`0.50 (19.7)
`0.50 (19.7)
`0.50 (19.7)
`0.80 (31.5)
`1.27 (50.0)
`
`D
`0.30 (