---
`
`CSMNCD
`CSMNCD
`
`
`ISOIIEC 8802-3 : 1993 ISOIIEC 8802-3 : 1993
`ANSVIEEE Std 802.3. 1993 Edition
`ANSVIEEE Std 802.3. 1993 Edition
`
`7.4 Electrical Characteristics. Terms BR and BRJ2 have very specific meaning as used in this
`7.4 Electrical Characteristics. Terms BR and BRJ2 have very specific meaning a" used in thi"
`subsection. The term BR is used to mean the bit rate of the highest signaling rate supported by anyone
`subsection. The term BR is used to mean the bit rate of the highest signaling rate supported by anyone
`implementation of this interface, BRJ2 is used to mean half the bit rate of the lowest signaling rate
`implementation of this interface, BRJ2 is used to mean half the bit rate of the lowest signaling rate
`supported by anyone implementation of this interface (see 7.3.2). An interface may support one or more
`supported by anyone implementation of this interface (see 7.3.2). An interface may support one or more
`signaling rates .
`signaling rates.
`
`
`NOTE: The characteristics of the driver and receiver can be achieved with standard ECL logic with the addition of an appropriate NOTE: The characteristics of the driver and receiver can be achieved with standard ECL logic with the addition of an appropriate
`coupling network; however, this implementation is not mandatory.
`coupling network; however, this implementation is not mandatory.
`
`7.4.1 Driver Characteristics. The driver is a differential driver capable of driving the specified 78 Q
`7.4.1 Driver Characteristics. The driver is a differential driver capable of driving the specified 78 Q
`interface cable. Only the parameters necessary to ensure compatibility with the specified receiver and to
`interface cable. Only the parameters necessary to ensure compatibility with the specified receiver and to
`assure personnel safety at the interface !::onnector are specified in the following sections.
`assure personnel safety at the interface ~onnector are specified in the following sections.
`
`7.4.1.1 Differential Output Voltage, Loaded. Drivers shall meet all requirements of this section
`7.4.1.1 Differential Output Voltage, Loaded. Drivers shall meet all requirements of this section
`under two basic sets of test conditions (that is, each of two resistive values). For drivers located within a
`under two basic sets of test conditions (that is, each of two resistive values). For drivers located within a
`DTE, a combined inductive load of 27 ~H ± 1% and either a 73 or 83 Q ± 1% resistive load shall be used. For
`DTE, a combined inductive load of 27 ~H ± 1% and either a 73 or 83 Q ± 1% resistive load shall be used. For
`a driver located within a MAU, a combined inductive load of 50 ~H ± 1% and either 73 or 83 Q ± 1% resis(cid:173)
`a driver located within a MAU, a combined inductive load of 50 ~H ± 1% and either 73 or 83 Q ± 1% resis(cid:173)
`tive load shall be used.
`tive load shall be used.
`The differential output voltage, V dm, is alternately positive and negative in magnitude with respect to
`The differential output voltage, V dm, is alternately positive and negative in magnitude with respect to
`zero voltage. The value of V dm into either of the two test loads identified above (R = 73 .Q or 83 Q ± 1%) at
`zero voltage. The value of V dm into either of the two test loads identified above (R = 73 .Q or 83 Q ± 1 o/e) at
`the interface connector of the driving unit shall satisfy the conditions defined by values VI, V 2, and V 3
`the interface connector of the driving unit shall satisfY the conditions defined by values VI, V 2, and V 3
`shown in Fig 7-11 for signals in between BR and BRJ2 meeting the frequency and duty cycle tolerances
`shown in Fig 7-11 for signals in between BR and BRJ2 meeting the frequency and duty cycle tolerances
`specified for the signal being driven. The procedure for measuring and applying the test condition is as
`specified for the signal being driven. The procedure for measuring and applying the test condition is as
`follows:
`follows:
`
`(1) Measure the output voltage Vdm for the driver being tested at the waveform point after overshoot,
`(1) Measure the output voltage Vdm for the driver being tested at the waveform point after overshoot,
`before droop, under test load conditions of 7.4.1.1. This voltage is V 2.
`before droop, under test load conditions of 7.4.1.1. This voltage is V 2.
`(2) Calculate VIand V 3.
`(2) Calculate VIand V 3·
`(3) VI shall be < 1315 mY, V3 shall be> 450 mv'
`(3) VI shall be < 1315 mY, V3 shall be > 450 mY.
`(4) The waveform shall remain within shaded area limits.
`(4) The waveform shall remain within shaded area limits.
`
`The differential output voltage magnitude, Vdm, into either ofthe two test loads identified above, at the
`The differential output voltage magnitude, V dm, into either of the two test loads identified above, at the
`interface connector of the driving unit during the idle state shall be within 40 m V of 0 V. The current into
`interface connector of the driving unit during the idle state shall be within 40 m V of 0 Y. The current into
`either of the two test loads shall be limited to 4 rnA.
`either of the two test loads shall be limited to 4 rnA.
`When a driver, connected to the appropriate two test loads identified above, enters the idle state, it shall
`When a driver, connected to the appropriate two test loads identified above, enters the idle state, it shall
`maintain a minimum differential output voltage of at least 0.7 x V 2 m V for at least 2 bit times after the last
`maintain a minimum differential output voltage of at least 0.7 x V2 mV for at least 2 bit times after the last
`low to high transition. The driver differential output voltage shall then approach within 40 m V of 0 V
`low to high transition. The driver differential output voltage shall then approach within 40 m V of 0 V
`within 80 bit times. In addition, the current into the appropriate test load shall be limited in magnitude to
`within 80 bit times. In addition, the current into the appropriate test load shall be limited in magnitude to
`4 rnA within 80 bit times. Undershoot, if any, upon reaching 0 V shall be limited to -100 mV. See Fig 7-12.
`4 rnA within 80 bit times. Undershoot, if any, upon reaching 0 V shall be limited to -100 mY. See Fig 7-12.
`For drivers on either the CO or CI circuits, the first transition or the last positive going transition may
`For drivers on either the CO or CI circuits, the first transition or the last positive going transition may
`occur asynchronously with respect to the timing of the following transitions or the preceding transition(s),
`occur asynchronously with respect to the timing of the following transitions or the preceding transition(s),
`respectively.
`respectively.
`
`
`7.4.1.2 RequirementsMter Idle. When the driver becomes nonidle after a period of idle on the inter(cid:173)7.4.1.2 Requirements After Idle. When the driver becomes nonidle after a period of idle on the inter(cid:173)
`face circuit, the differential output voltage at the interface connector shall meet the requirements of 7.4 .1.1
`face circuit, the differential output voltage at the interface connector shall meet the requirements of 7.4.1.1
`beginning with the first bit transmitted. The first transition may occur asynchronously with respect to the
`beginning with the first bit transmitted. The first transition may occur asynchronously with respect to the
`timing of the following transitions.
`timing of the following transitions.
`
`
`7.4.1.3 AC Common-Mode Output Voltage. The magnitude of the ac component of the common(cid:173)7.4.1.3 AC Common-Mode Output Voltage. The magnitude of the ac component of the common(cid:173)
`mode output voltage of the driver, measured between the midpoint of a test load consisting of a pair of
`mode output voltage of the driver, measured between the midpoint of a test load consisting of a pair of
`matched 39 Q ± 1% resistors and circuit VC, as shown in Fig 7-13, shall not exceed 40 m V peak.
`matched 39 Q± 1% resistors and circuit VC, as shown in Fig 7-13, shall not exceed 40 mV peak.
`
`
`7.4.1.4 Differential Output Voltage, Open Circuit. The differential output voltage into an open cir(cid:173)7.4.1.4 Differential Output Voltage, Open Circuit. The differential output voltage into an open cir(cid:173)
`cuit, measured at the interface connector ofthe driving unit, shall not exceed 13 V peak.
`cuit, measured at the interface connector ofthe driving unit, shall not exceed 13 V peak.
`
`
`7.4.1.5 DC Common-Mode Output Voltage. The magnitude of the dc component of the common(cid:173)7.4.1.5 DC Common-Mode Output Voltage. The magnitude of the dc component of the common(cid:173)
`mode output voltage of the driver, measured between the midpoint of a test load consisting of a pair of
`mode output voltage of the driver, measured between the midpoint of a test load consisting of a pair of
`
`matched 39 n ± 1% resistors and circuit VC, as shown in Fig 7-13, shall not exceed 5.5 V. matched 39 n ± 1% resistors and circuit VC, as shown in Fig 7-13, shall not exceed 5.5 V.
`
`103
`103
`
`AMX
`Exhibit 1026-00103
`
`

`
`-
`-
`
`ISO/lEe 8802-3 : 1993
`ISO/lEe 8802-3 ; 1993
`ANSI/IEEE Stci Rn2~ . 1 !1!1~ Edition
`ANSTlTEEE Strl R02~ H19.1 Rrliti on
`
`I .OCAI . ANn MF.'T'HOrOI .ITA N AHl~A N R'T'WORl(<":: '
`T,OCAI.ANn MR1'HOr>Or ,ITAN Am~A NR1'WORl{C:; ·
`
`1315 mV---
`1315 mV-
`
`16 ns
`16 ns
`
`8 ns
`8 ns
`
`450mV-
`450mV-
`
`OmV - ~2W~ill&2L------------------------------~&&&&+&~~----
`
`OmV --- ~~~~~-------------------------------F~~~~~----
`
`BT
`BT
`
`OR
`OR
`BT/2
`BT/2
`(NOMINAL]
`(NOMINAL)
`
`1= 3.5 ns AT HO MHz DATA RATES
`t = 3.5 ns AT HO MHz DATA RATES
`V2 = 0 . 89 VI
`V2 = 0.89 V1
`V 3 = 0.82 V 2
`V 3 = 0.82 V 2
`
`RAND L VALUES PER 7.4.1.1
`A AND L VALUES PER 7.4.1.1
`~------------------------r-----.--~ +
`~--------------------------------.-----.----r +
`A
`A
`
`B
`B
`
`R
`R
`
`L
`L
`
`TEST LOAD
`
`NOTE: The lime I in Ihis figure refers to the rise time envelope. Jitter and duty cycle are specified elsewhere.
`NOTE: The time t in this figure refers to the rise time envelope. Jitter and duty cycle are specified elSewhere.
`
`Fig 7-11
`Fig 7-11
`Differential Output Voltage, Loaded
`Differential Output Voltage, Loaded
`
`7.4.1.6 Fault Tolerance. Any single driver in the interface, when idle or driving any permissible sig(cid:173)
`7.4.1.6 Fault Tolerance. Any single driver in the interface, when idle or driving any permissible sig(cid:173)
`nal, shall tolerate the application of each of the faults specified by the switch settings in Fig 7-14 indefi(cid:173)
`nal, shall tolerate the application of each of the faults specified by the switch settings in Fig 7-14 indefi(cid:173)
`nitely; and after the fault condition is removed, the operation of the drive)', according to the specifications of
`nitely; and after the fault condition is removed, the operation of the driver, according to the specifications of
`7.4.1.1 through 7.4.1.5, shall not be impaired.
`7.4.1.1 through 7.4.1.5, shall not be impaired.
`In addition, the magnitude of the output current from either output of the driver under any of the fault
`In addition, the magnitude of the output current from either output of the driver under any of the fault
`conditions specified shall not exceed 150 mAo
`conditions specified shall not exceed 150 mAo
`
`7.4.2 Receiver Characteristics. The receiver specified terminates the interface cable in its character(cid:173)
`7.4.2 Receiver Characteristics. The receiver specified terminates the interface cable in its character(cid:173)
`istic impedance. The receiver shall function normally over the specified dc and ac common-mode ranges.
`istic impedance. The receiver shall function normally over the specified dc and ac common-mode ranges .
`
`104
`104
`
`AMX
`Exhibit 1026-00104
`
`

`
`--
`
`CSMAlCD
`CSMAJCD
`
`lSOIIEC 8802-3 : 1993
`ISOIIEC 8802-3 : 1993
`ANSVIEEE Std 802.3. 1993 Edition
`ANSVIEEE Std 802.3. 1993 Edition
`
`o
`o
`
`-v dm
`-v dm
`
`
`T 1 -T 1 -
`
`T 2 T 2
`U
`U
`E
`E
`
`R
`R
`
`-
`-
`
`
`200 ns MINIMUM 200 ns MINIMUI.4
`
`80 BIT TIMES MAXIMUM 80 BIT TII.4ES MAXII.4UI.4
`-100 mV MAXIMUM UNDERSHOOT
`-100 mV MAXIMUM UNDERSHOOT
`STEADY STATE OFFSET INTO SPECIFIED TEST LOAD
`STEADY STATE OFFSET INTO SPECIFIED TEST LOAD
`
`+/- 40 mV MAX +/- 40 mV MAX
`+/-
`+/-
`4 mA I.4AX
`4 mA I.4AX
`RINGING SHALL BE < 200 mV PK-PK
`RINGING SHALL BE <200 mV PK-PK
`AFTER T 1 AND BEFORE T 2
`AFTER T 1 AND BEFORE T 2
`
`Fig 7·12
`Fig 7·12
`Generalized Driver Waveform
`Generalized Driver Waveform
`
`
`
`A A
`
`B
`B
`
`R1
`R1
`1--------. +
`1------.+
`
`R2
`R2
`
`
`
`vc vc
`
`R1 = R2 = 39 n ± 1%
`R1 = R2 = 39 n ± 1%
`
`Fig 7·13
`Fig 7·13
`Common·Mode Output Voltage
`Common·Mode Output Voltage
`
`105
`105
`
`AMX
`Exhibit 1026-00105
`
`

`
`I9Q1I\o:C 1!80'~ : 1993
`I90/I\o:C MO'~ : 1993
`ANS!nXII:E SI<l 1302.3, li1!13 Edit",.,
`ANSIIIEEE Std 13(12.3. IW3 Edition
`
`LOCALAND lIIETROPOLITAN AlU':A Nt.'l'WORKS:
`LOCALAND lIlETROPOLI1'AN Alt&>. Nl.'1'WORKS:
`
`-
`
`
`, ,
`
`- > , - » ,
`
`
`
`/ /
`
`
`
`VO VO
`
`
`, ,
`
`, ,
`
`" , " ,
`
`, ,
`
`, ,
`" , ,
`"
`
`
`FAULT
`FAULT
`CQNQITION
`CQNI2II1QN
`
`
`
`, , , , , , , , , , , ,
`
`SWiTC H SETTINGS
`SWlTCH SETTINGS
`
`, ,
`A LDlO 6
`A u:AD 6
`
`, ,
`
`, ,
`
`, ,
`
`, ,
`
`, ,
`
`, ,
`
`, ,
`
`
`CEAD , , CEA, , ,
`
`, ,
`
`, ,
`
`, ,
`
`, ,
`• ,
`
`, ,
`
`, ,
`
`• •
`'"
`t!-
`" VOLTS {
`" VOLTS {
`.or
`'T
`
`Fig7.1 ..
`Fig7.14
`Driver Fault ConditlolU
`Driver Fault Conditiona
`
`7.4.2.1 Receiver Threshold Level&. When the receiving interface cittUit at the interface connoctor of
`7 ... .2.1 Receiver Thre~hoid Level&. When the receiving interface """,uit at the interlace connector of
`the receiving equipment is driven by II differential input aignal at either BR or BM meeting the frequency
`the receiving equipment is driven by a differential input sigual at either BR or BM meeting the frequency
`and duty cycle tolorallC8ll .pecified for the receiving circuit, when the A lead ill 160 m V poo;itive with r.,.;pect
`and duty cycle tolerance • • pecified for the receiving circuit, when tho A lead i& 160 m V poo;itive with respect
`to the B lead, the interface circuit is in the HI state, and when the A lead j., 160 m V negative with ..... pert
`to the B lead, the interfa"e circuit is in the HI state, and when theAlcad;" 160 mV negative with rel!pect
`
`to the B lead, the interface circuit is in the LO state. 'The rooeiver output shall a •• um~ the intended HI and to the B lead, the interlace circuit ill in the LO stato. 'The l'<!<:eiver output Mall anume the intended HI and
`LO """tea for the corresponding input "onditiOlUl,
`LO s!alel! for the corresponding input conditio"",
`Ifthc receiver has a squelch feature, the Bpecified "",eive threshold level. apply only when the "'luelch i.
`If tho receivCT has a squelch feature, the apecified receive threshold level. apply only when the o.quelch i.
`allowing the signal to pasa through the receiver.
`aUowing the signal to pa"" through the receiver.
`
`NOTE: Tho opeciJied IIuahoId Iovelo do "'" ~ pnooo<\-.. .ur tho duty <yd • .00 jitter toler..",. • .,..,!!locl .lom.h_. Both .... 0(
`NO'J'E: '!'he opecilied Ihmohold !eve .. 00 "'" <aU ~ ..... tho doty ty<1o aDd jitter toler..",. opeoiliod .a....h-. Both .to 0(
`.poocilioou_ onuot bo """
`~o~t!"'"" "' .... bo "",t.
`
`7.4.2.2 AC Differential Input Impedance. The ac diffeNntiaI input impedance fOT AUI receivers
`7.4.2.2 AC Differential Input Impedance. The IlC differ't'ntial input impedance fOT AUI reoeiven!
`located in MAO. ohM! have a real part of77.83 0. ± 6%. with the sign of the imaginary part poo;itive. and IDC .. ted in MAUs oh!Ll! have a real part of77.B3 0. ± 6%. with the sign of the imaginary part po&itive. and
`
`
`the pha.e angle of the impedance in dcgreetlles. than or equal to 0,0338 times the real part of the imped(cid:173)the phaae angle of the impedance in degreellles. than or equ!Ll to 0.0338 times the re!Ll part oflhe imped(cid:173)
`ance, when measured with a 10 MHz Bine wove.
`ance, when me ... urOO with a 10 Mfu !ine wave.
`The ac differential input impedsnce for AUI r"""iv"". located in the mE .hall have a rcal part of
`The ac differential input impedance for AUI receiv ..... l""ated in the mE .hall have II real part of
`
`77.950. :1:6%, with the sign of the imaginary part pooitive, and the ph""" angle of the impedance in degrees 77.95 n :1:6%, with the sign of tile imaginary part poIIitive, and the ph""" angle of the impedance in degrees
`lesa than or equal to 0_0183 tim ... the real part of the impedance, when measured with 8 10 MHz sine
`les8 than or equal to 0.0183 tim ... the real part of the impedance, when me9.llurcd with 8 10 MHz Dine
`wave.
`wave.
`A 78 n:l: 6% resiBtor in parallel with an inductance of greater than 27j.L1l or 5O)IlI for receivers in the
`A 78 n:l: 6% resistor in parallel with an inductance of greater than 27 j.lll or 50 j.lll for reooeiveI'S in the
`MAU and DTE respe"tively, satisfi ... thi. requirement.
`MAU and DTE respectively, sstisfies Wo requirement.
`
`7.4.2.SAC Co mmon·Mode Range. When the receiving interface circuit at the receiving equipment ia
`7.4.2.SAC Common·Mode Range. When the receiving interflK!l! circuit Ilt the receiving equipment ia
`driven by a differentisl input .ignalat either BR or BRIll mooting the fr"'l.uency 'and duty cyde tolerances
`driven by a differentia! input signal at either BR or BRIll mooting the frequency 'and duty cyde tolerances
`specified for the circuit being driven, the receiver output .han aSSume the proper output otate WI .peci.fied
`specified fnr the cireuit being driven, tho receiver output . hall assume the prop"r output .tate "" specified
`in 7 .4.2.1, in the p"".ence ofa peak common_mode a" lrine wave voltage either .. from 30 Hz to 40 kHz ref(cid:173)
`in 7.".2.1, in the pre""nce ofa peat common_mode ac sine wave voltage either .. from 30 Hz t<> 40 kHz ref(cid:173)
`erenced to cireuit VC in magnitude from 0 to 3 V, M in magnitude 0 to 100 mV for a" voltage$ of from
`erenced to circuit VC in magnitude from 0 to 3 V, or in IIJlI8IIitude 0 to 100 mV for ac voltages of from
`40 kHz to BR aft shown in Fig 7-15.
`40 kHz to BR 9.lI shown in Fig 7-15.
`
`7.4.2.4 Total COllllllon-Mode Range. When the receiving interf""", circuit at the roceivingequipment
`7.4.2.4 Total Common-Mode Range, When the receiving interl""", circuit at tho roceivingequipment
`is driven by a differential input .ignal at either BR or ER/2 meeting the frequency and duty cycle toler_
`i8 driven by 8 differential input . ignal at ei1Mr BR or BR/2 meeting the frequency and duty cycle toler_
`ancc. sp""ified fM the crr"uit being driven, the receiver output .hall assume the intended output .tate ""
`MCC! specified for the crn,uit being driven, the receiver output ~h..u a""ume the intended output .tate ""
`specified in 7.4.2.1 in the P"<'gen"" nf a total common-mode voltage. de plus ac, referenced to oircuit VC in
`specified in 7." .2.1 in the ,,",!lence of a total common-lDod~ voltag(>, dc plus ac, referenced to circuit VC in
`magnitude from 0 to 5.5 V, ... !!hown in the te8t setup of Fig 7·15. The ac component shall nnt exceed the
`magnitude from 0 to 5.5 V, DB mown in the test setup of Fig 7.15. The ao component shall not exceed the
`roquirementft of 7 .4,2.3.
`rcquiremen~ of7.4.2.3.
`
`H<
`
`AMX
`Exhibit 1026-00106
`
`

`
`-
`-
`
`CSMAfCD
`CSMAJCD
`
`ISOIIEC 8802-3 : 1993
`TSOIIEC 8802-3 • 1993
`A N."TfTRRE StJ 802.3, 1993 Editicm
`A N.<:;TfTRRE Stu 802.3, 1993 Ed!t!a~
`
`A
`A
`
`Fig 7-15
`Fig 7-15
`Common-Mode Input Test
`Common-Mode Input Test
`
`The receiver shall be so designed that the magnitude of the current from the common-mode voltage
`The receiver shall be so designed that the magnitude of the current from the common-mode voltage
`source used in the test shall not exceed 1 mAo
`source used in the test shall not exceed 1 rnA.
`
`7.4.2.5 Idle Input Behavior. When the receiver becomes nonidle after a period of idle on the interface
`7.4.2.5 Idle Input Behavior. When the receiver becomes nonidle after a period of idle on the interface
`circuit, the characteristics of the signal at the output ofthe receiver shall stabilize within the startup delay
`circuit, the characteristics of the signal at the output of the receiver shall stabilize within the startup delay
`allowed for the device incorporating the receiver so that it is not prevented from meeting the jitter specifi(cid:173)
`allowed for the device incorporating the receiver so that it is not prevented from meeting the jitter specifi(cid:173)
`cations established for that device.
`cations established for that device.
`The receiving unit shall take precautions to ensure that a HI to idle transition is not falsely interpreted
`The receiving unit shall take precautions to ensure that a HI to idle transition is not falsely interpreted
`as an idle to nonidle transition, even in the presence of signal droop due to ac coupling in the interface
`as an idle to nonidle transition, even in the presence of signal droop due to ac coupling in the interface
`driver or receiver circuits.
`driver or receiver circuits.
`
`7.4.2.6 Fault Tolerance. Any single receiver in the interface shall tolerate the application of each of
`7.4.2.6 Fault Tolerance. Any single receiver in the interface shall tolerate the application of each of
`the faults specified by the switch settings in Fig 7-16 indefinitely, and after the fault condition is removed,
`the faults specified by the switch settings in Fig 7-16 indefinitely, and after the fault condition is removed,
`the operation of the receiver according to the specifications of 7.4.2.1 through 7.4.2.6 shall not be impaired.
`the operation of the receiver according to the specifications of 7.4.2.1 through 7.4.2.6 shall not be impaired.
`In addition, the magnitude of the current into either input of the receiver under any of the fault condi(cid:173)
`In addition, the magnitude of the current into either input of the receiver under any of the fault condi(cid:173)
`tions specified shall not exceed 3 rnA.
`tions specified shall not exceed 3 rnA.
`
`•
`•
`
`2
`2
`
`3
`3
`
`4
`4
`
`
`
`+ +
`
`16 VOLTS
`16 VOLTS
`
`•
`•
`
`2
`2
`
`3
`3
`
`4
`4
`
`A
`A
`
`B
`B
`
`VC
`VC
`
`FAULT
`FAULT
`CONDITION
`CONDITION
`
`,
`,
`
`2
`2
`3
`3
`4
`4
`5
`5
`6
`6
`
`7 7
`8
`8
`
`Fig 7-16
`Fig 7-16
`Receiver Fault Conditions
`Receiver Fault Conditions
`
`107
`107
`
`,
`
`,
`
`SWITCH SETIINGS
`SWITCH SETIINGS
`LEAD B
`LEAD B
`LEAD A
`LEAD A
`1
`1
`4
`4
`3
`3
`3
`3
`4
`4
`4
`4
`4
`4
`2
`2
`3
`3
`3
`3
`2
`2
`2
`2
`2
`2
`3
`3
`3
`3
`
`AMX
`Exhibit 1026-00107
`
`

`
`ISG'lEC ~!IIJZ,'I : 1_
`ISO'IEC !\!102-3 : 199.1
`ANBlIIEEE!;Itd M2.~, lW~ l!:dition
`ANBlIIEEE SId 802. ~, 19'.1~ l!:ditiolll
`
`LOCALAND J,(ETROPOI.I'TAN AREA NRTWORKS:
`LOCALAND J,(ETROPOI.I'TAN AREA NETWORKS:
`
`7.4.3 AlJI Cable Ch .... acteri.tics. The interface cable ronsim of individually ~hielded twisted pair. of
`7.4.3 AlJI Cable Ch .... acteri.tics. The interface cable con.im. of individually ~hielded twisted pair. of
`
`wire~ with a n ov .. rall shield cov .. ring the. e individunl ~hielded wire pairs. These shield. must provide . uf(cid:173)wire~ with a n overall shield covering these individual ~hielded wire pairs. Thase . hields must Pl'ovide . uf(cid:173)
`
`ficient shielding to meet the requirements of protection against rf interf .. rence and the fnUnwing cable ficient shielding to meet the requirements of Pl'otection against rf interference and the fnUnwing cable
`
`parameter~ . Individual . hiolds fnr each signal pair are electrically isolated from the outer shield but not parometer~ . Individual . hields fnr each . ignal pair are electrically isolated from the outer shield but not
`
`necessarily frnm each other. neces"arily frnm each other.
`The ovar.ll ~hield .hall be returned to the MAU and DTE Unim via theAUI connector shell a. defined in
`The overs ll ~hield shall be r .. turned to the MAU and DTE Uni!>; via theAU! connector shell a. defined in
`
`7.6.2 and 7.6.3. If a common drain wire i. u.oo for all the oignnl pair shields, then it shall be cnnnccted to 7.6.2 and 7.6.3. If. common drain wire i. used for all the ",gnal pair shield., then it shall be conIIDcted to
`pin 4. Individual drain wire retum~ fnr each ~ignal pair may be used (seo 7.6.3). It is reoommeuded that
`pin 4. Individual drRin wire returng fnr each signal pair may be used ( .... e 7.6.3). It i. :reoommeuded that
`
`individual drain wir .... be used nu a ll ooutrnl and data circuit .hields to meet "ati~fllCtooy crosstalk level •. If individual drain wir .... be used nn a ll control and data circuit shields to meet .... ti~factooy crosstalk levels. If
`individual drain wir"" are used, they.ha11 be interconnected within theAU! cable at each end and..hall be
`individual drain wires are used, they shall be interconnected within theAU! cable at each end and Mall be
`cnnnected at loa. t to pin 4 at each ... d of the cable.
`oonnected at loast to pin 4 at each RId of the cable.
`
`The presence nf the Control Out signal pair is optionnl. If driver or ",>coiver circuit components fnr CO The presence nf the Control Out signal pair is optional. If driver Or roceiver circuit components fnr CO
`arc not provided. con"idaration should be given to Pl'operly terminating the CO signal pair within the DTE
`arc not provided, consideration shnuld be given to properly terminating-the CO signal pair within the DTE
`and MAU to preclude erroneous operation.
`and MAU to precludo erroneous operation.
`
`
`7.4.3.1 Conductor Size. The de power pair in the interconnecting cable, voltage commnu and voltage 7.4.3.1 Conductor Size. The de power pair in the interconnecting cable, voltage commnn and voltage
`minus, "hall be composed of a twi8ted pair of Hufficient gauge au-anded wire~ to r06u1t in a nominal de minus, .hall be composed of a twisted pair ~ Hufficient gauge stl'anded wire. to rasult in .. nominal dc
`
`
`resistance uot to excood 1.7~ n per conductor. :resistance uot to excoorl 1.7~ n per conductor.
`Conductor size flU" the signal pairs shall be determined a<:coI"Wng to tho IlC related parameter! in 7.4.3.2-
`Conductor size fill" the sign.l pair. shall be ootcrmined acoordIDll: to the IlC related parameter" in 7.4.3.2-
`
`7.4.3.6. 7.4.3.6.
`
`7.4.3.2 Pair-tn_Pair BaJanced Crosstalk. The balanced croSlltalkfrom nne pair of wire. to any other
`7.4.3.2 Pair-tn_Pair BaJanced Crosstalk. The balanced cro •• talkfrom nne pair of wire. to any other
`
`pair in the .am .. cable sheath (when each pair is driven per 7.".1.1_7.".1.~) . hall have a minimum valuo of pair in the sarne cable she/lth (when each pair is driven per 7. ".1.1_7. ".1.~) shall have a minimum valuu of
`
`40 dB of attenuation me .... mred nver th .. range of BM to BR. 40 dB nf attenuation me ..... ured over the range of BM to BR.
`
`
`7.4.3.3 Diff ...... ntia] Characteristic Impedanoe. The differential characteristic impedance for all 7.4.3.3 DifferentlaJ Characteristic Impedance. The differential characteristic impedance for all
`
`. ignnl pairs shall be equal within 3 n and shall be 78 ± ~ n meMll:recl at a frequency of BR. signal pairs .hall be equal within 3 n and shall boo 78 ± ~ n me98Ured at II. frequency of BR.
`
`
`
`7.4.3.4 Transfer Impedanc .. 7.4.3.4 Transfer Impedance
`
`
`(1) The common-mnde tr9llS:f .... impedance shall not exceed the values shown in Fig 7"17 over the indi_ (1) The common-mnde trRIJSfar impedance MaIl not exceed the values "hown in Fig 7"17 over the indi_
`
`cated frequency range. cated frequency rani:<'.
`
`(2) The diff .. rential mod .. u-ansfer impedance fnr all pairs ~hall be at least 20 dB belnw the cOIIlmon(cid:173)(2) The differential mode tl'ansf"er impedance fnr all pairs shall be .. t least 20 dB belnw the common(cid:173)
`mode transfer impedance.
`mnde tran"for impedance.
`
`7.4.3.5Attenuation. 'ThtaJ cable ~ttenuation level!! betw .... n driver RIKI receiver (at .... parate station.)
`7.4.3.5Attenuation. Thtal cable ~ttenuatiOIllevell! betw .... n driv .. r and receiver (at ""parate stations)
`
`for each signal pair shllli not exceed 3 dB nver the frequency range ofBR12 to BR (Hz) fur ~inewave mea(cid:173)for each signal pair shall not exc .... d 3 dB mer the frequency range ofBR12 to BR (Hz) for sinewave mea(cid:173)
`
`.urements. su:rementll.
`
`
`7.4.3.6 Timing Jitter. Cable mootingthi.o! ~pecificatim shall exhibit edgejitt..r of no more than 1.5 ns 7.4.3.6 Timing Jitter. Cable mootingthi.o! ~pecification.ball exhibit oogejitter of no more than 1.5 os
`.. t the receiving end when the longest legal length of the oable "" spccifiod in 7.4.3.1 thr<>u!l:h 7.4.3.7 ;,. rer(cid:173)
`at the "'cciving .. nd when the longest legal length of the oable as spccifioo in 7.4.3.1 thmugh 7.4.3.7 u; rer(cid:173)
`
`minated in a 78 n± 1% resi. tor at thereceiving end and i. driven with p.eudnranclom Mancheater encoded minated in a 78 n± 1% ",,,;ster at thereoeiving end and is driven with p.eudnrandom Mancheater encoded
`
`binary data from a data gen .. rator which eIhlbitl! no m .... than O.~ ru; of edge jitter on half bit cells of binary data from a dat .. generatnr which cIhibits no m,..., than O . ~ ru; of edge Jitrer on half bit ceIls of
`
`exacily 112 BT and whose output meets the specification. of 7 .".1.1 through 7.4:1.I'i. This te. t shall be COll(cid:173)exacily 112 BT and whose output meets the specificlltions of7.".I.1 through 7.4:1.I'i. This te. t "hall be con(cid:173)
`
`ducted in a noise-free ... vironment. '!he above specified component is not ro introdure mnre than 1 n. of ducted in a noise_free anvironment. '!he above specified component is not ttl introduce mnre than 1 n. of
`
`edge jittet' into the "Y8tem. edge jittet' Into the "Y8tem.
`
`
`7 .... :'1.7 Delay. Thml signal delay between driver and receiver(at separate statinns):for .. ach signal pair 7 .... 3.7 Delay. Thtal signal delay between driver Rlld receiver(at oeparate .tatinns):ro.- each signal pair
`
`:.hall not .. xceed 257 n8. sh.ll not exceed 257 ns.
`
`
`
`7.5 Functional Description ofInterchange CircuitIJ 7.5 Functional De""ription ofInterchange Circuit..
`
`7.~.1 General. The AU! consist. of either three Ill" fnur differmtial signal cireuito, power, and ground .
`7./t1 Gen .. raJ. The AU! ron"i. !>! of either three or fnu? differential signal circuit., pnwer, andgrnuncl.
`Two of the circuits carry encoded data and two carry encoded control information. Circuit. DO ro .. t .. Out)
`Two of the circuits carry .. ncoded data and two carry encoded control information. Circuits DO mata Out)
`and CO (Control Out) are sourced by the DTE, and circuit. or (Data In) and CI (Control In) are snurced by
`and CO (Control Out) are sourced by the DTE, and circuit. DI (D .. ta In) and CI (Control In) are lllIuroud by
`
`'"
`
`AMX
`Exhibit 1026-00108
`
`

`
`---
`---
`
`ISOI1EC 8802-3 . ] 993
`ISOfTEC 8802-3 . ] 993
`A N~ TfTRI<', I<', ~trl An ? "l 1 QQ"l I<'rlitinn
`A N~TfTRli'. li'. ~td Rn ? "l
`, QQ"l li'ditinn
`- ---, ---- ~----~--
`- -._) ---~ - ~ --- ~ - -
`. ~
`. ~
`
`100
`100
`
`E d 10
`E d 10
`
`E
`E
`
`I
`I
`
`I
`I
`
`I\, ,
`I\, ,
`
`L
`/
`I
`I
`
`1
`1
`10K
`10K
`
`lOOK
`lOOK
`
`1M
`1M
`
`10M
`10M
`
`100M
`100M
`
`FREQUENCY (Hz)
`FREQUENCY (Hz)
`
`Fig 7-17
`Fig 7-17
`Common-Mode Transfer Impedance
`Common-Mode Transfer Impedance
`
`the MAD. The interface also provides for power transfer from the DTE to the MAD. The CO circuit is
`the MAD. The interface also provides for power transfer from the DTE to the MAD. The CO circuit is
`optional.
`optional.
`
`7.5.2 Definition of Interchange Circuits. The following circuits are defined by this specification:
`7.5.2 Definition of Interchange Circuits. The following circuits are defined by this specification:
`
`Circuit Name
`Circuit Name
`
`Signal Direction
`Signal Direction
`
`to MAD
`to MAD
`
`from
`from
`MAD
`MAD
`
`DO
`DO
`
`DI
`DI
`
`CO
`CO
`
`CI
`CI
`
`VP
`VP
`
`VC
`VC
`
`PG
`PG
`
`Data Out
`Data Out
`
`Data In
`Data In
`
`Control Out
`Control Out
`
`Control In
`Control In
`
`Voltage Plus
`Voltage Plus
`
`Voltage Common
`Voltage Common
`
`Protective Ground
`Protective Ground
`
`X
`X
`
`X
`X
`
`X
`X
`
`X
`X
`
`X
`X
`
`X
`X
`
`X
`X
`
`Remarks
`Remarks
`
`Encoded Data
`Encoded Data
`
`Encoded Data
`Encoded Data
`
`Encoded Control
`Encoded Control
`
`Encoded Control
`Encoded Control
`
`12 Volts
`12 Volts
`
`Return for VP
`Return for VP
`
`Shield
`Shield
`
`7.5.2.1 Circuit DO-Data Out. The Data Out (DO) circuit is sourced by the DTE. It is a differential
`7.5.2.1 Circuit DO-Data Out. The Data Out (DO) circuit is sourced by the DTE. It is a differential
`pair consisting of DO-A (Data Out circuit A) and DO-B (Data Out circuit B).
`pair consisting of DO-A (Data Out circuit A) and DO-B (Data Out circuit B).
`The signal transferred over this circuit is Manchester encoded. An output message containing a one bit is
`The signal transferred over this circuit is Manchester encoded. An output message containing a one bit is
`encoded