UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
`
`Petitioner
`
`v.
`
`AU OPTRONICS CORPORATION
`
`Patent Owner
`
`
`
`Patent No. 6,689,629 C1
`Issued: November 14, 2014
`Filed: March 16, 2010
`
`Inventors: Takatoshi TSUJIMURA et al.
`
`Title: ARRAY SUBSTRATE FOR DISPLAY, METHOD OF
`MANUFACTURING ARRAY SUBSTRATE FOR DISPLAY AND DISPLAY
`DEVICE USING THE ARRAY SUBSTRATE
`
`
`
`Inter Partes Review No.: Unassigned
`
`
`
`PETITION FOR INTER PARTES REVIEW
`
`
`
`
`
`

`
`Petition for Inter Partes Review
`U.S. Patent No. 6,689,629 C1
`
`TABLE OF CONTENTS
`
`V. 
`
`INTRODUCTION ........................................................................................... 1 
`I. 
`II.  MANDATORY NOTICES UNDER 37 C.F.R. § 42.8(a)(1) .......................... 1 
`A. 
`Real Party-in-Interest Under 37 C.F.R. § 42.8(b)(1) ............................ 1 
`B. 
`Related Matters Under 37 C.F.R. § 42.8(b)(2) ..................................... 1 
`C. 
`Lead and Back-Up Counsel ................................................................... 2 
`D. 
`Service Information ............................................................................... 2 
`PAYMENT OF FEES UNDER 37 C.F.R. § 42.013 ....................................... 2 
`III. 
`IV.  REQUIREMENTS FOR IPR UNDER 37 C.F.R. §§ 42.104 .......................... 2 
`A.  Grounds for Standing Under 37 C.F.R. § 42.104(a) ............................. 2 
`B. 
`Priority Date and Prior Art Patents ....................................................... 3 
`C. 
`Identification of Challenge Under 37 C.F.R. § 42.104(b) and Relief
`Requested .............................................................................................. 4 
`SUMMARY OF THE '629 PATENT.............................................................. 5 
`A. 
`Brief Description of the '629 Patent ...................................................... 5 
`B. 
`Summary of the Prosecution History of the '629 Patent ....................... 6 
`VI.  CLAIM CONSTRUCTION ............................................................................ 8 
`VII.  THERE IS A REASONABLE LIKELIHOOD THAT AT LEAST ONE
`CLAIM OF THE '629 PATENT IS UNPATENTABLE. ............................. 10 
`A.  Ground 1: Claims 1, 3, 5-6, 9, 11, 14, and 17 are obvious under
`35 U.S.C. § 103 in view of Noda, AAPA, Tsujimura, Ichioka, and
`Shimizu. ............................................................................................... 10 
`Ground 2: Claims 7-8 and 15-16 are obvious under 35 U.S.C. § 103
`in view of Noda, AAPA, Tsujimura, Ichioka, Shimizu, and Wicke. .. 29 
`C.  Ground 3: Claims 1, 9, and 17 are obvious under 35 U.S.C. § 103
`under Noda, AAPA, Tsujimura, Ichioka, and Ono. ............................ 32 
`D.  Grounds 1-3 are non-cumulative. ........................................................ 38 
`VIII.  CONCLUSION .............................................................................................. 39 
`
`
`B. 
`
`
`
`i
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`

`
`Petition for Inter Partes Review
`U.S. Patent No. 6,689,629 C1
`
`EXHIBITS
`
`1006
`
`1007
`1008
`
`Exhibit Description
`1001
`U.S. Patent No. 6,689,629 C1 ("the '629 Patent")
`1002
`File History of U.S. Patent No. 6,689,629 C1
`1003
`U.S. Patent No. 6,689,629 B2
`1004
`File History of U.S. Patent No. 6,689,629 B2
`1005
`Certified English Translation of Japanese Publication No. P2000-
`98909A (“Noda”)
`Low Resistance Gate Line for High-Resolution TFT/LCD Display
`("Tsujimura")
`U.S. Patent No. 5,546,013 ("Ichioka")
`Certified English Translation of Japanese Publication No. HEI 2-
`189922 ("Shimizu")
`U.S. Patent No. 2,990,282 ("Wicke")
`Certified English Translation of Japanese Publication No. SHO 63-
`181355 ("Ono")
`Declaration of Prof. Yue Kuo, Dr.Eng.Sci.
`Power of Attorney
`Japanese Application No. 2001-029587 ("the '587 Application")
`Japanese Publication No. P2000-98909A
`Japanese Publication No. HEI 2-189922
`Japanese Publication No. SHO 63-181355
`
`1009
`1010
`
`1011
`1012
`1013
`1014
`1015
`1016
`
`
`
`
`
`ii
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`

`
`Petition for Inter Partes Review
`U.S. Patent No. 6,689,629 C1
`I.
`
`INTRODUCTION
`
`Pursuant to 35 U.S.C. §§ 311-319 and 37 C.F.R. § 42, Petitioner Shenzhen
`
`China Star Optoeletronics Technology Co., Ltd. (“CSOT” or “Petitioner”)
`
`respectfully requests Inter Partes Review ("IPR") of claims 1, 3, 5-9, 11, and 14-
`
`17 of U.S. Patent 6,689,629 C1 (Ex. 1001, “the ’629 Patent”), which was filed on
`
`March 16, 2010, issued on November 14, 2014, and is currently assigned to AU
`
`Optronics Corporation (“AUO”) according to the U.S. Patent and Trademark
`
`Office ("USPTO") assignment records. There is a reasonable likelihood that
`
`Petitioner will prevail with respect to at least one of the claims challenged in this
`
`Petition.
`
`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8(A)(1)
`
`A. Real Party-in-Interest Under 37 C.F.R. § 42.8(b)(1)
`
`Petitioner is Shenzhen China Star Optoeletronics Technology Co., Ltd., and
`
`is the only real party in interest.
`
`B. Related Matters Under 37 C.F.R. § 42.8(b)(2)
`
`Pursuant to 37 C.F.R. § 42.8(b)(2), Petitioner states that the ’629 Patent is
`
`the subject of the following patent infringement arbitration by the assignee, AUO,
`
`which may affect, or be affected by, a decision in this proceeding: AUO v. TCL
`
`Multimedia Technology Holdings Limited, TCL Corp., and Shenzhen China Star
`
`
`
`1
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`

`
`Petition for Inter Partes Review
`U.S. Patent No. 6,689,629 C1
`
`Optoelectronics Technology Co., Ltd, filed in the Hong Kong International
`
`Arbitration Centre on September 22, 2015.
`
`Petitioner has requested IPR of U.S. Patent No. 7,652,285 B2, which is not
`
`related to the '629 Patent. Each of the patents for which Petitioner seeks IPR has
`
`been asserted against Petitioner in the above arbitration.
`
`C. Lead and Back-Up Counsel
`
`Lead counsel for Petitioner is William H. Mandir, Registration No. 32,156,
`
`and back-up counsel is John F. Rabena, Registration No. 38,584, both of Sughrue
`
`Mion, PLLC. Pursuant to 37 C.F.R. § 42.10(b), a Power of Attorney accompanies
`
`this Petition.
`
`D.
`
`Service Information
`
`Service information for lead and back-up counsel is provided in the
`
`signature block below. Petitioner consents to electronic service.
`
`III. PAYMENT OF FEES UNDER 37 C.F.R. § 42.013
`
`Petitioner authorizes the USPTO to charge Deposit Account 19-4880 for the
`
`fees set forth in 37 C.F.R. § 42.15(a) for this Petition for IPR and further authorizes
`
`payment for any additional fees to be charged to this Deposit Account.
`
`IV. REQUIREMENTS FOR IPR UNDER 37 C.F.R. §§ 42.104
`
`A. Grounds for Standing Under 37 C.F.R. § 42.104(a)
`
`
`
`2
`
`

`
`Petition for Inter Partes Review
`U.S. Patent No. 6,689,629 C1
`
`Petitioner certifies that the '629 Patent is available for IPR and that Petitioner
`
`is not barred or estopped from requesting IPR.
`
`B.
`
`Priority Date and Prior Art Patents
`
`The claims of the '629 Patent have an effective filing date no earlier than
`
`February 6, 2001, the filing date of the Japanese Application No. 2001-029587
`
`(Ex. 1013, "the '587 Application") to which the applicants claimed priority.
`
`Petitioner reserves the right to challenge this claim of priority in related litigation.
`
`Petitioner relies upon the following patents and publications, all of which are prior
`
`art to all claims of the '629 Patent:
`
`Art available as prior art under 35 U.S.C. § 102(a):
`
`Ex. 1005 – Japanese Publication No. P2000-98909A (“Noda”) published on
`
`April 7, 2000.
`
`Art available as prior art under 35 U.S.C. § 102(b):
`
`Ex. 1006 – Low Resistance Gate Line for High-Resolution TFT/LCD
`
`Display ("Tsujimura") published on October 10-13, 1994.
`
`Ex. 1007 - U.S. Patent No. 5,546,013 ("Ichioka") published on August 13,
`
`1996.
`
`Ex. 1008 - Japanese Publication No. HEI 2-189922 ("Shimizu") published
`
`on July 25, 1990.
`
`Ex. 1009 - U.S. Patent No. 2,990,282 ("Wicke") published on June 27, 1961.
`
`
`
`3
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`

`
`Petition for Inter Partes Review
`U.S. Patent No. 6,689,629 C1
`
`Ex. 1010 - Japanese Publication No. SHO 63-181355 ("Ono") t published on
`
`July 26, 1988.
`
`C.
`
`Identification of Challenge Under 37 C.F.R. § 42.104(b) and Relief
`
`Requested
`
`Petitioner requests IPR of claims 1, 3, 5-9, 11, and 14-17 of the '629 Patent
`
`on the grounds set forth in the table and claim charts below and requests that each
`
`of the claims be found unpatentable. Additional explanation and support for each
`
`ground of rejection is set forth in the Declaration of Yue Kuo, Dr.Eng.Sci (Ex.
`
`1011).
`
`Ground '629 Patent Claims
`
`Basis for Rejection:
`
`1
`
`1, 3, 5-6, 9, 11, 14, and
`
`Obviousness: Noda, Applicants' Admitted
`
`17
`
`Prior Art (AAPA), Tsujimura, Ichioka, and
`
`Shimizu
`
`2
`
`3
`
`7-8 and 15-16
`
`Obviousness: Noda, AAPA, Tsujimura,
`
`Ichioka, Shimizu, and Wicke
`
`1, 9, and 17
`
`Obviousness: Noda, AAPA, Tsujimura,
`
`Ichioka, and Ono
`
`
`
`4
`
`

`
`Petition for Inter Partes Review
`U.S. Patent No. 6,689,629 C1
`V.
`
`SUMMARY OF THE '629 PATENT
`
`A. Brief Description of the '629 Patent
`
`The '629 Patent is directed to a thin film transistor (TFT) array layout for a
`
`display and a method for forming the same. The '629 Patent focuses on the use of
`
`larger dummy conductive patterns 29 between connection pads 25 and 27.
`
`In FIGS. 2 and 5C of the '629 Patent, below, an array substrate includes an
`
`insulating substrate 1 (pink), a TFT array (TFTs 21) on the insulating substrate 1,
`
`and a plurality of wirings 2 (grey) (scan lines 23 and signal lines 24) on the
`
`insulating substrate 1, each wiring 2 having a first end, each wiring 2 in
`
`communication with at least one transistor (the TFT 21) in the thin film array, and
`
`at least one of the wirings 2 having an upper layer and a lower layer of conductive
`
`materials. See Ex. 1003 at FIGS. 2 and 5A-5C, 4:42-67, 5:1-10, 6:17-55.
`
`FIG. 5
`
`
`
`
`
`5
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`

`
`Petition for Inter Partes Review
`U.S. Patent No. 6,689,629 C1
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`The array substrate further includes a plurality of connection pads 25 and 27
`
`(blue), each connection pad 25 or 27 contacting a first end of at most one of the
`
`plurality of wirings 2. The array substrate further includes a plurality of pixel
`
`electrodes 22 (green) and a plurality of dummy conductive patterns 29 (red) on the
`
`insulating substrate 1, the plurality of dummy conductive patterns 29 including at
`
`least about 30% of an area of the insulating substrate 1 between the connection
`
`pads 25 and 27 and the pixel electrodes 22, and the dummy conductive patterns 29
`
`being not in contact with any of the wirings 2. See Ex. 1003 at FIGS. 2 and 5A-
`
`5C, 4:42-67, 5:1-10, 5:29-42, 6:17-55.
`
`According to the '629 Patent, the dummy conductive patterns 29 have a
`
`wiring density of at least 30%. See Ex. 1003 at 6:7-13, 5:55-67, 6:1-6. By keeping
`
`the wiring density of the dummy conductive patterns 29 above 30%, the effect of
`
`"undercutting" during etching can be reduced, and a gentler taper of the wiring 2
`
`can be formed. See Ex. 1003 at 5: 29-42, 7:8-18, FIG. 8.
`
`Dependent claims include additional limitations. For example, claims 3 and
`
`11 specify that the lower layer wiring material is selected from the group
`
`consisting of aluminum and aluminum alloys.
`
`B.
`
`Summary of the Prosecution History of the '629 Patent
`
`The '629 Patent issued on November 14, 2014, from Reexamination Request
`
`No. 90/009,697 ("the '697 Reexamination") filed on March 16, 2010. The original
`
`
`
`6
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`

`
`Petition for Inter Partes Review
`U.S. Patent No. 6,689,629 C1
`
`U.S. Application No. 10/068,500 ("the '500 Application") was filed on February 5,
`
`2002, which issued as U.S. Patent No. 6,689,629 B2 on February 10, 2004, which
`
`claimed priority from the '587 Application filed February 6, 2001. Ex. 1001-1004.
`
`In the '500 Application, an Office Action dated May 29, 2003, was issued,
`
`based on U.S. Patent No. 5,285,301 and U.S. Patent No. 6,163,356. Ex. 1004.117-
`
`122. An Amendment was filed on August 29, 2003, in response to the Non-Final
`
`Office Action, in which the subject matter of claim 2 was incorporated into claim
`
`1, i.e., the feature “the dummy patterns comprises at least about 30% of the area of
`
`the insulating substrate." Ex. 1004.123-130. A Notice of Allowance dated Oct. 1,
`
`2003, was issued. Ex. 1004.131-135.
`
`The '629 Patent was assigned from IBM to AUO on December 29, 2009.
`
`In the '697 Reexamination, a Non-Final Office Action dated January 6,
`
`2011, was issued, in which EP Publication No. 0 887 695 and U.S. Patent No.
`
`5,995,189 ("the '189 Patent") are cited as main references and the AAPA in the
`
`'629 Patent is cited as a secondary reference. Ex. 1002.1096-1007.
`
`A Supplemental Amendment was filed on May 18, 2011, in response to the
`
`Non-Final Office Action in which the subject matter of claims 2 and 4 was
`
`incorporated into claim 1, i.e., the feature "at least one of the wirings comprises at
`
`least an upper layer and a lower layer of conductive materials, wherein the upper
`
`layer wiring material is selected from the group consisting of molybdenum,
`
`
`
`7
`
`

`
`Petition for Inter Partes Review
`U.S. Patent No. 6,689,629 C1
`
`chromium, tantalum, titanium and alloys thereof." Ex. 1002.1278-1306. A Final
`
`Office Action dated June 6, 2012, was issued, in which the '189 Patent is cited as
`
`the main reference and the AAPA in the '629 Patent is cited as a secondary
`
`reference. Ex. 1002.1580-1495. A Supplemental Amendment was filed on
`
`September 19, 2012, in response to the Final Office Action, in which the claims
`
`were amended as issued in the '629 Patent. Ex. 1002.1632-1641. A Notice of
`
`Intent to Issue a Reexam Certificate dated September 26, 2014, was issued. Ex.
`
`1002.1866-1872.
`
`VI. CLAIM CONSTRUCTION
`
`A claim subject to IPR is given its “broadest reasonable construction in light
`
`of the specification of the patent in which it appears.” 37 C.F.R. § 42.100(b). As
`
`such, the words of the claim are given their plain meaning from the perspective of
`
`one of ordinary skill in the art unless that meaning is inconsistent with the
`
`specification. In re Zletz, 893 F.2d 319, 321 (Fed. Cir. 1989).
`
`Petitioner submits that a person of ordinary skill in the art (“POSITA”) of
`
`the '629 Patent would have had, as of February 2001, at least a bachelor's degree in
`
`electrical engineering, physics, chemical engineering, material science or
`
`engineering, or equivalent coursework, and at least two years of experience in
`
`transistor design, fabrication, or analysis.
`
`Petitioner submits that the following terms may need to be construed in
`
`
`
`8
`
`

`
`Petition for Inter Partes Review
`U.S. Patent No. 6,689,629 C1
`connection with this IPR.1
`
`A.
`
`"a plurality of dummy conductive patterns on the insulating
`substrate" (claims 1, 9, and 17)
`
`The broadest reasonable construction of this feature, which is found in
`
`independent claims 1, 9, and 17 of the '629 Patent, is "conductive material disposed
`
`on an insulating substrate and not contacting any wirings." See Ex. 1003 at FIGS.
`
`2 and 5A-5C, 5:29-42, 6:17-55.
`
`B.
`
`"wherein the plurality of dummy conductive patterns comprises
`at least about 30% of an area of the insulating substrate between
`the connection pads and the pixel electrodes" (claims 1, 9, and 17)
`
`The broadest reasonable construction of this feature, which is found in
`
`independent claims 1, 9, and 17 of the '629 Patent, is that "the area covered by the
`
`dummy conductive patterns covers 30% or more of a region between the
`
`connection pads and pixel electrodes." For example, the '629 Patent refers to this
`
`concept as the "wiring density" and states that "the term 'wiring density' refers to
`
`an area ratio of an area of portions where the signal lines, the scan lines, the
`
`drawing lines, and the dummy conductive patterns are formed [to] an area of a
`
`
`1 Because, for instance, a different legal standard applies to claim construction
`
`in IPR proceedings than in district court litigation, Petitioner reserves the right to
`
`raise different constructions in any district court or other proceeding between
`
`CSOT and AUO, including to assert that additional terms merit construction.
`
`
`
`9
`
`

`
`Petition for Inter Partes Review
`U.S. Patent No. 6,689,629 C1
`
`specific region where the dummy conductive patterns are formed." Ex. 1003 at
`
`5:55-67, 6:1-6.
`
`VII. THERE IS A REASONABLE LIKELIHOOD THAT AT LEAST ONE
`
`CLAIM OF THE '629 PATENT IS UNPATENTABLE.
`
`A. Ground 1: Claims 1, 3, 5-6, 9, 11, 14, and 17 are obvious under
`
`35 U.S.C. § 103 in view of Noda, AAPA, Tsujimura, Ichioka, and
`
`Shimizu.
`
`The combination of Noda, the AAPA, Tsujimura, Ichioka, and Shimizu
`
`disclosed all of the features of claims 1, 3, 5-6, 9, 11, 14, and 17, namely, the
`
`features of independent claim 1, which recites:
`
`An array substrate for display, comprising:
`an insulating substrate;
`a thin film transistor array on the insulating
`substrate;
`a plurality of wirings on the insulating substrate,
`each wiring having a first end, each wiring in
`communication with at least one transistor in the thin
`film array, and at least one of the wirings comprising at
`least an upper layer and a lower layer of conductive
`materials, wherein the upper layer wiring material is
`selected from the group consisting of molybdenum,
`chromium, tantalum, titanium and alloys thereof;
`a plurality of connections pads, each connection
`
`
`
`10
`
`

`
`Petition for Inter Partes Review
`U.S. Patent No. 6,689,629 C1
`
`pad contacting the first end of at most one of the plurality
`of wirings;
`a plurality of pixel electrodes; and
`a plurality of dummy conductive patterns on the
`insulating substrate, wherein the plurality of dummy
`conductive patterns comprises at least about 30% of an
`area of the insulating substrate between the connection
`pads and the pixel electrodes, and the dummy conductive
`patterns are not in contact with any of the wirings.
`
`Noda is directed to a solid device such as a polysilicon-typed TFT mode
`
`active matrix liquid crystal device (see Ex. 1005 at ¶¶ [0001]-[0002]), which is an
`
`array substrate as in the display of the '629 Patent. Noda expressly disclosed most
`
`of the features of the 12 claims of the '629 Patent. In addition to the features
`
`squarely disclosed by Noda, other features would have been obvious in view of the
`
`AAPA, Tsujimura, Ichioka, and Shimizu. Ex. 1011 at ¶ 46.
`
`1.
`
`Noda disclosed an insulating substrate, a thin film transistor array, and
`
`a plurality of pixel electrodes.
`
`Independent claims 1, 9, and 17 include "an insulating substrate," "a thin
`
`film transistor array on the insulating substrate," and "a plurality of pixel
`
`electrodes." Noda disclosed these features. Ex. 1011 at ¶ 47.
`
`Referring to FIG. 5 reproduced below, Noda disclosed that (emphasis added)
`
`"[p]ixel electrodes [12] [green] formed by ITO are provided in a matrix shape on
`
`
`
`11
`
`

`
`Petition for Inter Partes Review
`U.S. Patent No. 6,689,629 C1
`
`a transparent insulating substrate of a TFT array side substrate 11 which
`
`constitutes a polysilicon-typed TFT active-matrix liquid crystal display." Ex. 1005
`
`at Abstract, FIG. 5. Thus, Noda disclosed the claimed insulating substrate, thin
`
`film transistor array, and plurality of pixel electrodes. Ex. 1011 at ¶ 48.
`
`FIG. 5
`
`
`
`2.
`
`Noda disclosed a plurality of dummy conductive patterns.
`
`Independent claims 1, 9, and 17 include "a plurality of dummy conductive
`
`patterns on the insulating substrate, wherein … the dummy conductive patterns are
`
`not in contact with any of the wirings." Noda disclosed these features. Ex. 1011 at
`
`¶ 49.
`
`Referring again to FIG. 5 reproduced above, Noda disclosed (emphasis
`
`added):
`
`[I]t may be a shape that surrounds the periphery of
`the pixel electrode 12 as a set of the dummy films 5a
`[red] having a shape cut corresponding to the shape of
`
`
`
`12
`
`

`
`Petition for Inter Partes Review
`U.S. Patent No. 6,689,629 C1
`
`the pixel electrodes 12. The dummy films are provided
`to the same substrate end side with the pixel electrodes
`12 on the transparent insulating substrate 11a so as to
`surround the periphery of the pixel electrodes 12 … .
`Further, the dummy film 5 … may be formed of other
`materials such as Al (aluminum), Cr (chromium) and
`the like.
`
`Ex. 1005 at ¶¶ [0032]-[0033], FIG. 5. One of ordinary skill in the art would
`
`recognize that aluminum and chromium are conductive. Also, as shown in FIG. 5,
`
`the dummy films 5a are not in contact with any of the wirings, i.e., drain wires DL
`
`and gate lines GL. Thus, Noda disclosed the claimed plurality of dummy
`
`conductive patterns. Ex. 1011 at ¶ 50.
`
`3.
`
`The combination of Noda, the AAPA, and Tsujimura disclosed a
`
`plurality of wirings.
`
`Independent claims 1, 9, and 17 include "a plurality of wirings on the
`
`insulating substrate, each wiring having a first end, each wiring in communication
`
`with at least one transistor in the thin film array, and at least one of the wirings
`
`comprising at least an upper layer and a lower layer of conductive materials,
`
`wherein the upper layer wiring material is selected from the group consisting of
`
`molybdenum, chromium, tantalum, titanium and alloys thereof." The combination
`
`of Noda, the AAPA, and Tsujimura disclosed these features. Ex. 1011 at ¶ 51.
`
`Referring again to FIG. 5, Noda disclosed that (emphasis added) "[i]n the
`
`TFT array side substrate 11 … the pixel electrode 12 of each of the display
`
`
`
`13
`
`

`
`Petition for Inter Partes Review
`U.S. Patent No. 6,689,629 C1
`
`pixels constituting the liquid crystal display is pattern-formed in the vicinity of the
`
`intersection points of the drain wires DL connected to the drain driver and the
`
`gate lines GL connected to the gate driver." Ex. 1005 at ¶ [0024], FIG. 5. Also,
`
`as shown in FIG. 5, the drain wires DL and the gate lines GL are connected to
`
`TFTs of the TFT array side substrate 11 via contact holes 13. See Ex. 1005 at ¶
`
`[0025], FIG. 5. Thus, Noda disclosed the claimed plurality of wirings on the
`
`insulating substrate, each wiring having a first end (connected to the drain driver or
`
`the gate driver), and each wiring in communication with at least one transistor in
`
`the thin film array. Ex. 1011 at ¶ 52.
`
`The AAPA disclosed that it was well-known to employ "wiring using
`
`aluminum is constituted as a two-layer structure, in which aluminum is used as
`
`a lower conductive material, and a material harder to be oxidized than aluminum
`
`such as chromium, tantalum, titanium or molybdenum is used as an upper
`
`conductive material." Ex. 1003 at 1:33-38, 2:1-6. Thus, the AAPA disclosed at
`
`least one of the claimed wirings comprising at least the upper layer and the lower
`
`layer of conductive materials, wherein the upper layer wiring material is selected
`
`from the group consisting of molybdenum, chromium, tantalum, titanium and
`
`alloys thereof. Id.; see also Ex. 1011 at ¶ 53.
`
`Consistent with the AAPA, Tsujimura also disclosed that it was well-known
`
`to employ the claimed two-layer structure of wirings: "Fig.1 shows the cross
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`section of our gate line structure. As Al makes hillocks or blisters at high
`
`temperature, we must make a multi-layer structure using high-melting point
`
`metal Mo … on Al." Ex. 1006 at page 424, column 1, last paragraph, page 424,
`
`column 2, first paragraph (emphasis added), FIG. 1. Thus, Tsujimura also
`
`disclosed at least one of the claimed wirings comprising at least the upper layer
`
`and the lower layer of conductive materials, wherein the upper layer wiring
`
`material is selected from the group consisting of molybdenum, chromium,
`
`tantalum, titanium and alloys thereof. Ex. 1011 at ¶ 54.
`
`4.
`
`Ichioka disclosed a plurality of connection pads.
`
`Independent claims 1, 9, and 17 include "a plurality of connections pads,
`
`each connection pad contacting the first end of at most one of the plurality of
`
`wirings." Ichioka disclosed that these connection pads were also well-known. Ex.
`
`1011 at ¶ 55.
`
`While one of ordinary skill in the art would recognize that the drivers of
`
`Noda must include connection pads to connect the drivers to the respective wires,
`
`referring to FIG. 2 reproduced below, Ichioka expressly disclosed these connection
`
`pads: "[e]ach data line terminates in a data line electrode or data line pad 22
`
`[blue]. Also formed on substrate 10 are a large number of gate lines 24 each
`
`terminating in a gate line electrode or a gate line pad 26 [blue]." Ex. 1007 at
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`3:21-29 (emphasis added), FIG. 2. Thus, Ichioka disclosed the need for connection
`
`pads. Ex. 1011 at ¶ 56.
`
`
`
`5.
`
`Shimizu disclosed using dummy conductive patterns with large areas
`
`(at least about 30% of an area of an insulating substrate between
`
`connection pads and pixel electrodes).
`
`Independent claims 1, 9, and 17 include "wherein the plurality of dummy
`
`conductive patterns comprises at least about 30% of an area of the insulating
`
`substrate between the connection pads and the pixel electrodes." Shimizu
`
`disclosed that covering this much area or more was advantageous to reduce
`
`undercutting effects (emphasis added):
`
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`[T]he shape of the aluminum film 3 obtained by
`etching is greatly influenced by the pattern density of the
`photoresist film 7 (the ratio of the area occupied by the
`photoresist film toward the area of the wafer), and side
`etching and undercut occur more easily as the pattern
`density becomes small.
`
`Ex. 1008 at page 2, lines 22-25, FIGS. 3A, 3B, and 4; see also Ex. 1011 at ¶ 57.
`
`FIG. 1A
`
`FIG. 1B
`
`Shimizu further disclosed (emphasis added):
`
`
`
`[A]s shown in Fig. 1 (a) [reproduced above],
`aluminum film 3 is formed on all over the surface of
`silicon oxide film 2 which has been grown on the surface
`of semiconductor substrate 1 [pink], and thereon
`photoresist film 4 in formed by patterning. Here, the
`photoresist film 4 forms dummy pattern 4b in the part
`which is essentially unnecessary, in addition to pattern 4
`which is necessary for forming the wiring pattern. … By
`providing this dummy pattern 4b, the density of the
`whole pattern can be increased to 60%, even in the
`case where the pattern density of the essential pattern
`
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`4a is 10%. Next, as shown in Fig. 1 (b) [reproduced
`above], wiring pattern 3a [grey] and dummy wiring
`pattern 3b [red] are formed with the aluminum film 3 by
`… etching using each of patterns 4a and 4b of the above
`photoresist films as masks.
`
`Ex. 1008 at page 3, lines 30-34, page 4, lines 4-12, FIGS. 1A and 1B; see also id.
`
`at page 4, lines 32-36, page 5, lines 1-6, FIGS. 2A and 2B. In other words,
`
`Shimizu disclosed that after the etching using the patterns 4a and 4b, the density of
`
`both the wiring pattern 3a and the dummy wiring pattern 3b should be as high as
`
`60%, even when the density of just the wiring pattern 3a is 10%, and accordingly
`
`the density of the dummy wiring pattern 3b is 50%. Ex. 1011 at ¶ 58.
`
`Thus, Shimizu disclosed that the density of the plurality of dummy conductive
`
`patterns should be more than 30% of an area of the insulating substrate. Id.
`
`6.
`
`Obvious to combine teachings of Noda, the AAPA, Tsujimura,
`
`Ichioka, and Shimizu
`
`According to Prof. Kuo, it would have been obvious to combine the above
`
`two-layer structure teachings of the AAPA with those of Noda because the AAPA
`
`taught that it was advantageous to use the specifically claimed two-layer metal
`
`structure to implement the drain wires DL and gate lines GL such as those used in
`
`Noda. Ex. 1011 at ¶ 59. For example, the AAPA recognized that the two-layer
`
`metal structure of the AAPA would ensure a proper tapered shape of wiring. See
`
`Ex. 1003 at 1:46-60.
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`Prof. Kuo also explains that it would have been obvious to combine the
`
`above-discussed teachings of Tsujimura with those of Noda because like the
`
`AAPA, Tsujimura taught using the specifically claimed two-layer metal structure
`
`to implement gate lines such as those used in Noda. Ex. 1011 at ¶ 60. Further, the
`
`two-layer metal structure of Tsujimura would ensure a proper tapered shape of
`
`wiring. See Ex. 1006 at page 424, column 1, last paragraph, page 424, column 2,
`
`first paragraph, FIG. 1.
`
`It would have been obvious to combine the above-discussed aspects of
`
`Ichioka with those of Noda because Ichioka disclosed the well-known use of the
`
`connection pads 22 and 26 terminating into the data and gate lines, respectively,
`
`which correspond to the drain wires DL and gate lines GL of Noda. Ex. 1011 at ¶
`
`61. Also, one of ordinary skill in the art would recognize that the connection pads
`
`22 and 26 of Ichioka may be used to connect the drivers to the drain wires DL and
`
`gate lines GL of Noda. Ex. 1011 at ¶ 61. Additionally, the connection pads of
`
`Ichioka would be used to electrically test charge arrays of TFT displays prior to the
`
`attachment of line drivers. See Ex. 1007 at 1:33-42.
`
`It would have been obvious to combine the above-discussed aspects of
`
`Shimizu with those of Noda because Shimizu disclosed that it is advantageous to
`
`use the large dummy wiring patterns 3b that cover 50% of the overall area. Ex.
`
`1011 at ¶ 62. For example, Shimizu disclosed that such a high density of dummy
`
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`patterns suppresses undercutting during etching and side etching in a wiring
`
`pattern. See Ex. 1008 at page 4, lines 9-12.
`
`***
`
`Claims 1, 3, 5-6, 9, 11, 14, and 17 are rendered obvious under Noda in view
`
`of the AAPA, Tsujimura, Ichioka, and Shimizu, as shown in the claim charts
`
`below.
`
`Claim 1
`An array substrate for
`display, comprising:
`
`Noda, AAPA, Tsujimura, Ichioka, and Shimizu
`"Pixel electrodes [12] formed by ITO are provided
`in a matrix shape on a transparent insulating
`substrate of a TFT array side substrate 11 which
`constitutes a polysilicon-typed TFT active-matrix
`liquid crystal display." Ex. 1005 at Abstract, FIG.
`5; see also id. at ¶ [0001].
`
`
`FIG. 5
`
`[a] an insulating substrate;
`
`
`
`
`Ex. 1011 at ¶ 63.
`"Pixel electrodes [12] formed by ITO are provided
`in a matrix shape on a transparent insulating
`substrate of a TFT array side substrate 11 which
`constitutes a polysilicon-typed TFT active-matrix
`
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`liquid crystal display." Ex. 1005 at Abstract, FIG.
`5; see also id. at FIGS. 3, 7-9, 11, 13, ¶¶ [0005],
`[0025], [0037], and [0039].
`
`Ex. 1011 at ¶ 63.
`"Conventionally, in a display, for example, in a
`polysilicon-typed TFT (Thin Film Transistor:
`TFT) mode active matrix liquid crystal display, etc.,
`a transparent thin-film electrode such as ITO
`(Indium Tin Oxide) is used as the pixel electrode
`thereof. This transparent thin-film electrode is
`formed by patterning after forming the polysilicon-
`type TFT on a glass substrate or the like." Ex.
`1005 at ¶ [0002]; see also id. at Abstract, FIG. 5.
`
`Ex. 1011 at ¶ 63.
`"In the TFT array side substrate 11 … the pixel
`electrode 12 of each of the display pixels
`constituting the liquid crystal display is pattern-
`formed in the vicinity of the intersection points of
`the drain wires DL connected to the drain driver
`and the gate lines GL connected to the gate driver."
`Ex. 1005 at ¶ [0024], FIG. 5; see also id. at ¶¶
`[0004], [0024], FIG. 1.
`
`
`FIG. 5
`
`"each wiring in
`communication
`with at least one
`transistor in the
`thin film array"
`
`[b] a thin film transistor
`array on the insulating
`substrate;
`
`[c] a plurality of wirings on
`the insulating substrate,
`each wiring having a first
`end, each wiring in
`communication with at
`least one transistor in the
`thin film array, and at least
`one of the wirings
`comprising at least an
`upper layer and a lower
`layer of conductive
`materials, wherein the
`upper layer wiring material
`is selected from the group
`consisting of molybdenum,
`chromium, tantalum,
`titanium and alloys thereof;
`
`
`
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`"[W]iring using aluminum is constituted as a two-
`layer structure, in which aluminum is used as a
`lower conductive material, and a material harder to
`be oxidized than aluminum such as chromium,
`tantalum, titanium or molybdenum is used as an
`upper conductive material." Ex. 1003