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`01 UTILITY PATENT APPLICATION TRANSMITTAL
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`(Large Entity)
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`(Only for new nonprovisional applications under 37 CFR 1.53(b))
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`Docket No.
`JP920000310US1
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`TJ
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`TO THE ASSISTANT COMMISSIONER FOR PATENTS
`Box Patent Application
`Washington, D.C. 20231
`Transmitted herewith for filing under 35 U.S.C. 111 (a) and 37 C.F.R. 1.53(b) is a new utility patent application for an °
`04
`invention entitled:
`ARRAY SUBSTRATE FOR DISPLAY, METHOD OF MANUFACTURING ARRAY
`SUBSTRATE FOR DISPLAY AND DISPLAY DEVICE USING THE ARRAY SUBSTRATE
`Assignee Name: International Business Machines Corporation
`Assignee Residence: Armonk,New York
`and invented by:
`Takatoshi Tsujimura, et al.
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`UTILITY PATENT APPLICATION TRANSMITTAL
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`UTILITY PATENT APPLICATION TRANSMITTAL
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`I HEREBY CERTIFY THAT THIS CORRESPONDENCE IS BEING
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`APPLICATION
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`FOR
`
`UNITED STATES LETTERS PATENT
`
`APPLICANT: Takatoshi Tsujimura, et al.
`FOR:
`ARRAY SUBSTRATE FOR DISPLAY, METHOD
`OF MANUFACTURING ARRAY SUBSTRATE
`FOR DISPLAY AND DISPLAY DEVICE
`USING THE ARRAY SUBSTRATE
`JP920000310US1
`
`DOCKET:
`
`INTERNATIONAL BUSINESS MACHINES CORPORATION
`New Orchard Road, Armonk, New York 10504
`
`Page 5 of 147
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`ARRAY SUBSTRATE FOR DISPLAY, METHOD OF MANUFACTURING ARRAY
`
`SUBSTRATE FOR DISPLAY AND DISPLAY DEVICE USING THE ARRAY
`SUBSTRATE
`
`Background of the Invention
`The present invention relates to an array substrate for display, a method of
`
`manufacturing the array substrate for display and a display device using the array substrate
`for display.
`A display device using a thin film transistor (TFT) array has been frequently used
`owing to low power consumption and capability of downsizing the display device. The thin
`film transistor array is manufactured by forming thin film transistors, each being composed
`of electrodes such as a gate electrode, a source electrode and a drain electrode, wirings such
`as scan lines and signal lines connected with the above-mentioned electrodes, and pixel
`electrodes on an insulating substrate.
`In recent years, a higher operating speed, a higher resolution and a larger size have
`been required for the display device described above in many cases. A high speed and a high
`density have been required for each constituent component of the array for display, which
`forms a display device. Particularly, in order to operate the thin film transistor array at a high
`speed, it is preferable to use low-resistance aluminum (Al) for the wirings such as the scan
`lines and the signal lines since delay in gate pulses can be reduced and a writing speed to the
`thin film transistor can be increased.
`Incidentally, aluminum tends to be easily oxidized in spite of its low resistance.
`Therefore, in many cases, wiring using aluminum is constituted as a two-layer structure, in
`which aluminum is used as a lower conductive material, and a material harder to be oxidized
`than aluminum such as chromium, tantalum, titanium or molybdenum is used as an upper
`conductive material. Fig. 11 is a view schematically showing a state where wiring 2 is
`deposited on an insulating substrate 1. A lower conductive material film 2a is deposited on
`an insulating substrate 1 made of such as glass, and an upper conductive material film 2b is
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`deposited on the lower conductive material film 2a. Each of these films 2a and 2b is
`patterned by, for example, a proper etching process so as to have tapered ends.
`In order to form a tapered shape shown in Fig. 11, an etching rate for the upper
`conductive material is required to be increased. In order to form the tapered shape shown
`in Fig. 11, various methods have been proposed up to now. For example, in the gazette of
`Japanese Patent Laid-Open No. Hei 10 (1998)-90706, a method has been proposed, in which
`dummy connection pads are provided on sides opposite to scan line connection pads and
`
`signal line connection pads, respectively. According to this method, over etching due to an
`etchant that will be relatively increased by lowering wiring density at ends of the substrate
`is prevented. Thus, undercut of a lower conductive material 3 is prevented, and an interlayer
`short circuit is prevented by imparting a proper tapered shape to the wiring 2.
`However, though this method enables evenness of etching at the ends of the thin film
`transistor array substrate to be improved, the method cannot effectively prevent the undercut
`of the signal lines in a region where the wiring density is apt to be lowered from ends of the
`pixel electrodes to the connection pads, for example, in a portion where drawing wiring is
`formed.
`Moreover, in the gazette of Japanese Patent Laid-Open No. Hei 10 (1998)-240150,
`disclosed is a method of forming a tapered shape at an angle ranging from 20 degrees to 70
`degrees on wiring constituted of two layers, in which a pad formed of aluminum and metal
`such as molybdenum formed on the aluminum is subjected to wet etching. According to this
`method, a specified tapered shape can be imparted to the wiring formed of a conductive film
`of a two-layer structure by the wet etching. However, the method never discloses a method
`of evenly etching a substrate region while maintaining a selection ratio thereof even in the
`substrate region where the wiring density is lowered.
`Figs. 12A and 12B are enlarged schematic views for explaining a patterning process
`using a conventionally used wet process in order to impart the above-described tapered shape
`to the wiring.
`As shown in Fig. 12A, the lower conductive material 3 and an upper
`conductive material 4 are deposited on the insulating substrate 1 by a method such as
`physical vapor deposition. Fig. 12A shows that a photoresist film 5 is coated on a film of the
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`upper conductive material 4 and is patterned in a desired shape. The respective films are
`etched by an etchant such as a solution of phosphoric acid, nitric acid, acetic acid or mixtures
`thereof, and desired tapered shapes are formed thereon.
`Fig. 12B is a view for explaining an electrochemical process generated as each film
`is being etched when the wiring constituted of the upper conductive material 4 and the lower
`conductive material 3 is subjected to wet etching. In Fig. 12B, an internal layer portion of
`the upper conductive material 4 coated with the photoresist film 5 is not dissolved.
`However, at the end of the photoresist film 5, the upper conductive material 4 is dissolved
`by the etchant. When the wiring is formed by the wet etching, the upper conductive material
`4 protected by the photoresist film 5 is further dissolved in a lateral direction from the end
`of the photoresist film 5 to turn into positive ions, and electrons emitted as a result are
`supplied to the lower conductive material 3. Thus, the upper conductive material 4 serves
`as an anode. In this connection, the lower conductive material 3 comes to serve as a cathode.
`Accordingly, an electrochemical cell is formed. Here, when the etching rate for the upper
`conductive material 4 is increased to form a required tapered shape, the density of the
`electrons generated by dissolving the upper conductive material 4 and flowing to the lower
`conductive material 3 is increased accompanied with an increase of a dissolution rate of the
`upper conductive material 4. Fig. 12B schematically shows currents I flowing from the upper
`conductive material 4 to the lower conductive material 3.
`As the etching rate is increased, the density of the current flowing to an area of the
`upper conductive material 4, which is exposed to the etchant, exceeds a current density
`causing passivity of the upper conductive material 4. In such a case, the upper conductive
`material 4 is passivated not to be dissolved by the etchant, and only the lower conductive
`material 3 is dissolved accompanied with the progress of the etching, resulting in the
`occurrence of the undercut. When such undercut occurs, the wiring, for example, the gate
`wiring cannot be sufficiently coated with an insulating film in some cases, thus causing
`inconvenience such as an interlayer short circuit, resulting in lowering a yield of the display
`device.
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`Summary of the Invention
`The present invention was made with the foregoing problems in mind. An object of
`the present invention is to provide an array substrate for display, a method of manufacturing
`an array substrate for display and a display device using the array substrate for display, which
`are capable of being etched at a sufficiently high etching rate and a sufficient selection ratio,
`eliminating undercut, and providing a large-sized and high-resolution display device.
`The foregoing object of the present invention is achieved by providing the array
`substrate for display, the method of manufacturing an array substrate for display and the
`display device using the array substrate for display of the present invention.
`Specifically, according to the present invention, provided is an array substrate for
`display, comprising: a thin film transistor array formed on an insulating substrate; a plurality
`of wirings arranged on the insulating substrate; connection pads arranged on unilateral ends
`of the wirings and respectively connected with the wirings; pixel electrodes, and dummy
`conductive patterns arranged between the ends of the connection pads and ends of the pixel
`electrodes. The dummy conductive patterns can occupy 30 area% or more. In the present
`invention, the dummy conductive patterns can be formed as any of land patterns and
`line-and-space patterns. In the present invention, the wirings are constituted of a lower
`conductive material and an upper conductive material, and the lower conductive material can
`be any one of aluminum and an aluminum alloy. In the present invention, the upper
`conductive material has a passivating potential. The upper conductive material can be any
`one of molybdenum and a molybdenum alloy.
`According to the present invention, provided is a method of manufacturing an array
`substrate for display, the method comprising the steps of: forming a thin film transistor array
`including: a plurality of wirings arranged on an insulating substrate; and connection pads
`arranged on unilateral ends of the wirings and respectively connected with the wirings;
`forming pixel electrodes; and forming dummy conductive patterns between ends of the
`connection pads and ends of the pixel electrodes. In the present invention, it is preferable
`that the dummy conductive patterns be formed so as to occupy 30 area% or more. In the
`present invention, the dummy conductive patterns can be formed as any of land patterns and
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`line-and-space patterns. In the present invention, the wirings are constituted of a lower
`conductive material and an upper conductive material, the lower conductive material can be
`
`any one of aluminum and an aluminum alloy, and the upper conductive material can be any
`
`one of molybdenum and a molybdenum alloy. In the present invention, the wirings are
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`formed by wet etching.
`Moreover, in the present invention, provided is a display device, comprising the array
`substrate for display mentioned above.
`In the present invention, the display device used as a liquid crystal display device or
`an electroluminescence display device can be provided.
`
`Brief Description of the Drawings
`For a more complete understanding of the present invention and the advantages
`thereof, reference is now made to the following description taken in conjunction with the
`accompanying drawings.
`[Figure 1]
`Fig. 1 is a view showing an embodiment of a liquid crystal display device using an
`array substrate for display of the present invention.
`[Figure 2]
`Fig. 2 is a top plan view of the array substrate for display of the present invention.
`[Figure 3]
`Fig. 3 is an enlarged view showing a dummy conductive pattern in the present
`invention.
`[Figure 4]
`Fig. 4 is an enlarged view showing another dummy conductive pattern in the present
`invention.
`[Figure 5]
`Figs. 5A to 5C are views illustrating a method of manufacturing the array substrate
`for display of the present invention.
`[Figure 6]
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`Fig. 6 is an electron microscope photograph showing a pattern shape of wiring in the
`case of using the dummy conductive pattern shown in Fig. 3.
`
`[Figure 7]
`Fig. 7 is an electron microscope photograph showing a pattern shape of wiring in the
`case of using the dummy conductive pattern shown in Fig. 4.
`[Figure 8]
`Fig. 8 is a graph showing a relation between a taper angle of the wiring and a pattern
`
`density of the wiring.
`[Figure 9]
`Fig. 9 is an electron microscope photograph showing a wiring shape in the case of
`performing etching without using the dummy conductive pattern.
`[Figure 10]
`Fig. 10 is an electron microscope photograph showing a sectional shape of the wiring
`
`shape shown in Fig. 9.
`[Figure 11]
`Fig. 11 is a schematic view showing a tapered shape of the wiring.
`[Figure 12]
`Figs. 12A and 12B are views showing currents formed by a cell formed during an
`etching process.
`
`Detailed Description of the Preferred Embodiments
`
`Hereinbelow, description will be made in detail for the present invention with
`reference to embodiments shown in the accompanying drawings. However, the present
`invention is not limited to the embodiments shown in the drawings.
`Fig. 1 is a partially cutaway perspective view showing an embodiment of a display
`device using an array substrate for display of the present invention. As shown in Fig. 1, the
`display device of the present invention is constituted by sequentially laminating a liquid
`crystal layer 11, a transparent electrode 12 and a glass substrate 13 on an array substrate 10
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`for display, which is formed on an insulating substrate. Wiring 14 formed on the insulating
`substrate 10 is extended to an end (not shown) of the array substrate for display, and is
`connected with a driving system (not shown) through a connection pad (not shown).
`Fig. 2 is a top plan view of the display device using the array substrate 10 for display
`
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`present invention, a plurality of thin film transistors 21 constitute an array. A pixel electrode
`22 is connected with each thin film transistor 21 that controls a potential of the pixel
`electrode. In the array substrate 10 for display shown in Fig. 2, what is further shown is that
`a scan line 23 and a signal line 24 are connected with each thin film transistor 21.
`The respective scan lines 23 are connected with a driver 26 through scan line
`connection pads 25, and the respective signal lines 24 are connected with a driver 28 through
`signal line connection pads 27. These scan lines 23 and the signal lines 24 are formed so as
`to have the same constitution. As shown in Fig. 11, each of these lines is constituted of the
`lower conductive material 3 and the upper conductive material 4.
`In the present invention, aluminum can be used for the lower conductive material 3
`usable as wiring from a viewpoint of lowering resistance thereof. Moreover, it is preferable
`to use molybdenum (Mo) for the upper conductive material 4 usable in the present invention
`from a viewpoint of protecting the aluminum. However in the present invention, besides the
`aluminum, an aluminum alloy can be used for the lower conductive material 3. Moreover,
`for the upper conductive material 4, alloys of chromium, tantalum, titanium and molybdenum
`can be used. Film thickness of the lower conductive material 3 is not particularly limited,
`but film thickness of the upper conductive material 4 is preferably thick since a current tends
`to be concentrated thereto as the film thickness becomes thinner. However, a problem
`regarding stress occurs as the thickness becomes thicker. Therefore, in the present invention,
`it is preferable to set the film thickness of the upper conductive material 4 in a range of 30
`to 100 nm.
`The present invention makes it possible to prevent undercut of the lower conductive
`material 3, which occurs due to passivity of the upper conductive material 4. In the present
`invention, the term "passivity" is referred to as a phenomenon that metal such as
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`molybdenum or a metal alloy such as a molybdenum alloy becomes insoluble in an acid or
`alkaline etchant. For example, the term "passivity" is referred to as a phenomenon that metal
`
`serving as an anode becomes insoluble in such etchant. In the present invention, specifically
`
`as for such passivated metal or a metal alloy, metal or a metal alloy with a passivating
`potential, that is, a Flade potential can be mentioned. Note that, in the present invention, the
`Flade potential is referred to as a potential which causes a current density for passivating
`metal, which is described in the Encyclopedia Chimica (miniature edition 32nd printing,
`issued by Kyoritsu Shuppan Co., Ltd., edited by editorial committee of the Encyclopedia
`Chimica), vol. 7, p. 911.
`Furthermore, in the embodiment shown in Fig. 2, dummy conductive patterns 29 are
`disposed between the pixel electrodes 22 and each scan line connection pad 25 and between
`the pixel electrodes 22 and each signal line connection pad 27. Thus, the wiring density is
`increased. Therefore, it is made possible to form good wiring over the entire surface of the
`array substrate for display without causing defects such as undercut and a mouse hole of the
`lower conductive material 3 during etching for the scan lines 23 and the signal lines 24.
`Each of these dummy conductive patterns 29 can be formed as a two-layers structure with
`the same materials as those of the scan lines 23 and the signal lines 24 at the same time when
`the patterning is performed therefor.
`Fig. 3 is an enlarged view showing a portion where the dummy conductive pattern
`29 is formed in the embodiment of the array substrate 10 for display of the present invention
`shown in Fig. 2. Fig. 3 shows the dummy conductive pattern 29 formed as a line-and-space
`pattern between the connection pad 25 and an end 30 of the pixel electrode. In the present
`invention, the dummy conductive pattern 29 can be formed as the line-and-space pattern
`shown in Fig. 3. Alternatively, the dummy conductive pattern 29 can be formed as a land
`pattern completely coating a region where the dummy conductive pattern 29 is formed.
`In any case of the patterns, in the present invention, it is preferable that the wiring
`density of the dummy conductive patterns 29 themselves be 30% or more on an area of a
`specified surface from a viewpoint of forming a properly tapered shape on the lower
`conductive material 3 without forming the undercut thereto while dissolving the upper
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`conductive material 4 at a required rate.
`Moreover, when the dummy conductive patterns 29 are arranged in the present
`invention, it is more preferable that the dummy conductive patterns 29 be formed between
`the end 30 of the pixel electrode 22 and each connection pads 25 and 27 so that the wiring
`density including the dummy conductive patterns 29 can be 30% or more on the area of a
`specified surface. In the present invention, the term "wiring density" refers to an area ratio
`of an area of portions where the signal lines, the scan lines, the drawing lines, and the dummy
`conductive patterns are formed on an area of a specified region where the dummy conductive
`
`patterns are formed.
`Fig. 4 is a view showing another embodiment of the dummy conductive pattern 29
`of the present invention. In the embodiment shown in Fig. 4, the dummy conductive pattern
`29 is disposed so that the wiring density thereof, which is specified at 30% or more, is further
`increased, thus reducing concentration of electric current to exposed portions of the upper
`conductive material to the etchant during the etching. As shown in Fig. 4, the dummy
`conductive pattern 29 may have any shapes and any patterns. Moreover, any combination
`of a plural type of the dummy conductive patterns 29 can be used.
`Figs. 5A, 5B and 5C are views showing an embodiment of a method of
`manufacturing the array substrate 10 for display of the present invention. With reference to
`Fig. 5, description will be made for the method of manufacturing the array substrate 10 for
`display of the present invention, exemplifying a case where the thin film transistor 21 of a
`reverse stagger type is formed. First, as shown in Fig. 5A, the lower conductive material 3
`using aluminum and the upper conductive material 4 using molybdenum are deposited on the
`transparent or untransparent insulating substrate 1, thus forming a film.
`Next, as shown in Fig. 5B, photoresist 31 is coated on the film. The photoresist is
`exposed and developed by use of a photo mask 32 provided with patterns for forming the
`dummy conductive patterns 29 in portions where the wiring density is lowered between the
`pixel electrodes and the connection pads, which are not particularly shown.
`Subsequently, etching is performed by use of an etchant such as a solution of
`phosphoric acid, nitric acid, acetic acid and mixtures thereof, thus forming the wiring 2 and
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`the dummy conductive patterns 29. The dummy conductive patterns 29 are arranged in the
`portions where the wiring density is low. Thus, it is made possible to form wirings having
`good tapered shape as shown in Fig. 5C even in regions where the conductive material such
`
`as molybdenum tends to be passivated. A taper angle can be set in a range of 20 degrees to
`70 degrees by adjusting a composition of the etchant and etching conditions. It is more
`
`preferable to set the taper angle in a range of about 20 degrees to about 60 degrees.
`Thereafter, in the present invention, gate insulating films, the gate electrodes, the
`source electrodes, the drain electrodes, the pixel electrodes and the like are formed, thus the
`array substrate 10 for display of the present invention is manufactured. In the present
`
`invention, the dummy conductive patterns 29 may be removed if necessary. Alternatively,
`the dummy conductive patterns 29 may be left as they are without being eliminated.
`Fig. 6 is an electron microscope photograph showing a shape of the wiring 33 shown
`in Fig. 3, which was obtained when the dummy conductive pattern 29 shown in Fig. 3 was
`provided and the etching was performed. In this case, molybdenum was used for the upper
`conductive material 4, and aluminum was used for the lower conductive material 3. The film
`thickness of molybdenum is about 50 nm, and wet etching is performed by use of an etchant
`of a mixed solution of phosphoric acid, nitric acid and acetic acid. As shown in Fig. 6, a
`good tapered shape is formed even in a wiring portion where the undercut is formerly apt to
`occur by forming the dummy conductive pattern 29.
`Fig. 7 is a photograph showing a shape of the wiring 34 shown in Fig. 4, which was
`obtained when the dummy conductive pattern 29 shown in Fig. 4 was formed and the etching
`was performed under the same conditions as those in Fig. 6. As shown in Fig. 7, even when
`the density of the dummy conductive pattern 29 is increased, a good tapered shape is
`obtained.
`Fig. 8 is a graph plotting values of the taper angle of the formed wiring relative to
`values of the pattern density (area%) of the wiring including the portions of the dummy
`conductive patterns 29 on the substrate when the dummy conductive patterns 29 are
`arranged. As shown in Fig. 8, the taper angle of the wiring obtained by the etching is
`reduced as the pattern density of the wiring is increased, and a more gentle taper is formed.
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`Therefore, it is understood that the upper conductive material 4 can impart a sufficient
`selective ratio to the etching of the lower conductive material 3 by arranging the dummy
`conductive patterns 29.
`Fig. 9 is an electron microscope photograph showing, for comparison, a shape of
`wiring obtained when etching is performed by use of the array substrate 10 for display, which
`has the same pattern as those shown in Figs. 3 and 4, but without forming the dummy
`conductive patterns 29 at all. As shown in Fig. 9, large undercut occurs in the wiring since
`the molybdenum used for the upper conductive material 4 is passivated, and only the etching
`for the aluminum as the lower conductive material 3 progresses.
`Fig. 10 is an electron microscope photograph showing a cross section taken along a
`cutting plane line A-A of the wiring shown in Fig. 9. As shown in Fig. 10, the etching for
`the aluminum used for the lower conductive material 3 progresses more than that for the
`molybdenum used for the upper conductive material 4, resulting in the occurrence of the
`great undercut.
`The present invention ca