`571-272-7822
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` Paper 9
`Entered: September 9, 2015
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SHARP CORPORATION, SHARP ELECTRONICS CORPORATION, and
`SHARP ELECTRONICS MANUFACTURING COMPANY OF
`AMERICA, INC.,
`Petitioner,
`
`v.
`
`SURPASS TECH INNOVATION LLC,
`Patent Owner.
`____________
`
`Case IPR2015-00913
`Patent 7,420,550 B2
`____________
`
`
`
`Before SALLY C. MEDLEY, BRYAN F. MOORE, and BETH Z. SHAW,
`Administrative Patent Judges.
`
`SHAW, Administrative Patent Judge.
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`IPR2015-00913
`Patent 7,420,550 B2
`
`
`I.
`INTRODUCTION
`Sharp Corporation, Sharp Electronics Corporation, and Sharp
`Electronics Manufacturing Company of America, Inc. (“Petitioner”) filed a
`Petition (“Pet.”) to institute an inter partes review of claims 1–5 of Patent
`7,420,550 B2 (the “’550 patent”) pursuant to 35 U.S.C. §§ 311–319. Paper
`1. Surpass Tech Innovation LLC (“Patent Owner”) filed a Preliminary
`Response (“Prelim. Resp.”) to the Petition. Paper 8. We have jurisdiction
`under 35 U.S.C. § 314, which provides that an inter partes review may not
`be instituted “unless . . . there is a reasonable likelihood that the petitioner
`would prevail with respect to at least 1 of the claims challenged in the
`petition.” 35 U.S.C. § 314(a).
`For the reasons set forth below, we institute an inter partes review of
`claims 1–5 of the ’550 patent.
`
`A. Related Matters
`Petitioner indicates that the ’550 patent is asserted in Surpass Tech
`Innovation LLC v. Samsung Display Co., Ltd. et al. (Civil Action No. 1:14-
`cv-00337-LPS) and Surpass Tech Innovation LLC v. Sharp Corporation et
`al. (Civil Action No. 1:14-cv-00338-LPS). Pet. 7. We denied inter partes
`review of the’550 patent on March 10, 2015 in IPR2015-00022, Paper 9.
`B. The ’550 Patent (Ex. 1001)
`The ’550 patent is titled “Liquid Crystal Display Driving Device of
`Matrix Structure Type And Its Driving Method.” Ex. 1001, Title. The ’550
`patent specifically discloses a matrix structure arrangement for a liquid
`crystal display (LCD) panel in which pixels are arranged in rows and
`columns.
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`An example of this structure is shown in Figures 4A and 4B of the
`’550 patent. Figure 4A is reproduced below:
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`Figure 4A depicts a schematic view showing the arrangement of the gate
`lines and the data lines of the display panel. Ex. 1001, 4:49–51. Figure 4B
`is reproduced below:
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`Figure 4B depicts an enlarged schematic sectional view taken from Fig. 4A,
`which shows the arrangement of the gate lines and the data lines and the
`state of the gate and the source, which are connected to the gate lines and the
`data lines, of each thin film transistor. Id. at 4:52–56.
`As shown in Fig. 4A and Fig. 4B, data lines D1, D1’, D2, D2’ are
`connected to source drivers, and the data lines are grouped in pairs, such as
`D1 and D1’. The first and the second data lines D1, D1’ of the first group of
`data lines respectively are connected with the sources of all the thin film
`transistors Q of the odd and the even rows of the first column. Id. at 8:23–
`26.
`
`The driving device includes a group of thin film transistors Q with
`matrix array, which consists of N rows and M columns of thin film
`transistors, wherein, each thin film transistor Q can drive one pixel, so NxM
`pixels (shown by rectangle with dotted line) can be driven. Id. at 8:12–17.
`The first gate line G1 is connected with the gates of all the thin film
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`transistors Q of the first row, the second gate line G2 is connected with the
`gates of all the thin film transistors Q of the second row, and so are the
`others. Id. at 8:17–20.
`
`
`C. Illustrative Claim
`Independent claim 1 of the ’550 patent is illustrative and recites:
`1. A liquid crystal display driving device of matrix
`structure type including:
`a group of thin film transistors with matrix array
`consisting of N rows and M columns of thin film transistors,
`wherein each thin film transistor can drive one pixel so that
`N×M of pixels can be driven;
`a group of N gate lines connected to the gate drivers and
`insulated with each other, wherein the first gate line is
`connected with the gates of all the thin film transistors of the
`first row, the second gate line is connected with the gates of all
`the thin film transistors of the second row . . . and the Nth gate
`line is connected with the gates of all the thin film transistors of
`the Nth row; and
`M groups of data lines connected to the source drivers
`and insulated with each other, wherein the first and the second
`date lines of the first group of date lines are respectively
`connected with the sources of all the thin film transistors of the
`odd and the even rows of the first column, the first and the
`second data lines of the second group of data lines are
`respectively connected with the sources of all the thin film
`transistors of the odd and the even rows of the second
`column . . . and the first and the second data lines of the Mth
` group of data lines are respectively connected with the sources
`of the all thin film transistors of the odd and the even rows of
`the Mth column, and the first data lines and the second data lines
`of each group of data lines are connected with the same source
`driver.
`
`
`D. The Prior Art
`Petitioner relies on the following prior art references as its basis for
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`challenging claims 1–5 of the ’550 patent.
`
`Reference
`Sharp
`
`Shimada et al.
`
`Kamizono et al.
`
`
`
`Publication
`Japanese Patent
`Publication No. H08-
`305322
`U.S. Patent No.
`6,081,250
`U.S. Patent No.
`6,407,795 B1
`
`Exhibit
`Ex. 1002 (“Sharp”)
`
`Ex. 1003 (“Shimada”)
`
`Ex. 1004 (“Kamizono”)
`
`E. The Asserted Grounds of Unpatentability
`Petitioner contends the challenged claims are unpatentable under
`35 U.S.C. § 103 based on the following grounds (Pet. 10–11):
`Ground
`Statutory
`Basis
`Number
`Ground
`1.
`§ 102(b)
`2.
`§ 103
`3.
`§ 103
`4.
`§ 103
`
`Sharp
`Sharp
`Sharp and Kamizono
`Shimada and Kamizono
`
`Challenged
`Claim(s)
`1–3
`1–3 and 5
`1–5
`1–5
`
`
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`F. Claim Interpretation
`Consistent with the statute and legislative history of the America
`Invents Act (AIA), the Board interprets claims using the “broadest
`reasonable construction in light of the specification of the patent in which
`[they] appear[].” 37 C.F.R. § 42.100(b); see also Office Patent Trial
`Practice Guide, 77 Fed. Reg. 48,756, 48,766 (Aug. 14, 2012).
`Petitioner proposes claim constructions for “gate drivers” and “source
`drivers,” “the first and the second date lines of the first group of date lines,”
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`“[G]ate lines…insulated with each other” and “data lines . . . insulated with
`each other.” See Pet. 19–23. At this point in the proceeding, Patent Owner
`does not specifically contest these claim constructions. Prelim. Resp. 1–28.
`We adopt Petitioner’s proposed constructions for the following terms,
`as we determine them to be consistent with the broadest reasonable
`construction:
`
`
`CLAIM TERM
`
`date lines
`insulated with each other
`
`CONSTRUCTION
`data lines
`spaced apart from and parallel to
`each other
`
`
`For purposes of this decision, we need not construe any other
`limitations of the challenged claims.
`II. ANALYSIS
`We turn now to Petitioner’s asserted grounds of unpatentability and
`Patent Owner’s arguments in its Preliminary Response to determine whether
`Petitioner has met the threshold standard of 35 U.S.C. § 314(a).
`
`A. Obviousness of Claims 1–5 over the Combination of Sharp and
`Kamizono
`Petitioner alleges claims 1–5 would have been obvious over the
`combination of Sharp and Kamizono. Pet. 38–47. Upon consideration of
`Petitioner’s explanations and supporting evidence, we are persuaded by
`Petitioner’s contentions. In particular, Petitioner points to Sharp’s Figure
`10, which is reproduced below (with color annotations added by Petitioner):
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`Sharp’s Figure 10 depicts each gate bus line 6 is associated with an AND
`circuit 81 (shaded in orange and labeled 1, 2, or 3), and an output from gate
`shift register 3a (the orange rectangle). Each gate bus line 6 is individually
`driven by the output of an AND circuit 81. Ex. 1002 ¶¶ 142–45.
`Petitioner argues Sharp teaches that the gate bus lines 6 are spaced
`apart from and parallel to each other, and that the source bus lines 5 are also
`spaced apart from and parallel to each other, as shown in Figure 10. Pet. 27
`(citing Ex. 1002, Fig. 10). We agree that the gate bus lines 6 depicted in
`Figure 10 are spaced apart from and parallel to each other, and that source
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`bus lines 5 are also spaced apart from and parallel to each other. Therefore,
`we agree that based on this record, Sharp teaches “a group of N gate lines
`connected to the gate drivers and insulated with each other,” and “M groups
`of data lines connected to the source drivers and insulated with each other,”
`as recited in claims 1–5.
`Petitioner alleges Figure 10 shows more than one gate driver and also
`more than one source driver. Id. at 26 citing Ex. 1007 ¶ 86. Mr. Marentic
`explains that the first source driver includes AND circuit 72 (labeled “1”) in
`communication with shift register 10, data signal lines 73, 74, sampling
`switches 19, 20, and sampling capacitors 24, 25. Ex. 1007 ¶¶ 86–88. The
`second source driver includes AND circuit 72 (labeled “2”) in
`communication with shift register 10, sampling switches 21 and 22, and
`sampling capacitors (not numbered). Id. Mr. Marentic explains that each set
`of first and second source bus lines 5 associated with each column of pixel
`units 4 are individually driven by a separate source driver. Id. ¶ 88.
`Moreover, Petitioner alleges, Figure 10 shows that the first and second
`source bus lines 5 in each group of source bus lines are connected with the
`“same source driver,” as recited in claim 1. Pet. 26. (citing Ex. 1002, Fig.
`10, ¶¶ 131–140).
`Petitioner argues that even if Sharp does not teach or suggest the use
`of multiple source drivers and gate drivers, Kamizono teaches the use of
`multiple source drivers and multiple gate drivers to send signals through data
`lines and gate lines in an LCD device. Pet. 40 (citing Ex. 1004, Fig. 15).
`Mr. Marentic explains that modifying the LCD driving device of the Sharp
`reference to include the multiple source and gate driver ICs of Kamizono
`would merely yield a predictable result, since such a modification simply
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`allows more pixels to be added to increase the size of the LCD panel without
`changing the way the LCD panel operates. Id. at 42 (citing Ex. 1007 ¶ 148).
`Patent Owner does not specifically contest the Petitioner’s arguments
`regarding the alleged multiple source drivers and gate drivers in Sharp or
`Kamizono.
`Based on this record, we agree with Petitioner that the combination of
`Sharp and Kamizono meets the limitation of multiple source drivers and
`multiple gate drivers.
`We also agree with Petitioner that, based on this record, the
`combination of Sharp and Kamizono meets the odd/even configuration
`limitation recited in claim 1, specifically:
`the first and the second date lines of the first group of date lines
`are respectively connected with the sources of all the thin film
`transistors of the odd and the even rows of the first column, the
`first and the second data lines of the second group of data lines
`are respectively connected with the sources of all the thin film
`transistors of the odd and the even rows of the second
`column . . . and the first and the second data lines of the Mth
` group of data lines are respectively connected with the sources
`of the all thin film transistors of the odd and the even rows of
`the Mth column
` (emphasis added). See id. at 27–28, citing Ex. 1002, Fig. 10, ¶¶ 131–140,
`145. For example, we agree that Sharp teaches the first source bus line 5
`and the second source bus line 5 in each group of data bus lines are
`respectively connected with the sources of all of the 28 TFTs 7 of the odd
`and even rows of the column associated with that group of source bus lines.
`Ex. 1002, Fig. 10.
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`Therefore, on this record, we determine that Petitioner has
`demonstrated sufficiently for purposes of this Decision that the combination
`of Sharp and Kamizono renders obvious claims 1–3.
`Claim 4 depends from claim 2 and adds the limitation “wherein the
`gate driver is a chip installed on glass.” Claim 5 also depends on claim 2
`and adds the limitation “wherein the gate driver is an integrated gate driver
`circuit installed on glass.” Petitioner contends “Kamizono teaches that
`installing driving circuitry, including the gate drivers as a COG is the
`preferred way of implementing the gate drivers for a large sized LCD panel
`because it provides increased reliability and reduces the form factor (i.e.,
`size and weight) of the product.” Pet. 42 (citing Ex. 1004, Kamizono, col.
`1:12–58). We agree that Kamizono teaches the gate driver is a chip on
`glass, as recited in dependent claim 4, and the integrated gate driver circuit
`installed on glass, as recited in dependent claim 5.
`Patent Owner argues this ground is substantially similar to the ground
`presented unsuccessfully in IPR2015-00022 and that the Board should deny
`the Petition under 35 U.S.C. § 325(d). Prelim. Resp. 23. However, unlike in
`IPR2015-00022, in this case Petitioner directs our attention to evidentiary
`support for the combination of Sharp and Kamizono, in the form of a
`declaration to support the combination of the cited references. Ex. 1007.
`Thus, given the evidence in this record, we determine that Petitioner
`has demonstrated that there is a reasonable likelihood that Petitioner will
`prevail in showing that claims 1–5 of the ’550 patent are unpatentable as
`obvious over the combination of Sharp and Kamizono.
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`B. Other Asserted Grounds
`As summarized in Section I(E) of this Decision, Petitioner asserts four
`grounds of unpatentability. The other asserted grounds are against claims 1–
`5 as obvious over Shimada and Kamizono, against claims 1–5 as
`anticipation by Sharp; and against claims 1–3 and 4 as obvious over Sharp
`alone. See Pet. 10–11.
`Under 37 C.F.R. § 42.108(a), the Board has discretion to “authorize
`the review to proceed on all or some of the challenged claims and on all or
`some of the grounds of unpatentability asserted for each claim.” The Board
`also “may deny some or all grounds for unpatentability for some or all of the
`challenged claims.” 37 C.F.R. § 42.108(b); see also 35 U.S.C. § 314(a)
`(permitting institution of review under certain conditions, but not mandating
`institution of review under any conditions).
`Pursuant to 35 U.S.C. § 316(b), rules for inter partes proceedings
`were promulgated to take into account the “regulation on the economy, the
`integrity of the patent system, the efficient administration of the Office, and
`the ability of the Office to timely complete proceedings.” The promulgated
`rules provide that they are to “be construed to secure the just, speedy, and
`inexpensive resolution of every proceeding.” 37 C.F.R. § 42.1(b). As a
`result, and in determining whether to institute an inter partes review of a
`patent, the Board, in its discretion, may “deny some or all grounds for
`unpatentability for some or all of the challenged claims.” 37 C.F.R. §
`42.108(b).
`We exercise our discretion and decline to institute review based on
`any of the other asserted grounds advanced by Petitioner that are not
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`identified below as being part of the trial. See, e.g., Pet. 6; 37 C.F.R. §
`42.108(a).
`
`III. CONCLUSION
`For the foregoing reasons, we determine that Petitioner has shown a
`reasonable likelihood that it would prevail in demonstrating that the
`challenged claims 1–5 of the ’550 patent are unpatentable under 35 U.S.C.
`§ 103(a). At this juncture, we have not made a final determination with
`respect to the patentability of the challenged claims, nor with respect to
`claim construction.
`
`IV. ORDER
`ORDERED that pursuant to 35 U.S.C. § 314(a), an inter partes
`review is hereby instituted for the following ground of unpatentability:
`Claims 1–5 under 35 U.S.C. § 103 as obvious over Sharp and
`Kamizono.
`FURTHER ORDERED that pursuant to 35 U.S.C. § 314(c) and
`37 C.F.R. § 42.4, notice is hereby given of the institution of a trial; the trial
`will commence on the entry date of this Decision.
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`Patent 7,420,550 B2
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`PETITIONER:
`
`Anthony Lo Cicero
`Brian Comack
`Amster, Rothstein & Ebenstein LLP
`alocicero@arelaw.com
`sharp-550IPR@arelaw.com
`
`PATENT OWNER:
`
`
`Wayne Helge
`Michael Casey
`Davidson Berquist Jackson & Gowdey, LLP
`whelge@dbjg.com
`mcasey@dbjg.com
`
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