United States Patent I lOl
`Shimada et al.
`
`IJatent Number:
`[II[
`[45[ Date of l'atent:
`
`111111111111111111111111111
`
`1111111111111111111
`
`6,081,250
`.J un. 27, 2000
`
`[54[ ACTI VE MATRIX ))I SI'LAY I)f;VICt; ANI)
`ITS DRI VING METHOD
`
`[75[
`
`Inventors: Tukay uki Sh imada, Nara-ken;
`Toshihiro Ya mashitll; Yuhllul
`Takafuji, uUlh uf Nara, all uf Japau
`
`[73[ A'>Signee: Sha rp Kab ushiki Kaisha , Osaka, Japan
`
`[21[
`
`Appl. No.: 08/266,159
`
`[22[
`
`Filed:
`
`Jun. 27, 1994
`
`Related U.S. App lication Uatll
`
`1631
`
`Continual ion o f applicalion No. OMW, 11 5, Jan. 26, 1993,
`abandoned.
`Foreign Appliclltion l>riority I)ata
`
`1)01
`Jan. 3 1, 1992
`
`jJPJ
`
`Ja(Xln .................................... 4..{)16266
`
`[5[[
`....................................................... G09G 3/36
`Int. Cl.'
`[52[ U.S. Cl. ............................................... 345/94; 345/208
`[58[ Field of Search ................................ 345/1 00,89,90,
`345/94,95, 208, 99, 204, 87; 359/54
`
`[56 [
`
`References C ited
`
`U.S. ['ArENT DOCUMENTS
`
`4,724,433
`4,785,297
`4,842,371
`5,041,822
`
`2/1988 Inoue el al. ............................... 345187
`11/1988 Sckiya ..................................... 340n84
`6/1989 Yasuda ct al. .......................... 340n84
`811991 Hayashi .................................. 340n84
`
`5,253,091
`
`1O{1993 Kimura et al.
`
`345{87
`
`FOREIGN PArENT DOCUMENTS
`
`0466 378 A2
`3-t63529
`3-t63530
`3-t63531
`2 146478
`
`1/1992 European !'at. Off ..
`7/1991
`Ja(Xln.
`7/1991
`Jar,an.
`7/1991
`Japan.
`4/1985 United Kingdom .
`
`OTHER PU BLI CAnONS
`
`Pate nl Abstracts of Japan, vol. 14, No. 580 (E-1 017) Dec.
`25,1990 & 1p- A-02 252 378 (SONY) Oc\. II, 1990 (pp.
`501 -507).
`Japan Display '89, Emoto et al: 0.92 in. Active- Matrix LCD
`With Fully Integrated Po ly-Si TFT Drivers of New Circuit
`Configuration, pp. 152- 154.
`
`Primary Examiner-Regina Liang
`Anomey, Agenf, or Firm-Nixon & Vandcrhye, p.e.
`1571
`To enhance the display quality by improving the writing
`characteristic of active matrix display device.
`
`ABSTRACT
`
`A plunlity of signallincs of video signals are provided for
`pixels of each column arranged in two-dimensional array,
`and the driving element of each pixel is designed to be
`driven by anyone oltbe sigoallines, so that the scanning
`time of each line may be extended longer than one hori7.ontal
`scanning peri<xl.
`
`13 C laims, 8 Drawing Sheets
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`SHARP EXHIBIT 1003
`Page 1 of 13
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`

`

`U.S. Patent
`
`J UII. 27, 2000
`
`Sheet 1 of 8
`
`6,081,250
`
`Fi 9 . 1 (Prior Art)
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`Page 2 of 13
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`U.S. Patent
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`JUII. 27, 201M)
`
`Sheet 2 of 8
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`6,081,250
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`Fi g. 2 (Prior Art)
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`Page 3 of 13
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`U.S. Patent
`
`.Jun. 27, 201M)
`
`Sheet 3 of 8
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`6,081,250
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`Fi g. 3 (Prior Art)
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`Page 4 of 13
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`

`U.S. Patent
`
`JUII. 27, 2000
`
`Sheet 4 of 8
`
`6,081,250
`
`Fig.4
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`Page 5 of 13
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`

`

`U.S. Patent
`
`J UII. 27, 2000
`
`Sheet 5 of 8
`
`6,081,250
`
`Fig.S
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`Page 6 of 13
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`U.S. Patent
`
`JUII. 27, 201M)
`
`Sheet 6 of 8
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`6,081,250
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`Page 7 of 13
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`

`

`U.S. Patent
`
`Jun, 27, 2(KIO
`
`Sheet 7 of 8
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`6,081,250
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`Page 9 of 13
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`

`

`1
`ACTI VE MATRIX I>ISI'LAY DEVICE AN D
`ITS IlRIV ING 1\0 :1'HOI>
`
`6,081 ,250
`
`5
`
`"
`
`20
`
`-
`
`This is a continuation of application Ser. No. OSf(X)9,115.
`fi led Jan. 26, 1993, now abandoned .
`BACKGROUND OF HIE INVENTION
`l. Field of the Invention
`"' be present invention rclales to an active malri", display
`device used in liquid crystal display device and the like, and
`ils driving method.
`2. Iksc riplion o f the Related Art
`FIG. 1 soows an cnmplc o f construction of active matrix
`liquid c rys tal display device having pixels o f n rows and m
`columns in the prior art. A basic constitution of such prior art
`is d isclosed, for example, in pages 152-1 54 of JAPAN
`DIS PLAY '89. In the prior arl shown in FIG. I , additional
`capacitances arc connected in parallel with the pixel
`(electrically equ ivalent 10 capacitance). In the drawing,
`numcral 603 is a switching e1cmem composed of a thin film
`traru;istor (hereinafter called 11;""1), which is turned on o r ofr
`by a gatc signal scnt from a gate driving c ircuit 609 through
`a gate bus line 601 , Numeral 608 denotes a source driving
`circu it, which is composed o f analog switches 610 for
`sampling video signals sent from a video sj"nallioc 612 and
`writing into source bus line capacities 607, and a shift
`regis te r 613 for sending the sampling control signal to gate
`electrode 611 of the analog switch.
`A video signal supplied to Ihe source bus lioc 602 through
`the ~urce driving circuit 608 is wriuen into a pixel 606, JO
`whic h is equivalent to the capacitance being composed of a
`liqu.id crystal held between a pixel electrode disposed on
`each pixcl and a coun ter electrode on a counter substrate,
`and into an additional capacitance 605 for compensating the
`capudtance of the pixel being connected in parallel with 35
`pixcl 606 when the potential of the gate pulse line 601
`becomes high and thc pixel "IF r 603 is turned off.
`One terminal of this additional capacitance 605 is con(cid:173)
`nected to the pixel clectrode, and the other is connected to
`a groumk:d additional capacitance line 604. The written 40
`signal is held in the O FF state of the TFT 603, but by
`install ing tbe add itional c apacitance 605, the holding char(cid:173)
`acte rist ic of this signal may bc improvcd, or thc fluctuation s
`of c haracteristics due to anisotropy o f dielectric constant of
`thc liquid c rystal may be alleviated.
`FIG . 2 and FIG. 3 s how cxamples of driving wavcforms
`of conventional active matrix liquid crystal display device.
`FIG . 2 dcpicts signal waveforms delivered fro m the gate
`driving circuit 609 into individual gate bus lincs X"
`X:: • - - X" during one fi eld, 'Ibe signal " 1-1" corresponds to 50
`the ON state o f the pixel TFT 603, and ""L" to the OFF state.
`l bus, in the sequence of the gatc bus lines XI' Xz - - - X ...
`the s ignal "" U" is issucd , and the pulse width of the output is
`nearly equal to the horizontal scanning time (known as
`""1 1-1" ). In this period of "" 11-1", for on/off control o f the 55
`analog switch 610 in the source driving circuit 608. control
`signals having the waveform as shown in FIG. 3 are applied
`to the gate electrode of each analog switch 610.
`'Ibe diagram shows the waveform when the i-th and
`i+l · th gate bus lines X,~ Xi. " are ON, as is s imilar in other 60
`C3SC.S. In this examplc, incidcntally, the timing o f change o f
`the potcntial o f the i-th gate bus line Xi from ""1-1 " to " 1."
`coincides with the timing of changc of the potcntial of the
`(i+ l )-th gate bus line Xi. ' from ""L" to "" 1-1 ". In this period of
`I H, the m analog switches 610 arc sequentially turned on, 65
`and thc video s ignals arc wrillen into the source bus lines
`602.
`
`2
`A finite time II must be provided from tbe moment of the
`previous stage gate bus line XI . I becoming L until the first
`analogswitch 61 0 ~ .. turned on by the control signal Y ,. "ibis
`is because the resistance of the gate bus line 601 is finite and
`the po tenlia l change is delayed . "' b at is, if a video signal is
`wrincn in the source bus line 602 by turning on the analog
`switc h 610 by control signal Y I before the previous stage
`gate bus line X'_ I becomes sufficiently " 1.", s ince the
`resistance of the pixel T FT 603 connected to the previous
`to s tage gate bus line Xi_ , is not sufficiently increased. the
`s igna l wriuen in the previous stage pixel 606 may be
`d istu rbed by the vidco signal t'OITCsponding to the pixel 606
`of this stage.
`As a rcsult. the display of the previous stage pixel is a
`mixture of the video s ignal for the previous stage and the
`video sig nal for the next stage, and the resolution is lowered.
`"lbercfore, the time t1 should be sct sufficiently long in order
`to decrease thc effect of delay time of the galc bus linc 601.
`Likewise, a finitc time t2 must be provided fro m the moment
`of turning on thc tinal a nalog switch 610 by control signal
`Y ... untilthc potential o[ the gate bus line 601 is lowered to
`··L". "Ibis is because a (illitc time is required for writing
`signals into the pixel 606 and additional capacitance 60S
`through the pixel TFT 603, and discharging the wrinen
`charge through the additional capacitance wiring 604, and
`the video signal cannot be sufficient ly writtcn into the pixel
`606 unless a sufficiently long time is laken.
`It was thus a fea ture o f the conventional active matrix
`liquid crystal display device that only one source bus line
`602 w as oonnected to each pixel 606, In the driving method
`o f the oonventional active matrix display device, it was a
`featu re that the ON time of each gate bus line 601 did not
`exceed the horizontal scanning time,
`In the conventional activc matrix type liqu id crystal
`display device, the greater the number o f pixels, the higher
`becomes the resolution, and a favorable display quality may
`be obtained. However, as the number of pixels increases,
`scveralteehnica l problems occur. For example, delays o f the
`gate bus line and add itio nal capacitance common line arc
`noted . "n1C line resistance and additional capacitance arc
`both pTOportionalto the number of pixels in the horizontal
`direct ion. "nlcrefore, the time constant of delay o f these lines
`is ncarly propo rtional to the square of the num ber of pixels
`in the horizontal di rection. l ienee, as the number of pixels
`increases, the li ne delay increases noticeably. Accordingly,
`thc times tl , I2 must be extended.
`In the display device having a great number of pixels,
`however, the hori wntal scanning time becomes shorter. As
`a result , s ufficie ntly long duration cannot be taken for times
`t l , t2 in order to decrease the effcct o f delay, which results
`in an increase o f the effect o f delay. Whe n such effect of line
`delay increases, deterioration o f display quality or the like
`may occur at one end o f the screen. It is hitherto very
`d il1icult to improve the resolution without sacrific ing the
`d isplay quality. Besides, along w ith the increase o f the
`number of pixels, the signal writing time for one pillel
`bcl'Omcs shon er in proportion. Hence, it is also a problem
`Ihal a faster writing speed of signal is req uired.
`"Ibe prescnt inventors have previously disclosed some
`improved inventions in the .Japanese Palent Puhliealio ns No_
`163529/199 1 and No . .1 63530/1991, with the purpose of
`reducing thc effect of signal de lay on display quality. In
`thesc inventions, by lowering the resistance o f the additional
`capacita nce line , the s ig nal writing speed is cnhanced.
`It is similarly an object oflhe prCSCnl invcnlio n to reducc
`thc eU'cct of signal delay o n display q ual ity. In the invention,
`
`"
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`45
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`Page 100113
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`

`3
`however, Ihis object is achieved by completely differenl
`means for substantially extending the wriling timc.
`"10 achieve the above object, the invention presents an
`active matrix display device comprising pixels in [WO(cid:173)
`dimensional arrangement, and having each pixel provided
`with a driving e!cmcOI for driving the pixel, wherein a
`plurality of signal lines for fceding signals to driving cle(cid:173)
`ments of pixels in each column arc formed 31 each column,
`so that the successive rows of driving clements of Ihe pixels
`in a column arc connected 10 and succc~ive ones driven by 10
`any the plurality of signal lines.
`[n the invention, the pixel driving element of each row is
`arranged to be driven by a column signal from a signal linc
`([ilferent from the driving clement of the adjaccnt row.
`
`Also in the invention, thc pixel driving elemcnt in each "
`
`row comprises means for successively generating signals
`and for supplying the signals to the pixel driving element of
`each row to make active during the scanning time which is
`a product of one horizontal seanning time and a number of
`signal lines formed in each column.
`[n the invention, the pixel driving elements are con(cid:173)
`structed as thin mm transistors. In the invention, the signal
`provided for each column driving element is kept by capac(cid:173)
`ity of signal line for the moment.
`lbe invention also presents a driving mcthod of an active
`matrix display device for driving a matrix display device,
`which is composed of pixels in two-dimcnsional
`arrangement, and driving elements disposed at each pixel for
`driv illl!, by Ilu;alls o f Sl.:h;l:tioll sil!,llal for liildJ row alld vidlio
`signal for each row wherein
`a plurality of signal lines for feeding signals to driving
`elements of pixels in each column are formed, and the
`successive rows of driving elements of pixels in a
`column arc connected to and driven by successive ones 35
`of the plurality signal lines. so that the scanning time of
`the selection signal, when the driving element for
`driving pixels of each row is active, may be a product
`of one horizontal scanning time and a number of signal
`lines formed in each column.
`In the invention, the driving elements of pixels of each
`column are constructed so that the driving clement of pixels
`of each adjacent row may be driven by a video signal from
`a different signal line.
`Also in the invention, the driving clements of pixels of 45
`each row are provided wilh a selection signal sequentially
`for making active o nly during the scanning time, while
`deviating the section signal by a predetermined time.
`[n the invenlion, moreover, the driving elements of pixels
`of each row are provided with a video signal through one of 50
`the signal lines forming in a plurality at each column, after
`each row is made active by a selection signal and before the
`next row is made active by a selection signal.
`According to the above constitution, if ON signals are
`simultaneously sent to a plurality of adjacent gate bus lines, 55
`video signals to be wrinen into adjacent pixels across gate
`bus lines will nO! be mixed mutually. ·lberefore, the output
`width of the ON signal sent out to each gate bus line may be
`set longer than the time assigned for one gate bus line. As a
`result, the time for decreasing the delay effect of signal line 50
`may be extended, and the effect of line delay may be
`decreased if the number of pixels is increased, so that the
`display quality may be enhanced.
`·Ibe invention is thus constructed so that the sum tl +t2+t3
`can be extended to 211 and so forth, where the time tl is from 65
`the moment when the gate bus line becomes high until
`read ing ofvidco signal to the fin;t source bus line begins, the
`
`6,081,250
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`4
`time 12 is from Ihe moment when the video signal is read out
`to the final source bus line until the output of the gate bus
`line falls, and the time t3 is required to read out the video
`signal for pixel array if one row. In the conventional driving
`wave fonn, the sum is one horizontal time ( Ill). ·[berefore,
`the duration of tl, t2, t3 can be extended, and the clIect of
`the line delay is lessened accordingly, 50 it is possible to
`present a display device, which is excellent in writing
`characteristic; of the pixel transistor.
`
`BRI EF DESCRJI>11 0N OF T HE DRAWINGS
`Ot her and further objects, features, and advantages of the
`invenlion will be more explicit from the following detailed
`description taken with reference to the drawings wherein:
`FIG. I is a structural diagram of a prior art.
`FIG . 2 is an operatioll explanatory diagram of FIG. I.
`FIG . 3 is an operatioll explanatory diagram of FIG. I.
`FIG. 4 is a structural diagram of an embodiment of the
`20 illvention.
`FIG . 5 is an operatioll explanatory diagram of FIG. 4.
`FIG . 6 is an operatioll explanatory diagram of FIG. 4.
`FIG. 7 is a plan structural diagram Showing a practical
`constitutioll of essential par! of FIG. 4. and
`FIG. R is a sectional view from line A- A· of FIG. 7.
`DETAILED DESCRIPTION OF nlE
`PREFERRED EMBODIMENT
`Now referring to the drawing, preferred emlxldiments of
`30 the invention are described below.
`FIG. 4 shows an exa mple of circuit construction of an
`active matrix display device accordillg to Ihe invention. FIG.
`7 further shows an example of layout for T Vr array part of
`this active matrix display device. lIerei.n, numeral 101
`denoles a gate bus line, which is connected to a gate
`electrode 100G of a pixel TVI' \03 composed of two TF I\
`connected in series. Numeral 109 is a gate driving circuit,
`which sends out an Oil/off signal for the pixel TF r 103 to the
`40 gale bus line 101.
`Numeral 108 is a source driving circuit, which i~ com(cid:173)
`posed of analog switches 110a, 1I0b interposed between a
`video signal line 112 and source bus lines 102a, 102b, and
`a driving circuit 113 for sending out the on/off control
`sigllals of the analog switches 110a, 110b to the gate
`electrodes of the analog switches llOa, l1Ob. ·[be video
`signal is sent out to the source bus lines 102a, 102b through
`the source drivillg circuit 108 at adequate liming, wrinen
`into capacitances l07a, 107b of the 107b of the source bus
`lines, and further wrinen into a specific pixel through the
`pixel 1FT 103 ill ON state.
`The written video signal is written, in the OFF state of the
`pixel TF r 103, into a Ilixel 106 which is C{Juivalent to a
`capacitance formed with a liquid crystal held between a
`pixel electrode 116 and a counter electrode and into an
`additional capacitallce 105 collnected in parallel with the
`pixel. One electrode 105..1" of the additional capacitance lOS
`is connected to all additional capacitance common line 104,
`and is grounded. In one pixel array, a pair of source bus line~
`102a, 102b are disposed, which are connected alternately on
`every Olher row to sourcc electrodes I03Sa, 103Sb of the
`pixel T FT 103 through contact holes 11 4<1, 114b, respec(cid:173)
`tively as showll ill FIG. 7.
`Adrain electrode 103!) of the pixel TVr \03 is connected
`to the other electrode \05y of the additional capacitance lOS
`and to a pixel electrode 116 through cOll!act holes liSa,
`IISb as shown in FIG. 7.
`
`Page 11 of 13
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`6,081,250
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`A sectional structure along line A_A' of FIG. 7 is shown
`in riG. 8. On J
`transparent insulating, substrate 121 , a
`polycrYSlalline silicon film 122 serving as a channel portion
`10le of the TFT 103 and the olher elcctrode I05y of the
`additional capacitance 105, a gale insulation film 123, and a
`polycrystal line silicon film 124 doped with impurities
`serving as the gate electrode I03G of Ihe TFT 103 and [he
`o ne elcctrode lOS.\' of the additional capacitance 105 arc
`formed in this order. In specified part S of Ihe polycrystalline
`impurities are doped by ion implantation [0
`silicon fllm,
`method. An insulating film 125 is formed in Ihe upper part
`of the polycrystalline silicon film 124, and Ihe contact holc
`115[1 is opened, and lhe pixel electrode 116 is formed by
`wiring such as source bus line of low re~ista nce metal like
`as AI, and transparent conductive thin film like as riD.
`FIG.5 and FIG. 6 show driving waveforms in the embodi(cid:173)
`men\. FIG. 5 shows the s ignal waveform in one vertical
`scanning period (one field) scnt out to gate bus lines Xl
`through X"' When the potential to each gate bus lines Xl X"
`becomes "11" level, the transistors the gate electrodes to 20
`which the gate bus lines X 1 to X" are connected, are turned
`o n at the same time. In each gate bus line, the ON signal is
`SCnt out for the double duration of One horizontal scanning
`period (11-1). 'nle gate bus lines X, to X" send ou t signals at
`the timing shifted by the time o f 11-1 sequentially a~ shown 25
`in FIG. 5, and the output pulscsofadjacent gate bus lines are
`overlapped by the duration of lB.
`l~lG. 6 shows the de tail abou t driving waveform in two
`horizontal scanning periods (211). In the drawing. X; and
`X; .. , are driving wavefo rms of the i-th and (i+ I)-h gate bus 30
`lines respectively. Additionally Y " Y" J' Y : , Y':, to Y m' Y 'm
`are gate signals to be fet! iOlo gate electrodes of the analog
`swilChes 1I0a, b respectively, and when the gate signal
`hecnme<; "H", the corresponding analog switches liOn, "are
`turned on, and the video signal sent from the video signal 35
`line 112 is written into specific source bus lines lOla, b, and
`the video signal is further written into Ihe specific pixel
`through the pixel TFr 103 in ON state.
`[n this embodiment, lirst the gate bus line X; becomes 40
`" 11", and t [ time later the gate signal Y " o f the analog switch
`110a becomes " ['1", and the video signa] is wrinen in the
`is scnt out on the
`corresponding source bus line, " ],1"
`previous stage gate bus line X;_J ' However, since the source
`bus [inc corresponding to the gate signal Y I is not connected 45
`to the 'IFr connected to the gate bus line X;_I' a mixture of
`video signal does not occur because of the difference in the
`pulse width of the gate bus line.
`[n the embodiment, by installing two source bus [ines for
`o ne pixel column, the pulse width of each gate bus line is set 50
`twice as long as one horizontal scanning period for driving
`in the state free from mixture of video signals but the ellect
`of the embodiment is nOl limited to this case alone, and when
`more source bus lines are provided, the Qutput pu[sc width
`of the gate bus line may be set as many times as the number 55
`of source bus lines pcr pixel column in one hori7.0ntal
`scanning period.
`Further in the embodiment, the writing time of video
`signal may be e xtended. By o nce converting the incoming
`video signal into a digital signal, storing the digital s ignal
`into a memory and oonverting the Slored signal inlO an
`analog signal again at specillc timing, the writing time of the
`video signal for each pixel may be extende d. As a result, the
`required characteristic of the analog switch may be
`alleviated, and the writing characteristic of the video signal 65
`is fu rthcr enhanced, so that the display quality may be morc
`improved.
`
`6
`'Ilie invention may be embodied in othe r specific fonns
`without departing from the spirit or essential characteristics
`thereof. The prescnt embodiments are therefore to he oon(cid:173)
`sidered in all respects a<; illustrative and nOl restrictive, the
`soope of the invention being indicated by the appended
`claims rather than by the foregoing description and all
`changes which oome within the meaning and the range of
`equivalency of the claims are therefore intended to be
`embraced therein.
`What is claimed is:
`L An active matrix display device comprising:
`a plurality of pixels arranged tWO-dimensionally in col(cid:173)
`umns and rows,
`a plurality of driving clements wherein a driving element
`is provided for each pixel to drive the pixel, and
`wherein a group of signal lines for fceding signals to
`t he driving clements are provided for each column of
`pixcls and each driving clement of a column is oon(cid:173)
`nected to a se\ccted one of said group, so that the
`driving elements of each adjacent pixel in a column are
`driven by a different selected one of the s ignal lines
`from said group of signal lines and the driving elements
`provided for each row of pixels are connected to the
`$l.me selected o ne in each group o f signal lines pro(cid:173)
`vided for each column of pixels,
`a plurality of gating signal lines wherein each of the
`gating signal lines is connected to the driving elements
`of a single row of pixels so that each gating signal line
`provides an ON state gating signa l to thc driving
`clements of a different respective row of pixels, and
`wherein the time necessary to fced the s ignals from said
`group of signal lines for each columo to each driving
`clement of a row of pixels is substantially less than an
`ON state gating signal time of said row of pixels.
`2. An active matrix display dcvice as in claim 1, further
`comprising means for successively genera.ting and supply(cid:173)
`ing tbe ON state gating signals to the pixel driving elements
`of each row for successively driving each row for a time
`which is a product of the time necessary to feed the signals
`from said group of signal lines to each driving element of a
`row of pixels and the number of signal lines in said group for
`each column.
`3. An active matrix d isplay device as in claim I, wherein
`the pixel driving elemeot is a thin film tra nsistor.
`4. An active matrix d isplay device as in claim I, wherein
`the signal provided for each column driving element is
`temporarily capacitively stored by capacito r means for each
`signal line.
`.5. An active matrix display device as in claim I wherein
`the time necessary to feed thc signals from the group of
`signal lines for each column to the driving c lements of a row
`of pixels is substantially one half the ON state gating signal
`time.
`6. An active matrix display device as in claim I wherein
`the device pixels arc driven in a oonintcrlaced scanning
`mode.
`7. A driving met hod of an active matrix display device,
`which is composed of pixels in a two-dimensional arrange-
`60 ment of columns and rows with a driving element disposed
`at each pixel, for driving by means of a sclection signal for
`each row and video signals for each column, said method
`comprising:
`fonning a plurality o f signal lines in each column for
`feeding signals to the driving elements of pixels in each
`column, and driving the driving clement of each pixel
`of a column by a selected one of the signal lines, so that
`
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`6,081,250
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`7
`the driving clements of each adjacent pixel in a column
`is driven by a different ~lecteJ one of the plurality of
`signal lines,
`fonning a plurality of row selection lines whercln each
`row selection line provides a row selection signal [0 a
`single row of driving elements and generating row
`selection signals so that the lime thai a row selection
`signal for each row of driving clements is active is
`substantially greater than the time necessary \0 provide
`said video signals for each column [0 the driving 10
`clements of a row and wherein the driving clements
`provided for each row of pixels are connected [0 [he
`same SClct1cU one in each group of signal lines pro(cid:173)
`vided for each co lumn of pixels.
`8. Adriving method of an active matrix display device as 15
`in claim 7, further comprising: sequeniially providing the
`driving clements of pixels of each row with an active row
`selection signal for sequentially making said rows active and
`shifl ing the active time of a row selection signal for each
`sequential row for a predetermined time.
`9. Adriving method of an active matrix display device as
`in claim I!I, wherein the driving elements of pixels of each
`
`8
`row are provided with a video signal through one of the
`plura.! signal lines formed in eaeh column, after each row is
`made active by a selection signal and before the next row is
`made active by a selection signal.
`10. A driving method of an active matrix display device
`as in claim 7, wherein the signal provided for each column
`driving clement by each signal line is temporarily eapaci(cid:173)
`tively stored.
`1I . A driving method as in claim 7 wherein the time that
`a row selection signal is active is substantially twice the time
`necessary to provide the video signals for each column to the
`driving clemenis of a row.
`12 . A driving method as in claim 7 wherein the device
`pixels are driven in a non interlaced mode.
`13. A driving method as in claim 7 wherein the time that
`a row selection signal is active is a product of the time
`necessary \0 provide said video signals for each column to
`the driving elements of a row and the number of the plurality
`20 of lines formed in each column.
`• •
`
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