IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`SAMSUNG ELECTRONICS CO., LTD.; SAMSUNG DISPLAY CO., LTD; SONY
`CORPORATION
`Petitioners,
`
`v.
`
`SURPASS TECH INNOVATION LLC
`Patent Owner.
`
`Case No. To Be Assigned
`Patent No. 7,420,550
`
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO. 7,420,550
`UNDER 35 U.S.C. §§ 311-319 AND 37 C.F.R. § 42.100 et seq.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
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`

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`Docket No. 031179.0133-US01
`
`TABLE OF CONTENTS
`
`I.
`
`MANDATORY NOTICES (37 C.F.R. §42.8(a)(1)) ...................................... 1
`A.
`Real Party-In-Interest (37 C.F.R. §42.8(b)(1)) .................................... 1
`B.
`Related Matters (37 C.F.R. §42.8(b)(2)) .............................................. 1
`C.
`Lead and Backup Counsel (37 C.F.R. §42.8(b)(3)) ............................. 2
`D.
`Service Information (37 C.F.R. §42.8(b)(4)) ....................................... 2
`FEES (37 C.F.R. §42.103) .............................................................................. 2
`II.
`III. REQUIREMENTS FOR INTER PARTES REVIEW UNDER 37
`C.F.R. § 42.104 ............................................................................................... 3
`A. Grounds for Standing (37 C.F.R. §42.104(a)) ..................................... 3
`B.
`Citation of Prior Art ............................................................................. 3
`C.
`Claims and Statutory Grounds (37 C.F.R. §§42.104(b)(1) &
`(b)(2)) ................................................................................................... 4
`IV. SUMMARY OF THE ‘550 PATENT ............................................................ 5
`A. Overview of the ‘550 Patent ................................................................. 5
`1.
`The Admitted Prior Art .............................................................. 5
`2.
`The Alleged Invention of The ’550 Patent ................................ 6
`Prosecution History Summary of the ‘550 Patent ................................ 9
`Person of Ordinary Skill in the Art .................................................... 10
`Claim Construction (37 C.F.R. §42.104(b)(3)) .................................. 10
`1.
`“the gate drivers” and “the source drivers” ............................. 11
`2.
`“The first and the second date lines of the first group of
`date lines” ................................................................................. 14
`“Gate lines…insulated with each other” and “data lines . .
`. insulated with each other” ...................................................... 14
`“a space between the neighboring data lines” ......................... 15
`4.
`Unpatentability of the Construed Claims (37 C.F.R.
`§42.104(b)(4)) .................................................................................... 17
`Supporting Evidence (37 C.F.R. §42.104(b)(5)) ............................... 17
`
`B.
`C.
`D.
`
`3.
`
`E.
`
`F.
`
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`Docket No. 031179.0133-US01
`
`2.
`
`3.
`
`4.
`
`V.
`
`THERE IS A REASONABLE LIKELIHOOD THAT PETITIONERS
`WILL PREVAIL WITH RESPECT TO AT LEAST ONE CLAIM OF
`THE ‘550 PATENT ...................................................................................... 18
`A.
`Prior Art .............................................................................................. 18
`U.S. Patent Appl. Pub. No. 2002/0186190 to Janssen et
`1.
`al. (“Janssen ’190”) (Ex. 1003)................................................ 18
`PCT Publication WO 02/075708 A2 to Janssen et al.
`(“Janssen ’708”) (Ex. 1004) ..................................................... 21
`Japanese Patent Application Publication No. 2-214818 by
`Horii et al. (“Horii”) (Exs. 1006 & 1007)................................ 25
`U.S. Patent No. 6,300,927 to Kubota et al. (“Kubota”)
`(Ex. 1005) ................................................................................. 27
`Ground I: Claim 1 is invalid under 35 U.S.C. §103(a) as
`obvious over Janssen ’190 .................................................................. 30
`Explanation of the Obviousness Grounds II-VII ............................... 33
`C.
`D. Ground II: Claims 1-3 are invalid under 35 U.S.C. §103(a) as
`obvious over Janssen ’708 in view of Janssen ’190 ........................... 33
`Ground III: Claims 1-3 are invalid under 35 U.S.C. §103(a) as
`obvious over Janssen ‘708 in view of Horii ....................................... 41
`Ground IV: Claims 1-3 are invalid under 35 U.S.C. §103(a) as
`obvious over Janssen ‘708 in view of the Admitted Prior Art ........... 50
`G. Grounds V, VI and VII: Claims 4-5 are invalid under 35 U.S.C.
`§103(a) as obvious over Janssen ‘708 in combination with
`Janssen ‘190, Horii or the APA, and further in view of Kubota ........ 57
`VI. CONCLUSION ............................................................................................. 60
`
`B.
`
`E.
`
`F.
`
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`Docket No. 031179.0133-US01
`
`LIST OF EXHIBITS
`
`Description
`U.S. Patent No. 7,420,550
`File History for U.S. Patent No. 7,420,550
`U.S. Patent Application Publication No. 2002/0186190 to Janssen
`et al. (“Janssen ‘190”)
`Published PCT Application WO 02/075708 A2, Publication Date
`September 26, 2002, to Janssen et al. (“Janssen ‘708”)
`U.S. Patent No. 6,300,927 to Kubota et al. (“Kubota”)
`Japanese Patent Application Publication No. 2-214818 by Horii et
`al., Publication Date August 27, 1990
`Certified English translation of Japanese Patent Application
`Publication No. 2-214818 by Horii et al. (“Horii”)
`A. Lewis, et al., “Polysilicon TFT Circuit Design and
`Performance,” IEEE Journal of Solid-State Circuits, Vol. 27, No.
`12 (December 1992), pp.1833-1842 (“Lewis”)
`Surpass Tech Innovation LLC’s Preliminary Response filed in
`IPR2015-00022, Paper No. 8, Jan. 15, 2015 (“Response”)
`R. Joshi, “Chip on glass-interconnect for row/column driver
`packaging,” Microelectronics Journal 29 (1998), pp.343-349
`(“Joshi”)
`T. N. Ruckmongathan, “Driving matrix liquid crystal displays”,
`Pramana Journal of Physics, Vol. 53, No. 1 (July 1999), pp.199-
`212 (“Ruckmongathan”)
`Brown, ed., Electronics and Computer Acronyms, Butterworths
`(1988), pp. 244-45 (“Brown”)
`Declaration of Tsu-Jae King Liu, Ph. D.
`Curriculum vitae of Tsu-Jae King Liu, Ph. D.
`Roy, Physics of Semiconductor Devices, 2d ed., Universities Press
`(2004), p. 334 (“Roy”)
`
`Exhibit
`Ex. 1001
`Ex. 1002
`Ex. 1003
`
`Ex. 1004
`
`Ex. 1005
`Ex. 1006
`
`Ex. 1007
`
`Ex. 1008
`
`Ex. 1009
`
`Ex. 1010
`
`Ex. 1011
`
`Ex. 1012
`
`Ex. 1013
`Ex. 1014
`Ex. 1015
`
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`Docket No. 031179.0133-US01
`
`I. MANDATORY NOTICES (37 C.F.R. §42.8(a)(1))
`Petitioners are Samsung Electronics Co., Ltd., Samsung Display Co., Ltd.,
`
`and Sony Corporation (“Petitioners”).
`
`A. Real Party-In-Interest (37 C.F.R. §42.8(b)(1))
`The real parties in interest for this petition for Inter Partes Review are
`
`Samsung Electronics Co., Ltd.; Samsung Display Co., Ltd.; Samsung Electronics
`
`America, Inc.; Sony Corporation; Sony Electronics Inc.; and Sony Corporation of
`
`America.
`
`B. Related Matters (37 C.F.R. §42.8(b)(2))
`U.S. Patent No. 7,420,550 (“the ‘550 Patent”; Ex. 1001) is currently the
`
`subject of litigation against multiple defendants in the District of Delaware, captioned
`
`Surpass Tech Innovation LLC v. Samsung Display Co., Ltd. et al. (Civil Action No.
`
`1:14-cv-00337-LPS) and Surpass Tech Innovation LLC v. Sharp Corporation et al.
`
`(Civil Action No. 1:14-cv-00338-LPS). Other defendants in the litigation include
`
`Sharp Corporation; Sharp Electronics Corporation; Sharp Electronics Manufacturing
`
`Company of America, Inc.; Vizio, Inc. (DE Corp.) and Vizio, Inc. (CA Corp.). The
`
`litigation has been stayed in view of IPR2015-00022, filed on October 3, 2014, by
`
`the Sharp litigation defendants. The Patent Owner Preliminary Response was filed on
`
`January 15, 2015. (Ex. 1009) and the petition was denied March 10, 2015 in Paper
`
`No. 9.
`
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`Docket No. 031179.0133-US01
`
`C. Lead and Backup Counsel (37 C.F.R. §42.8(b)(3))
`Petitioners
`designate
`Jay
`I. Alexander
`(Reg. No.
`
`32,678;
`
`jalexander@cov.com) as lead counsel and Andrea G. Reister (Reg. No. 36,253;
`
`areister@cov.com) and Gregory S. Discher (Reg. No. 42,488; gdischer@cov.com)
`
`as back-up counsel, all of Covington & Burling LLP, One CityCenter, 850 Tenth
`
`Street, NW, Washington, DC 20001 (postal and hand delivery), telephone: 202-
`
`662-6000; facsimile: 202-662-6291. Petitioners further designate Michelle
`
`Carniaux (Reg. No. 36,098), Lewis Popovski (Reg. No. 37,423) and Aaron Zakem
`
`(Reg. No. 72,521) as additional back-up counsel, all of Kenyon & Kenyon LLP,
`
`One Broadway, New York, NY 10004.
`
`Service Information (37 C.F.R. §42.8(b)(4))
`
`D.
`Service information for lead and back-up counsel is provided in the
`
`designation of lead and back-up counsel above.
`
`II.
`
`FEES (37 C.F.R. §42.103)
`The undersigned authorizes the Office to charge $23,000 ($9,000 request fee
`
`and $14,000 post-institution fee) to Deposit Account No. 50-0740 for the fees set
`
`forth in 37 C.F.R. §42.15(a) for this Petition for Inter Partes Review. The
`
`undersigned further authorizes payment for any additional fees that might be due in
`
`connection with this Petition to be charged to the above-referenced Deposit Account.
`
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`Docket No. 031179.0133-US01
`
`III. REQUIREMENTS FOR INTER PARTES REVIEW UNDER 37 C.F.R.
`§ 42.104
`A. Grounds for Standing (37 C.F.R. §42.104(a))
`Pursuant to 37 C.F.R. §42.104(a), Petitioners certify that the ‘550 Patent is
`
`available for inter partes review and that Petitioners are not barred or estopped
`
`from requesting an inter partes review challenging the ‘550 Patent on the grounds
`
`identified in the present petition.
`
`B. Citation of Prior Art
`Exhibit Reference
`
`Ex. 1003 U.S. Patent Appl. Pub. No.
`
`Availability as
`Publication
`Prior Art
`Date
`June 8, 2001 35 U.S.C.
`
`2002/0186190 to Janssen et al.
`
`§102(b)
`
`(“Janssen ’190”)
`
`Ex. 1004 Published PCT Application No. WO
`
`Sep.26, 2002 35 U.S.C.
`
`02/075708 A2 to Janssen et al.
`
`§102(b)
`
`(“Janssen ’708”)
`
`Ex. 1005 U.S. Patent No. 6,300,927 to Kubota
`
`Oct. 9, 2001
`
`35 U.S.C.
`
`et al. (“Kubota”)
`
`§102(b)
`
`Ex. 1006,
`
`Japanese Patent Application
`
`Aug. 27,
`
`35 U.S.C.
`
`Ex. 1007
`
`Publication No. 2-214818 by Horii et
`
`1990
`
`§102(b)
`
`al. and Certified English translation of
`
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`

`Exhibit Reference
`
`the same (“Horii”)
`
`Docket No. 031179.0133-US01
`
`Publication
`Date
`
`Availability as
`Prior Art
`
`
`
`C. Claims and Statutory Grounds (37 C.F.R. §§42.104(b)(1) & (b)(2))
`The relief requested by Petitioners is that Claims 1-5 of the ‘550 Patent be
`
`found unpatentable and cancelled from the ‘550 Patent on the following grounds:
`
`Ground Claims
`
`Basis
`
`I
`
`II
`
`1
`
`1-3
`
`Under 35 U.S.C. §103 as obvious over Janssen ’190
`
`Under 35 U.S.C. §103 as obvious over Janssen ’708 in view
`
`of Janssen ’190
`
`III
`
`1-3
`
`Under 35 U.S.C. §103 as obvious over Janssen ’708 in view
`
`of Horii
`
`IV
`
`1-3
`
`Under 35 U.S.C. §103 as obvious over Janssen ’708 in view
`
`of the Admitted Prior Art
`
`V
`
`4-5
`
`Under 35 U.S.C. §103 as obvious over Janssen ’708 in view
`
`of Janssen ’190 and further in view of Kubota
`
`VI
`
`4-5
`
`Under 35 U.S.C. §103 as obvious over Janssen ’708 in view
`
`of Horii and further in view of Kubota
`
`VII
`
`4-5
`
`Under 35 U.S.C. §103 as obvious over Janssen ’708 in view
`
`of the Admitted Prior Art and further in view of Kubota
`
`
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`Docket No. 031179.0133-US01
`
`IV. SUMMARY OF THE ‘550 PATENT
`A. Overview of the ‘550 Patent
`The ‘550 Patent (Ex. 1001) is entitled “Liquid Crystal Display Driving
`
`Device of Matrix Structure Type and Its Driving Method.” The patent issued on
`
`September 2, 2008 from U.S. Patent Application No. 10/929,473 (“the ‘473
`
`Application”), filed on August 31, 2004. The ‘550 Patent does not claim priority to
`
`any earlier domestic or foreign patent application. Thus, publications dated before
`
`August 31, 2004 are prior art.
`
`The claims in issue in this petition, Claims 1-5, are directed to a structure
`
`that drives a liquid crystal display (“LCD”) that includes a specific arrangement of
`
`thin film transistors (“TFTs”), gate lines, gate drivers, data lines, and data drivers
`
`in a matrix. Claims 1 and 2 are independent claims.
`
`The Admitted Prior Art
`
`1.
`The ’550 Patent describes the admitted prior art (“APA”) at length at Col.
`
`1:24-3:15 and Figs. 1-3. Figs 1A
`
`and
`
`1B
`
`are
`
`of
`
`particular
`
`significance. As seen in
`
`these figures, the prior art display
`
`panel 10 includes data lines 111
`
`(highlighted in red) and gate lines
`
`121 (highlighted in yellow) connected to the sources and the gates, respectively, of
`
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`Docket No. 031179.0133-US01
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`TFTs shown as Q1. Pixel 13 is defined as the area enclosed between two adjacent
`
`data lines 111 and two adjacent gate lines 121 and includes TFT Q1. Multiple gate
`
`drivers 12 (yellow boxes) are installed on one side of the panel 10 and provide
`
`scanning signals to the gates of the TFTs via the gate lines 121 to turn each pixel
`
`TFT on and off. Multiple source drivers 11 (red boxes) are connected on the top
`
`side of the periphery of the active matrix as viewed in the figure and provide the
`
`voltage signals to the data lines 111. (Ex. 1001, 1:36-41) The voltages on the data
`
`lines are transferred to the pixels via the TFTs which are switched on and off by
`
`the control signal from the gate driver 12 to the gate line 121 (G1 in Fig. 1B). (Id.,
`
`1:43-52) A driving voltage is thereby applied to the liquid crystal molecules
`
`corresponding to pixels 13, which each comprise a liquid crystal capacitor CLC and
`
`a storage capacitor CS, to form an image. (Id., 1:52-61, Fig. 1B)
`
`The Alleged Invention of The ’550 Patent
`
`2.
`As can be seen in Figs. 4A and 4B, the alleged invention comprises a matrix
`
`array of N rows by M columns of TFTs (denoted as “Q”) with corresponding gate
`
`drivers and source drivers just as disclosed in the APA. The alleged invention
`
`provides a second data line for each TFT column (indicated in blue) so that there
`
`are M groups (i.e., pairs) of data lines (D1 & D1ˈ, D2 & D2ˈ, … DM & DMˈ) per
`
`column. In each group of data lines, the first data line of each pair is connected
`
`with the sources of all the TFT’s on the odd rows (indicated by red dots) and the
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`Docket No. 031179.0133-US01
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`second data line of the pair is connected with the sources of all of the TFTs on the
`
`even rows (indicated by blue dots). The matrix thus includes M groups of first and
`
`second data lines that alternatingly connect the source drivers and the sources of
`
`the TFTs Q in the odd and the even rows of each column, respectively.
`
`
`
`The ’550 Patent describes that the alternating connections of the first and
`
`second data lines of the group of data lines with the respective odd and even rows
`
`of the gate lines (the “Odd/Even Alternating Connections”) result in reducing the
`
`“response time” of the liquid crystal molecules in the display. (Ex. 1001, 3:35-40,
`
`Fig. 4) However, the ’550 Patent does not provide a clear description as to how the
`
`Odd/Even Alternating Connections reduce the response time.
`
`The M groups of data lines and the N gate lines of the Odd/Even Alternating
`
`Connections are described as “insulated with each other.” (Id., 8:20-22, 29-31) As
`
`explained further below, a person of ordinary skill in the art (“POSA”) would
`
`understand this to mean that the data lines and gate lines are electrically insulated
`
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`Docket No. 031179.0133-US01
`
`from each other. The specification describes that the second data line of the first
`
`group of data lines (e.g., D1ˈ) and the first data line of the second group of data
`
`lines (e.g, D2) are “neighboring data lines,” and that there is “a space between the
`
`neighboring data lines” to prevent the data lines from short circuiting. (Id., 8:31-
`
`36) However, the ’550 Patent does not provide any specifics as to the dimensions
`
`or configuration of the space between the neighboring data lines necessary to
`
`prevent short circuits.
`
`The ’550 Patent further describes that “the first data line of each group of
`
`data lines and the neighboring second data line of another group of data lines are
`
`connected to the same source drivers”;
`
`that is, the data lines from two groups of
`
`data lines share the same source driver,
`
`and that the data transfer is switched by an
`
`electronic switch. (Id., 8:47-52) The
`
`specification also describes the electronic
`
`switch as required only when the first data
`
`line of one group and the second data line
`
`of another group (i.e., neighboring groups) share the same source driver. (Id., 8:47-
`
`52, 10:21-26, 18:7-12) However, Fig. 6A shows use of electronic switches
`
`(highlighted in brown ovals) where the first data line (D1, red) and the second data
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`Docket No. 031179.0133-US01
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`line (D1’, blue) of the same group of data lines (i.e., D1 and D1ˈ) share the same
`
`source driver.
`
` The specification contains no details as to the structure or function of the
`
`electronic switch. (Ex. 1013, ¶¶18-19) For example, it is unclear whether the
`
`electronic switch is required between the data lines of different groups sharing the
`
`same source driver as suggested by the specification or between the data lines of
`
`the same group as suggested by Fig. 6A. (Id.) Further, there is no description of the
`
`two lines (highlighted in green) that seemingly connect the electronic switches
`
`horizontally across. (Id., ¶19) The ’550 Patent also states that “the form of the gate
`
`driver can be a chip on glass or an integrated gate driver circuit on glass” without
`
`providing any further description. (Ex. 1001, 8:53-54)
`
`Prosecution History Summary of the ‘550 Patent
`
`B.
`The application from which the ’550 patent issued was originally filed with
`
`56 claims. The initial office action mailed on September 20, 2007 imposed a
`
`restriction requirement, identifying six patentably distinct species within those
`
`claims and requiring an election. (Ex. 1002, p.120-124) In response, the patentee
`
`elected to proceed with the species covered by application claims 1-8, which were
`
`said to correspond to the embodiment disclosed in Figures 4A-4C. (Id., p.127)
`
`Following the applicant’s election, the elected claims were either rejected or
`
`the subject of objections. (Id., p.138-145) The applicants amended the independent
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`Docket No. 031179.0133-US01
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`device claims to add the limitation that “the first data lines and the second data
`
`lines of each group of data lines are connected with the same source driver.” (Id.,
`
`p.151-156) A notice of allowance followed on May 16, 2008. (Id., p.162) None of
`
`the references relied upon in this Petition (i.e., Janssen ’708, Janssen ’190, Horii,
`
`and Kubota) was cited during the prosecution of the ’550 Patent.
`
`Person of Ordinary Skill in the Art
`
`C.
`A person of ordinary skill in the art of the ‘550 Patent at the time of the
`
`alleged invention (“POSA”) would have had at least an undergraduate degree in
`
`electrical engineering, or related field, at least one (1) year of education or training
`
`in semiconductor devices and integrated circuit design, and at least two (2) years of
`
`experience with active-matrix liquid crystal display (“AMLCD”) technology,
`
`including work on a project that included the eventual fabrication and testing of an
`
`AMLCD. (Ex. 1013, ¶21)
`D. Claim Construction (37 C.F.R. §42.104(b)(3))
`A claim subject to IPR is given its “broadest reasonable construction in light
`
`of the specification of the patent in which it appears.” 37 C.F.R. §42.100(b); In re
`
`Cuozzo Speed Technologies, LLC, __ F.3d __, 2015 WL 448667 at *5-6 (Fed. Cir.
`
`Feb. 4, 2015). Petitioners have included below a discussion of the “broadest
`
`reasonable construction consistent with the specification” for a number of claim
`
`terms of the ‘550 Patent.
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`Docket No. 031179.0133-US01
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`“the gate drivers” and “the source drivers”
`
`1.
`Independent Claims 1 and 2 refer to “the gate drivers” and “the source
`
`drivers.” No antecedent basis exists for “the gate drivers” or “the source drivers” in
`
`the claims. Moreover, the term “source driver” is not mentioned in the
`
`specification of the ’550 Patent, although the term “data driver” is used.
`
`Petitioners do not concede that these claims satisfy the requirements of 35
`
`U.S.C. §112, and, for purposes of this Petition only, Petitioners note that the ’550
`
`Patent describes data drivers and gate drivers as used in the APA. (Ex. 1001, 1:34-
`
`61, Figs. 1A and 1B) A POSA would understand the structure described in the
`
`APA, particularly Figs. 1A and 1B, to contain multiple gate drivers and source
`
`drivers and would understand that these features were already known in the art and
`not the novel aspect of the alleged invention of the ’550 Patent. (Ex. 1013 at ¶38)
`
`Moreover, the specification does not ascribe any particular significance to the
`
`structure, number, or location of the gate drivers or the source drivers. Therefore,
`
`using the broadest reasonable construction, a POSA would construe these terms as
`
`written in the plural form, that is, “the gate drivers” refer to more than one gate
`
`driver and “the source drivers” refer to more than one source/data driver. (Ex.
`
`1013 at ¶23)
`
`Thus, for purposes of this Petition, the broadest reasonable construction of
`
`term “the gate drivers” is that this term refers to more than one gate driver.
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`Docket No. 031179.0133-US01
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`Similarly, the term “the source drivers” is construed to refer to more than one
`
`source driver or data driver. However, as Petitioners’ expert explains, a POSA
`
`would appreciate that the use of the plural form of “gate drivers” and “source
`
`drivers” can lead to some ambiguity when comparing the prior art to the claims in
`
`light of a POSA’s understanding of this technology. (Ex. 1013, ¶¶24-32)
`
`As to the “gate drivers” limitation, a POSA would understand that one
`
`interpretation is that “gate drivers” refer to a single “gate driver” circuit that has
`
`multiple buffers, one per gate line, as was conventional in the art as of the filing
`
`date of the ‘550 Patent. (Ex. 1008, Fig. 4(a); Ex. 1013, ¶25) In this sense, each
`
`buffer is a “gate driver” because each buffer transmits the control signal to its
`
`corresponding gate line. (Id., ¶25)
`
`A second
`
`interpretation of
`
`“gate drivers” is shown in Fig. 20A
`
`of the ‘550 Patent, in which a
`
`separate “Gate driver” made up of
`
`several IC chips (highlighted
`
`in
`
`yellow boxes) is illustrated as being
`
`located on the right and left sides of
`
`the display. (Ex. 1013, ¶26)
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`Docket No. 031179.0133-US01
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`A third interpretation of the “gate drivers” limitation is that a gate driving
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`circuit can be implemented using multiple gate driver IC chips on the same side of
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`the display. (Ex. 1013, ¶27) Trying to fabricate and install on the display one large
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`IC chip to drive the gate lines numbering in the hundreds and sometimes more than
`
`one thousand lines would be prohibitively expensive. (Id.) Thus, a POSA would
`
`expect to use multiple gate driver IC chips, which is consistent with the illustration
`
`of the “Gate driver” in the APA figure (Fig. 1A) as well as the embodiments of the
`
`alleged invention (e.g., Fig. 4A). (Id.)
`
`The broadest reasonable construction of “gate drivers” therefore should
`
`encompass all three of these alternatives.
`
`Potential ambiguity also exists with respect to the claim term “source
`
`drivers.” (Ex. 1013, ¶28) A POSA would appreciate that the ’550 Patent describes
`
`the data drivers in terms of the conventional digital data architecture in use at the
`
`time the ‘550 Patent was filed. (Ex. 1008, Fig. 5(a); Ex. 1013, ¶¶29-30) In this
`
`architecture, one digital-to-analog converter (DAC) is used per data line. (Id.)
`
`Thus, a POSA would appreciate that the “source drivers” limitation in the claims
`
`refers to the multiple DACs, one per data line, that was used in the conventional
`
`digital architecture of the time. (Id.)
`
`A second interpretation of “data drivers” is that it refers to multiple data
`
`driver IC chips. As with gate drivers, a POSA would understand that due to the
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`Docket No. 031179.0133-US01
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`large number of data lines that existed in an LCD that was conventional at the time
`
`of the filing of the ‘550 Patent, multiple IC chips would have been used rather than
`
`a single large chip. (Ex. 1013, ¶¶31-32) This interpretation is consistent with the
`
`drawings of the ’550 Patent.
`
`The broadest reasonable construction of “data drivers” therefore should
`
`encompass both of these alternatives.
`
`2.
`
`“The first and the second date lines of the first group of
`date lines”
`
`Independent Claims 1 and 2 each recite that “the first and the second date
`
`lines of the first group of date lines are respectively connected with the sources of
`
`all the thin film transistors of the odd and the even rows of the first column . . . .”
`
`(Ex. 1001, 19:52-56, 20:13-17) (emphasis added). For purposes of this Petition
`
`only, Petitioners presume that the term “date lines” in the claims is a typographical
`
`error and was meant to be “data lines.” The Board agreed in its decision in
`
`IPR2015-00022 (Paper No. 9, p. 7).
`
`3.
`
`“Gate lines…insulated with each other” and “data lines . . .
`insulated with each other”
`
`Independent Claims 1 and 2 each recite “a group of N gate lines . . .
`
`insulated with each other” and “M groups of data lines . . . insulated with each
`
`other.” (Ex. 1001, 19:44-45, 51-52, 20:5-6, 12-13) (emphasis added) A POSA
`
`would recognize that “insulated with each other” includes a grammatical error and
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`Docket No. 031179.0133-US01
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`is meant to be “insulated from each other,” and that there is no electrical
`
`connection between the two lines because the lines are not in contact with each
`
`other. (Ex. 1013, ¶¶33-34) This is consistent with the descriptions of the lines
`
`being parallel to each other. Furthermore, when reading the description of gate
`
`lines and data lines being “orthogonally crossed,” a POSA would understand that
`
`due to the “insulation,” these lines are not in physical contact with each other and
`
`do not make any electrical connection. (Id.) The broadest reasonable construction
`
`of this limitation thus requires that there be no electrical connection between the
`
`lines. It does not require that the lines also be parallel as the Board found in
`
`IPR2015-00022 (Paper No. 9, p. 7).
`
`“a space between the neighboring data lines”
`
`4.
`Dependent Claim 3 recites “there is a space between the neighboring data
`
`lines to prevent them from short circuit.” (Ex. 1001, 20:30-32) (emphasis added)
`
`The specification of the ‘550 Patent provides no further explanation of what is
`
`meant by “a space between” the lines to “prevent them from short circuit.” For
`
`example, the specification does not discuss any minimum dimensions of the space
`
`necessary to prevent a short circuit and does not ascribe any particular significance
`
`to the size or shape of the space. The only instances of the specification describing
`
`the “space between the neighboring data lines to prevent them from short circuit”
`
`are by using figures and “arrangements shown” in Figs. 4C, 8C, and 22D. (Id.,
`
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`Docket No. 031179.0133-US01
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`8:31-36, 10:5-10, 17:60-64) However, a POSA looking at the figures would find it
`
`unclear what the “arrangements” are intended to show. (Ex. 1013, ¶35) Figs. 4C
`
`and 8C seem to show the data lines to be evenly spaced apart, regardless of
`
`whether the space is between two lines of the same group or two lines of the
`
`neighboring groups, whereas Fig. 22D depicts the space between the neighboring
`
`groups (e.g., D1ˈ and D2) as smaller than the space between the data lines of the
`
`same group (e.g., D1 and D1ˈ).
`
`
`In its Preliminary Response in IPR2015-00022, Patent Owner appeared to
`
`suggest that the arrangement shown on Figs. 4B
`
`and 4C where a pixel Q is arranged between the
`
`pair of data lines D1 and D1ˈ is “described in the
`
`specification as providing ‘a space … between the
`
`neighboring data lines’ to avoid the risk of short-
`
`circuiting[.]”. (Ex. 1009, p.4) However,
`
`this
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`Docket No. 031179.0133-US01
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`reading is inconsistent with the specification, which makes it clear that “the
`
`neighboring data lines” are formed between two neighboring groups of data lines,
`
`such as “for example, the second data line D1ˈ of the first group of data lines and
`
`the first data line D2 of the second group of data lines.” (Ex. 1001, 8:31-36, 8:47-
`
`50) On Fig. 4B, there is no pixel present between the neighboring data lines D1ˈ (in
`
`blue) and D2 (in red). Fig. 22D, which also purports to show the “space between
`
`the neighboring data lines” does not show pixel Q between the neighboring data
`
`lines D1ˈ (in blue) and D2 (in red), either.
`
`Thus, for purposes of this Petition only, Petitioners contend that the broadest
`
`reasonable construction of “a space between the neighboring data lines to prevent
`
`them from short circuit” is that it refers to any space sufficient to prevent two data
`
`lines from electrical communication, in other words, to prevent a short circuit.
`
`(Ex. 1013, ¶36)
`E. Unpatentability of the Construed Claims (37 C.F.R. §42.104(b)(4))
`An explanation of how Claims 1-5 of the ‘550 Patent are unpatentable under
`
`the statutory ground(s) identified above, is provided in Section V, below.
`
`Supporting Evidence (37 C.F.R. §42.104(b)(5))
`
`F.
`The exhibit numbers of the supporting evidence relied upon to support the
`
`challenge and the relevance of the evidence to the challenge raised, including
`
`identifying specific portions of the evidence that support the challenge, are
`
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`Docket No. 031179.0133-US01
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`provided below in the form of explanatory text and claim charts. An Exhibit List
`
`with the exhibit numbers and a brief description of each exhibit is set forth above.
`
`V. THERE IS A REASONABLE LIKELIHOOD THAT PETITIONERS
`WILL PREVAIL WITH RESPECT TO AT LEAST ONE CLAIM OF
`THE ‘550 PATENT
`
`The subject matter of Claims 1-5 of the ‘550 Patent is disclosed and taught
`
`in the prior art as explained below. As set forth in §V.A.-V.G., the references and
`
`combinations utilized in Grounds I-VII render obvious each of Claims 1-5 and thus
`
`provide a reasonable likelihood that the Petitioners will prevail on at least one
`
`claim. 35 U.S.C. §314(a).
`
`Prior Art
`
`A.
`Paragraphs 22-65 of the Liu Declaration, Ex. 1013, describe the state of the
`
`art regarding LCD panels and the LCD-panel driving methods used in the 2003
`
`time frame. The specific prior art applied here includes Janssen ’190 (Ex. 1003),
`
`Janssen ‘708 (Ex. 1004), Horii (original Japanese in Ex 1006, certified English
`
`translation in Ex. 1007) and Kubota (Ex. 1005).
`
`1.
`
`U.S. Patent Appl. Pub. No. 2002/0186190 to Janssen et al.
`(“Janssen ’190”) (Ex. 1003)
`
`Janssen ‘190 is a United States Published Patent Application that was
`
`published on June 8, 2001, and therefore qualifies as prior art to the ‘550 Patent
`
`under 35 U.S.C. §102(b). Janssen ‘190 was neither cited nor considered during
`
`prosecution of the ‘550 Patent.
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`Janssen ’190 discloses a multi-row addressable active matrix liquid crystal
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`Docket No. 031179.0133-US01
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`display that, by switching on or
`
`enabling
`
`multiple
`
`rows
`
`concurrently,
`
`(1)
`
`increases
`
`the
`
`available scanning transfer time
`
`required for scanning the display
`
`elements, and (2) reduces
`
`the
`
`capacitive
`
`load of
`
`the source
`
`drivers, which facilitate the source
`
`drivers
`
`to
`
`transfer
`
`the voltage
`
`signals to the LCD pixels faster,
`
`thereby
`
`improving
`
`display
`
`performance. (Ex. 1003, ¶¶1, 4-6)
`
`The second embodiment of Janssen ’190 is illustrated in Fig. 2, reproduced
`
`here with color annotations. In this embodiment, Janssen ’190 discloses an active
`
`matrix liquid crystal display device containing an M row by N column matrix array
`
`of display elements 20. Each display element represents one pixel of the panel and
`
`can be connected to an IGFETS transistor 30 or 35. (Id., ¶14) A POSA was
`
`familiar with IGFETs (insulated-gate field effect transistor) transistors in the late
`
`1990s and early 2000s and understood that a TFT is a form of IGFET transistor,
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`Docket No. 031179.0133-US01
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`(Ex. 1012, p.244; Ex. 1015, p. 334: Ex. 1013, ¶50), and that TFTs were commonly
`
`used in LCD displays before the priority date of the ‘550 Patent. ((Ex. 1003, ¶3; Ex.
`
`1008, p. 1834; Ex. 1011, p. 210;