throbber
IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`
`
`In re Inter Partes Review of:
`U.S. Patent No. 7,420,550
`
`For: LIQUID CRYSTAL DISPLAY DRIVING
`DEVICE OF MATRIX STRUCTURE
`TYPE AND ITS DRIVING METHOD
`
`
`
`DECLARATION OF TSU-JAE KING LIU, PH.D.
`
`
`
`Mail Stop PATENT BOARD
`Patent Trial and Appeal Board
`US Patent and Trademark Office
`PO Box 1450
`Alexandria, Virginia 22313-1450
`
`I, Tsu-Jae King Liu, hereby declare and state as follows:
`
`
`
`1.
`
`I have been retained as a technical consultant on behalf of Samsung
`
`Electronics Co., Ltd., Samsung Display Co., Ltd., and Sony Corporation, the
`
`petitioners in the present proceeding, and I am being compensated at my usual
`
`and customary hourly rate. The petition names Samsung Electronics Co., Ltd.;
`
`Samsung Display Co., Ltd.; Samsung Electronics America, Inc.; Sony
`
`Corporation; Sony Electronics Inc.; and Sony Corporation of America as real
`
`parties-in-interest. I have no financial interest in, or affiliation with, the
`
`petitioner, real parties-in-interest, or the patent owner, which I understand to
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`be SURPASS TECH INNOVATION LLC. My compensation is not
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`dependent upon the outcome of, or my testimony in, the present inter partes
`
`review or any litigation proceedings.
`
`2.
`
`I have reviewed each of the following:
`
`a. U.S. Patent No. 7,420,550 (“the ’550 Patent”), including the claims,
`
`description and prosecution history (which are identified in the
`
`Petition respectively as Exhibits 1001 and 1002);
`
`b. U.S. Patent Appl. Pub. No. 2002/0186190 to Janssen et al. (which is
`
`identified in the Petition as Exhibit 1003 or “Janssen ’190”);
`
`c. PCT Patent Application Publication WO 02/075708 A2 to Janssen et
`
`al. (which is identified in the Petition as Exhibit 1004 or
`
`“Janssen ’708”);
`
`d. U.S. Patent No. 6,300,927 to Kubota et al. (which is identified in the
`
`Petition as Exhibit 1005 or “Kubota”);
`
`e. Japanese Patent Application Publication No. 2-214818 by Horii et al.
`
`(the original Japanese document is identified in the Petition as Exhibit
`
`1006 and the certified English translation is identified as Exhibit 1007
`
`or “Horii”);
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`f. A. Lewis, et al., “Polysilicon TFT Circuit Design and Performance,”
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`IEEE Journal of Solid-State Circuits, Vol. 27, No. 12 (December
`
`1992), pp. 1833-1842 (which is identified as Exhibit 1008 or
`
`“Lewis”);
`
`g. Surpass Tech Innovation LLC’s Preliminary Response filed in
`
`IPR2015-00022 (which is identified as Exhibit 1009 or “Response”);
`
`h. R. Joshi, “Chip on glass-interconnect for row/column driver
`
`packaging,” Microelectronics Journal 29 (1998), pp. 343-349 (which
`
`is identified as Exhibit 1010 or “Joshi”);
`
`i. T. N. Ruckmongathan, “Driving matrix liquid crystal displays”,
`
`Pramana Journal of Physics, Vol. 53, No. 1 (July 1999), pp. 199-212
`
`(which is identified as Exhibit 1011);
`
`j. P. Brown, ed., Electronics and Computer Acronyms, Butterworths
`
`(1988), pp. 244-45 (which is identified as Exhibit 1012); and
`
`k. D. Roy, Physics of Semiconductor Devices, 2d ed., Universities Press
`
`(1992), p. 334 (which is identified as Exhibit 1015).
`
`3.
`
`I understand that the application leading to the ʼ550 Patent was Application
`
`No. 10/929,473, which was filed on August 31, 2004. For the purposes of my
`
`analysis, I assume the time of the purported invention to be August 31, 2004.
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`4. My background, qualifications, and experience relevant to the issues in this
`
`proceeding are summarized below. My curriculum vitae is Exhibit 1014.
`
`5.
`
`I am currently a Professor in the Department of Electrical Engineering and
`
`Computer Sciences in the College of Engineering at the University of
`
`California at Berkeley. I have approximately twenty-five years of experience
`
`in the broad field of integrated-circuit (“IC”) devices and technology.
`
`6.
`
`I received my B.S. and M.S. degrees in electrical engineering from Stanford
`
`University in 1984 and 1986, respectively. In 1994, I received my Ph.D. in
`
`electrical engineering from Stanford University. My Ph.D. thesis was entitled
`
`“Applications of Polycrystalline Silicon-Germanium Thin Films in Metal-
`
`Oxide Semiconductor Technologies.”
`
`7. From 1986 to 1992, I worked as a research assistant at Stanford University
`
`investigating new semiconductor materials and fabrication processes for IC
`
`applications, including high-performance thin-film transistor (“TFT”)
`
`technology. From 1992 to 1996, I conducted research at the Xerox Palo Alto
`
`Research Center on TFT technology for active-matrix liquid crystal displays
`
`(“AMLCDs”). From 1995 to 1996, I worked as a consulting assistant
`
`professor at Stanford University and advised on research on semiconductor
`
`devices and fabrication process technology. In 1995 I served as a member of
`
`the Technical Program Committee for the Second International Active Matrix
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`Liquid Crystal Display Symposium co-sponsored by the Institute of Electrical
`
`and Electronics Engineers (“IEEE”) and the Society for Information Display
`
`(“SID”).
`
`8.
`
`In 1996, I became an assistant professor in the Electrical Engineering and
`
`Computer Sciences (“EECS”) department at UC Berkeley. From 1996 to
`
`2003, as an assistant professor and later an associate professor, I conducted
`
`research on advanced materials, semiconductor devices, and fabrication
`
`processes for ICs including AMLCDs. In 1997 I co-chaired the Active Matrix
`
`Liquid Crystal Displays Conference, which was held as part of the
`
`Symposium on Electronic Imaging Science and Technology co-sponsored by
`
`the Society for Imaging Science and Technology (“IS&T”) and the
`
`international professional society for optics and photonics technology
`
`(“SPIE”). In 1997 and again in 1998 I gave a tutorial on “Flat Panel Display
`
`Materials and Large-Area Processing” at the Materials Research Society
`
`(“MRS”) Spring Meeting, which covered the state of the art as well as
`
`emerging TFT technologies for AMLCDs. In 1998 and 1999 I served as a
`
`member of the Technical Program Subcommittee on Detectors, Sensors and
`
`Displays for the IEEE International Electron Devices Meeting.
`
`9.
`
`In 2003, I became a full professor of EECS and continued my research on
`
`advanced IC materials and semiconductor devices and fabrication processes,
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`which included work developing high-performance TFT technology for
`
`AMLCDs. In 2004, I gave a short course on “Polycrystalline-Silicon Thin-
`
`Film Transistor Technology for Active-Matrix Displays,” as part of the
`
`Display Winter School at National Chiao Tung University (Hsinchu, Taiwan).
`
`10. At UC Berkeley I have taught multiple courses covering semiconductor
`
`devices, IC design and microfabrication. In 1999 I taught a graduate-level
`
`course on Flat-Panel Display Technologies, which covered AMLCD
`
`technology.
`
`11. I served as the faculty director of the UC Berkeley Microfabrication
`
`Laboratory (“Microlab”), a shared clean room research facility, from 2000 to
`
`2004. Starting in 2000, I cofounded and served as president of Progressant
`
`Technologies, Inc., which developed new transistor technology for compact
`
`memory IC products. In 2004 I sold the company to Synopsys, Inc. and took
`
`industrial leave of absence from 2004 to 2006 to work for Synopsys as Senior
`
`Director of Engineering for its Advanced Technology Group, to develop new
`
`semiconductor technologies. I returned full-time to UC Berkeley in 2006 and
`
`resumed the position of Microlab faculty director from 2006 to 2008.
`
`12. From July 2008 through June 2012, I served as Associate Dean for Research
`
`in the College of Engineering. Since July 2012 I have been serving as Chair of
`
`the Electrical Engineering Division of the EECS department at UC Berkeley.
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`Since July 2014 I also have been serving as Chair of the EECS department.
`
`From July 2009 through June 2014, I held the Conexant Systems
`
`Distinguished Professorship in EECS. Since July 2014 I have held the Taiwan
`
`Semiconductor Manufacturing Company Distinguished Professorship in
`
`Microelectronics.
`
`13. Since 1990, I have attended annual IEEE conferences relating to
`
`semiconductor devices and ICs. Since 1992, I have attended annual SID
`
`conferences relating to flat-panel display devices and technologies. At these
`
`technical conferences, I attended presentations by manufacturers of AMLCDs
`
`and spoke to their representatives about trends in AMLCD technology. I have
`
`also taken short courses and attended tutorials and seminars that cover
`
`AMLCD technology and market.
`
`14. Over the course of my career, I have received ninety-one U.S. patents in the
`
`field of semiconductor devices and technology. My honors and awards
`
`include the Ross M. Tucker AIME Electronics Materials Award (1992) for
`
`seminal work in polycrystalline silicon-germanium thin films, the DARPA
`
`(Defense Advanced Research Projects Agency) Significant Technical
`
`Achievement Award (2000) for development of the FinFET, promotion to
`
`Fellow of the IEEE (2007) for applications of silicon-germanium thin films to
`
`metal oxide semiconductor transistors and microelectromechanical systems,
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`the IEEE Kiyo Tomiyasu Award (2010) for contributions to nanoscale MOS
`
`(metal-oxide-semiconductor) transistors, memory devices, and MEMs (micro-
`
`electro-mechanical systems) devices, the Electrochemical Society Thomas D.
`
`Callinan Award (2011) for excellence in dielectrics and insulation
`
`investigations, the Intel Outstanding Researcher in Nanotechnology Award
`
`(2012), and the Semiconductor Industry Association University Research
`
`Award (2014).
`
`15. I have authored or co-authored over 470 publications in the field of
`
`semiconductor devices and technology, including over 50 invited conference
`
`presentations, and have given more than 100 invited seminars and
`
`presentations at universities, companies, and industry-sponsored
`
`workshops/symposia. My publications and presentations are listed in my CV
`
`at Ex. 1014.
`
`Overview of the ’550 Patent
`
`16. The ’550 Patent addresses a liquid crystal display driving device of matrix
`
`structure type to increase the response speed of the liquid crystal display. At a
`
`high level, the patent describes a liquid crystal display device with a matrix
`
`array of thin film transistors (“TFT”) having N rows of gate lines (highlighted
`
`in yellow in the figure below) and M columns of groups (i.e., pairs) of data
`
`lines (highlighted in red and blue) connecting the gates and the sources of the
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`TFTs to multiple gate drivers (yellow boxes) and source drivers (red boxes),
`
`respectively. For example, the odd gate lines (e.g., G1 and G3 in the figure
`
`below) are connected to the gates of the TFTs (denoted as “Q” in the figure
`
`below) and the sources of the TFTs Q are connected to the first data lines (e.g.,
`
`D1 and D2) within each of the groups of data lines. Similarly, the even gate
`
`lines (e.g., G2) are connected to the gates of the TFTs Q, the sources of which
`
`TFTs Q are connected to the second data lines (e.g., D1’ and D2’) within each
`
`of the groups of data lines. This forms alternating connections of the first and
`
`second data lines of the group of data lines with the respective odd and even
`
`rows of gate lines (the “Odd/Even Alternating Connections”).
`
`
`
`17. The M groups of data lines and the N gate lines of the Odd/Even Alternating
`
`Connections are described as “insulated with each other.” (Ex. 1001, Col.
`
`8:20-22, 29-31). As explained further below, a person of ordinary skill in the
`
`art (“POSA”) would understand this to mean that the data lines and gate lines
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`are electrically insulated from each other. The specification describes that the
`
`second data line of the first group of data lines (e.g., D1’) and the first data line
`
`of the second group of data lines (e.g., D2) are “neighboring data lines,” and
`
`that there is “a space between the neighboring data lines” to prevent the data
`
`lines from short circuit. (Id., Col. 8:31:36). However, the ’550 Patent does not
`
`provide any specifics as to the width of the space between the neighboring
`
`data lines necessary to prevent short circuits.
`
`18. The ’550 Patent further describes that “the first data line of each group of data
`
`lines and the neighboring second data line of another group of data lines are
`
`connected to the same source drivers”; that is, the data lines from two groups
`
`of data lines share the same source driver, and that the data transfer is
`
`switched by an electronic switch. (Id., Col. 8:47-52). The specification also
`
`describes the electronic switch as required only when the first data line of one
`
`group and the second data line of another group share the same source driver.
`
`(Id., Col. 8:47-52, 10:21-26, 18:7-12).
`
`19. However, Figure 6A, reproduced below, shows use of electronic switches
`
`(highlighted in brown ovals) where the first data line (D1, red) and the second
`
`data line (D1’, blue) of the same group of data lines (i.e., D1 and D1’) share the
`
`same source driver. The specification contains no further details as to the
`
`structure or function of the electronic switches. Further, there is no description
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`of the two lines (highlighted in green) that seemingly connect the electronic
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`switches horizontally across the matrix.
`
`
`
`20. The ’550 Patent also states that “the form of the gate driver can be a chip on
`
`glass or an integrated gate driver circuit on glass” without providing any more
`
`description. (Id., Col. 8:53-54).
`
`Level of Ordinary Skill
`
`21. As can be seen, the ‘550 Patent is directed to the design and construction of
`
`LCD devices, such as may be used in television or other video monitors. It is
`
`my opinion that a person of ordinary skill in the art at the time of the
`
`inventions claimed in the ’550 Patent (“POSA”) would have at least an
`
`undergraduate degree in electrical engineering, or related field, at least one (1)
`
`year of education or training in semiconductor devices and integrated circuit
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`design, and at least two (2) years of experience with active-matrix liquid
`
`crystal display (“AMLCD”) technology, including work on a project that
`
`included the eventual fabrication and testing of an AMLCD. I have provided
`
`my opinion from the point of view of a person of skill in this art in August,
`
`2004.
`
`Claim Construction
`
`22. I have been asked to offer my opinion regarding how a POSA would have
`
`understood certain claim terms in the ’550 Patent. I understand that in this
`
`proceeding, claim terms are interpreted in accordance with their broadest
`
`reasonable construction consistent with the specification.
`
`“Gate drivers” and “Source drivers”
`A.
`23. The claim terms “the gate drivers” and “the source drivers” appear in both
`
`independent claims 1 and 2. There is no earlier mention of a gate driver or a
`
`source driver in the claims and thus it is not clear to what “the” gate drivers
`
`and “the” source drivers are referring. In my opinion, a POSA would construe
`
`these terms as written in the plural form. That is, “the gate drivers” refer to
`
`more than one gate driver and “the source drivers” refer to more than one
`
`source/data driver. This is the way I have construed these terms for purposes
`
`of this declaration. However, I note below that a POSA would appreciate that
`
`the use of the plural form of “gate drivers” and “source drivers” can lead to
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`some ambiguity when comparing the prior art to the claims in light of a
`
`POSA’s understanding of this technology. Thus, I offer the additional
`
`explanation below.
`
`24. I note that when the ‘550 Patent depicts the prior art in Fig. 1 and in the
`
`embodiment of the invention described with respect to Fig. 4, the drawings
`
`use the term “Gate driver” in the singular in both instances. Also, the prior art
`
`drawing Fig. 1 uses the singular term “Source driver” whereas Fig. 4A uses
`
`the term “Source driver x 2 (60 Hz).”
`
`
`
`25. The ‘550 Patent itself contains little discussion of the gate driver and does not
`
`purport to draw a distinction over the prior art on the basis of this feature. The
`
`specification states, with respect to the prior art, that: “[t]he gate driver 12 is
`
`installed on one side of the display panel 10” and “can continuously provide
`
`scanning signal. The scanning signal can be transferred to the display panel 10
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`through the plurality of gate lines 121 connected with the gate driver 12.” (Ex.
`
`1001, Col. 1:41-45). The specification does not disclose how the multiple gate
`
`drivers with a plurality of gate lines are implemented in the panel. A POSA
`
`would know that a typical structure of a gate driver for an active matrix LCD
`
`display (“AMLCD”) in the early 1990s would include a shift register and
`
`multiple buffers, one buffer corresponding to each gate line to charge up the
`
`capacitive load presented by the gate lines, as shown schematically in Lewis
`
`(Ex. 1008) at pp. 1835-36, Fig. 4(a) (buffers highlighted in yellow):
`
`
`
`A POSA would ordinarily consider the structure shown in Fig. 4(a) of Lewis
`
`to be a single “gate driver” even though multiple buffers are present. Thus, a
`
`POSA would understand that one interpretation of the plain language “gate
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`drivers” as used in the ‘550 Patent is a single gate driving circuit having
`
`multiple buffers, one per line, as was conventional in the art as of the priority
`
`date of the ‘550 Patent, as evidenced by Lewis (Ex. 1009).
`
`26. A second interpretation of “gate drivers” as written in the plural, could be that
`
`shown in Fig. 20A of the ‘550 Patent, in which a separate “Gate driver” made
`
`up of several IC chips (highlighted in yellow boxes) is illustrated as being
`
`located on the right and left sides of the display:
`
`
`
`While this arrangement would also fit within the plain language of the term
`
`“gate drivers,” I note that the embodiment depicted in Fig. 20A was not
`
`indicated as being “elected” for purposes of examination in the prosecution
`
`history. (Ex. 1002 at 127).
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`27. A third interpretation of “gate drivers,” plural, is that a gate driving circuit can
`
`be implemented using multiple gate driver IC chips. The number of gate lines
`
`in an LCD can be in the hundreds and may exceed one thousand lines. Trying
`
`to fabricate one large IC chip to drive many hundreds of gate lines would be
`
`prohibitively expensive. Thus, a POSA would expect to use multiple gate
`
`driver IC chips. This is consistent with the illustration of the “Gate driver” in
`
`the prior art figure (Fig. 1A) as well as the embodiments of the alleged
`
`invention (e.g., Fig. 4A).
`
`28. Potential ambiguity also exists with respect to the claim term “source drivers.”
`
`The specification of the ’550 Patent does not describe a “source driver,” but it
`
`does describe a “data driver” which “can change the data of the adjusted gray
`
`level signal into the corresponding data voltage” and transfer the image signal
`
`to the display panel (i.e., the TFTs) through the data lines. (Ex. 1001, Col.
`
`1:36-41). The purpose of the data driver is to convert serial input into parallel
`
`output signals, and provide the appropriate output signals (analog voltages)
`
`onto the data lines. (Ex. 1008, p. 1836). For the purposes of this declaration,
`
`the terms “source driver” and “data driver” will be used interchangeably.
`
`29. Figure 5(a) of Lewis shows a common data driver architecture used for
`
`AMLCDs in the 1990s:
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`
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`Fig. 5(a) shows a digital interfacing architecture that feeds digital input into
`
`the shift register. The shift register transfers the data in parallel to multiple
`
`digital to analog converters (DACs, highlighted in red) to generate the
`
`appropriate analog signals to drive the data lines. (Ex. 1008, p. 1836). One
`
`DAC is used per data line.
`
`30. A POSA would understand from the description of the data drivers in the
`
`embodiments of the ’550 Patent that DACs are used to convert digital data
`
`input into analog voltage signals to drive the data lines. A POSA would
`
`understand this because the ‘550 Patent refers to “codes” that represent analog
`
`voltage levels throughout. (See, e.g., Ex. 1001, Col. 2:55-3:14, Figs. 3A-C &
`
`7). The function of a DAC is to convert an input code into an output voltage
`
`as shown in Lewis. (Ex. 1008, p. 1840 at Fig. 17). Thus, a POSA would
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`appreciate that the embodiments of the ’550 Patent utilize a digital data driver
`
`architecture similar to Fig. 5(a) of Lewis.
`
`31. Similar to the interpretation of the term “gate drivers” discussed above, the
`
`interpretation of “source drivers,” plural, in the claims of the ‘550 Patent is
`
`also subject to ambiguity. As in the case of gate driver circuits explained
`
`above at ¶27, a POSA understands that although the figures in Lewis and
`
`other prior art references may use one rectangular box to represent the source
`
`driver circuit, in reality, several source driver IC chips are required to drive an
`
`LCD. This is because trying to fabricate one large IC chip to drive several
`
`hundred to over thousand data lines would be prohibitively expensive to
`
`implement. Ultimately, with respect to the source driver, no matter how many
`
`IC chips are used, there is one DAC corresponding to each data line. (Id., p.
`
`1836).
`
`32. Therefore, with respect to the multiple “source drivers” limitation in the
`
`claims, the POSA would understand that there are multiple DACs connected
`
`to the data lines to drive each column independently as shown in Ex. 1008,
`
`Fig. 5(a), for the reasons discussed above. Another possibility is that multiple
`
`source drivers in the claims refer to the multiple IC chips included in the
`
`typical data driver circuitry for an AMLCD that was known at the time. This
`
`interpretation is consistent with the drawings of the ’550 Patent. Further, the
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`’550 Patent does not purport to draw a distinction over the prior art on the
`
`basis of this feature. It is particularly interesting to note that, the figures that
`
`describe the embodiment of the invention that was elected for patent
`
`prosecution, i.e., Figs. 4A-4C (Ex. 1002 at 122, 127) do not match up with
`
`claims 1-2 as issued. Fig. 4A appears to describe the “source driver” as a
`
`multiple of two (i.e., “Source driver x2”), the meaning of which is unclear and
`
`is not explained in the specification. Taken literally, each block representing a
`
`source driver in Fig. 4A would contain two source drivers, one connected to
`
`the first data line and one connected to the second data line, respectively. This
`
`would not meet the claim requirement “wherein the first data lines and the
`
`second data lines of each group of data lines are connected with the same
`
`source driver.” Fig. 5 shows the first and the second data line of the group of
`
`data lines each being connected to different source drivers installed on the top
`
`side of the panel and the bottom side of the panel, respectively. Thus, the
`
`embodiment illustrated in this figure also does not meet the limitation in
`
`claims 1 and 2 that “wherein the first data lines and the second data lines of
`
`each group of data lines are connected with the same source driver.” A
`
`POSA would therefore understand that Fig. 6 is the sole representation of the
`
`embodiment covered by the claims.
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`“Insulated with each other”
`B.
`33. The phrase “a group of N gate lines . . . insulated with each other” and “M
`
`groups of data lines . . . insulated with each other” appear in both
`
`independent claims 1 and 2. The specification uses the phrase “insulated with
`
`each other” when describing “the data line 111 and gate line 121” (i.e., both
`
`singular) that are “orthogonally crossed” as shown in Figures 1A and 1B of
`
`the prior art in the ’550 Patent. (Ex. 1001, Col. 1:45-47). The specification
`
`also uses the phrase “insulated with each other” in connection with the first
`
`embodiment shown in Figs. 4-7 where the specification states: “Therefore,
`
`there are N gate lines connected to gate driver and they are insulated with each
`
`other.” (Id., Col. 8:20-22). The specification also states: “Therefore, in total
`
`there are M groups of data lines connected to the data drivers and they are
`
`insulated with each other.” (Id., Col. 8:29-31). In the first embodiment, as
`
`shown in Figs. 6A and 6B, the gate lines are orthogonally crossed with the
`
`data lines, and vice versa. The gate lines and the data lines are also shown to
`
`be parallel to each other and therefore not in physical contact with each other.
`
`34. One of skill in the art would recognize that “insulated with each other”
`
`includes a grammatical error and is meant to be “insulated from each other,”
`
`and that there is no electrical connection between the two lines because the
`
`lines are not in contact with each other. This is consistent with the
`
`20
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`Docket No. 031179.00133
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`descriptions of the lines being parallel to each other. Furthermore, when
`
`reading the description of gate lines and data lines being “orthogonally
`
`crossed,” a POSA understands that due to the “insulation,” these lines are not
`
`in physical contact with each other and do not make any electrical connection.
`
`“A space between the neighboring data lines”
`C.
`35. The phrase “a space between the neighboring data lines to prevent them from
`
`short circuit” appears in dependent claim 3. The specification of the ‘550
`
`Patent does not discuss any minimum dimensions of the space necessary to
`
`prevent a short circuit and does not ascribe any particular significance to the
`
`size or shape of the space. The only instances of the specification describing a
`
`“space between the neighboring data lines to prevent them from short circuit”
`
`are in connection with “the arrangements shown” in Figs. 4C, 8C, and 22D.
`
`(Ex. 1001, Col 8:31-36, 10:5-10, 17:60-64). As shown below, Figs. 4C and 8C
`
`seem to show the data lines to be evenly spaced apart, regardless of whether
`
`the space is between two lines of the same group or two lines of the
`
`neighboring groups, whereas Fig. 22D shows that the space between the
`
`neighboring groups (e.g., D1’ and D2) is smaller than the space between the
`
`data lines of the same group (e.g., D1 and D1’).
`
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`Docket No. 031179.00133
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`Therefore, while the written description in the patent makes clear that the
`
`figures are intended to be examples, the specification does not clearly define
`
`the boundaries of the “space” being claimed. For example, the arrangement
`
`shown in Fig. 6A would also appear to have a “space” between “neighboring
`
`data lines” such that there is no short circuit.
`
`36. Thus, a POSA is left to rely only on the literal language of this limitation,
`
`which recites “a space between the neighboring lines.” The broadest
`
`reasonable construction of this literal language is that it refers to any space
`
`sufficient to prevent two data lines from electrical communication, in other
`
`words, to prevent a short circuit. This is how I have construed this term for
`
`purposes of this declaration.
`
`22
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`Docket No. 031179.00133
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`The Admitted Prior Art of the ‘550 Patent
`
`37. As discussed above, the ’550 Patent describes the prior art at length at Col.
`
`1:24-3:15 and Figs. 1-3 (“Admitted Prior Art”). Figs 1A and 1B are of
`
`particular significance and are shown below.
`
`
`
`
`
`38. As seen in these figures, the prior art display panel 10 includes data lines 111
`
`(highlighted in red) and gate lines 121 (highlighted in yellow) connected to
`
`the sources and the gates, respectively, of thin film transistors (“TFTs”)
`
`shown as Q1. The data lines and gate lines are orthogonally crossed and
`
`insulated with (i.e. “from”) each other, such that there is no electrical
`
`connection between the lines. (Ex. 1001, Col. 1: 45-47). Pixel 13 is defined as
`
`the area enclosed between two adjacent data lines 111 and two adjacent gate
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`Docket No. 031179.00133
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`lines 121 and includes TFT Q1. (Id.). Thus, applicant admitted that utilizing
`
`multiple gate drivers 12 (yellow boxes) and multiple source drivers 11 (red
`
`boxes) was already known in the art and not the novel aspect of the alleged
`
`invention of the ’550 Patent.
`
`39. In the Admitted Prior Art, the gate drivers 12 provide scanning signals to the
`
`gates of the TFTs via the gate lines 121 to turn each pixel TFT on and off.
`
`Multiple source drivers 11 (red boxes) are connected on the top side of the
`
`periphery of the active matrix as viewed in the figure and provide the voltage
`
`signals to the data lines 111. The voltages on the data lines are transferred to
`
`the pixels via the TFTs which are switched on and off by the control signals
`
`on the gate lines 121. (Id., Col. 1:24-61). A driving voltage is thereby applied
`
`to the liquid crystal molecules corresponding to pixels 13, which each
`
`comprise a liquid crystal capacitor CLC and a storage capacitor CS, to form an
`
`image. (Id., Col. 1:45-57, Fig. 1B).
`
`The Janssen ’708 PCT Publication
`
`40. Janssen ’708 addresses “the problem associated with the existing architecture”
`
`of “video displays” that include matrices of pixels in row and column format.
`
`(Ex 1004, pp. 1:6-2:5). Janssen ’708 discloses, among other things, a driving
`
`circuit and method for driving pixels in a column row matrix that aims to
`
`“reduc[e] the capacitive load in the columns of the matrix” by splitting the
`
`24
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`Docket No. 031179.00133
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`columns into multiple column lines. (Id., pp. 1:26-2:5). Figure 3 of
`
`Janssen ’708 shows the layout according to its invention:
`
`
`
`
`
`41. Janssen ’708 discloses a column row matrix of “junctions” (e.g., 94A)
`
`generally comprising transistor 96, capacitor 98, “pixel” 100, and ground 102.
`
`(Id., p. 5:16-18). A POSA would understand that the pixel 100 is a liquid
`
`crystal pixel display element and that the transistor 96 is a TFT, because by
`
`the time the application for the Janssen ’708 patent was filed in 2001, a POSA
`
`would conclude that “video displays” utilizing a column row matrix of pixels
`
`as disclosed in Janssen ’708 are AMLCD displays. A POSA would also know
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`that AMLCD displays use TFTs to drive liquid crystal display pixels. This is
`
`evidenced, for example, by T. N. Ruckmongathan, “Driving matrix liquid
`
`crystal displays”, Pramana Journal of Physics, Vol. 53, No. 1, July 1999, at p.
`
`210. (Ex. 1011). A POSA would consider the structure of the matrix disclosed
`
`in Janssen ’708 and conclude that TFT is the only plausible embodiment of
`
`the transistor 96, because using any other alternative form of transistor on a
`
`glass substrate at the time would have been prohibitively expensive.
`
`42. As can be seen in Fig. 3, the row matrix comprises M rows of gate lines
`
`(yellow) that are connected to the gate electrode of each transistor 96. Data
`
`line 80A (red) is connected to the source of each transistor on the odd rows
`
`and data line 80B (blue) is connected to the source of each transistor on the
`
`even rows, which forms the Odd/Even Alternating Connection structure set
`
`forth in the claims. Each pair of column lines 80A, 80B communicate with
`
`alternating rows of pixel junctions, e.g., the first column line 80A
`
`communicating with the odd rows (e.g., 94A-C, 94G-I) and the second
`
`column line 80B communicating with the even rows (e.g., 94D-F, 94J-L). (Ex.
`
`1004, p. 5:11-15, Fig. 3). Note that Fig. 3 shows one junction 94G as being
`
`connected to both 80A and 80B and row 90 being connected to column line
`
`80B, but a POSA would understand that these are obvious errors in the
`
`drawing and that both connections to 80B should not have been ind

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