(12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT)
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`(19) World Intellectual Property Organization
`International Bureau
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`(43) International Publication Date
`26 September 2002 (26.09.2002)
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`
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`PCT
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`(10) International Publication Number
`WO 02/075708 A2
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`(51) International Patent Classification7:
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`G09G 3/20
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`(21) International Application Number:
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`PCT/IB02/00903
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`(22) International Filing Date:
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`19 March 2002 (19.03.2002)
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`(25) Filing Language:
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`(26) Publication Language:
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`English
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`English
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`(72) Inventors: JANSSEN, Peter, J., M.; Prof. Holstlaan 6,
`NL—5656 AA Eindhoven (NL). ALBU, Lucian, R.; Prof.
`Holstlaan 6, NL—5656 AA Eindhoven (NL).
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`(74) Agent: VAN DEN HOOVEN, Jan; Internationaal Oc—
`trooibureau B.V., Prof. Holstlaan 6, NL—5656 AA Eind—
`hoven (NL).
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`(81) Designated States (national): CN, JP, KR.
`
`(30) Priority Data:
`09/812,489
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`20 March 2001 (20.03.2001)
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`US
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`(84) Designated States (regional): European patent (AT, BE,
`CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC,
`NL, PT, SE, TR).
`
`(71) Applicant: KONINKLIJKE PHILIPS ELECTRON-
`ICS N.V. [NL/NL]; Groenewoudseweg 1, NL—5621 BA
`Eindhoven (NL).
`
`Published:
`
`without international search report and to be republished
`upon receipt of that report
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`(54) Title: COLUMN DRIVING CIRCUIT AND METHOD FOR DRIVING PIXELS IN A COLUMN ROW MATRIX
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`[Continued on next page]
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`80A ‘v
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`(57) Abstract: A column driving circuit and method for driv—
`ing pixels in a column row matrix. Specifically, the present in—
`vention provides a circuit and method that generally includes an
`input for receiving a signal, a multiplexing circuit for receiving
`the signal from the input, and a first and a second column line,
`wherein each column line alternates in receiving the signal from
`the multiplexing circuit. By splitting the signal between two col—
`umn lines, overall line capacitance is reduced, as are problems
`associated with delays in ramp retrace.
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`For two-letter codes and other abbreviations, refer to the ”Guid-
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`1
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`Column driving circuit and method for driving pixels in a column row matrix
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`The present invention generally relates to a column driving circuit and method
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`for driving pixels in a column row matrix. More particularly, the present invention relates to
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`an improved circuit and method for reducing the capacitive load on the columns of the matrix
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`to provide improved pixel driving.
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`In video displays, matrices are commonly utilized in which pixels are oriented
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`in a column row format. The column driving scheme currently employed to drive the pixels
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`is based on a common analog ramp signal that is sampled by all columns in the display.
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`Problems associated with this architecture include a high capacitive load that each column
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`10
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`presents to the column buffer, where a buffer amplifier is used in every column. Moreover,
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`as the addressing frequency increases, as a result of a higher frame rate or a higher pixel
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`count of the display, the fidelity of the sampled signal decreases.
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`Another problem associated with the existing architecture is ramp retrace. In
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`particular, the ramp signal in each column must retrace rapidly to an initial state in order to
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`15
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`maximize the time available for sampling. Specifically, before the columns of the existing
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`architecture can be driven with the analog signal, they must first be brought to an initial state
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`or retraced. Thus, driving the pixels is at least a two step process in which each column
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`must: (1) retrace to initial state; and (2) apply the analog signal. Since, a fast retrace requires
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`large current capability of the driver(s), the associated large transients in the matrix could
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`20
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`cause undesired effects, e.g., activating unselected rows.
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`In view of the foregoing, there exists a need for a column driving circuit and
`method for reducing the capacitive load in the columns of the matrix. Moreover, a need
`exists for a column driving circuit and method that reduces the problems associated with
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`ramp retrace.
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`25
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`and: method fer d,
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` object of the invention to provide an impr0ved column driving circuit
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`, g pixels i-n’a column row matrix. Specifically, the presentégéinvention
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`providesa columndriving circuit wherein each column is split into at leasttWo column lines.
`Eac‘h‘xeol‘umnIlineeeommunicates with/is joined to a unique subset of11‘,OWS=:i=n‘ the-matrix. By
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`splitting the columns into multiple column lines, the capacitance of each line is a fraction of
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`that required by a single column. In addition, because each column is split into at least two
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`column lines, a first column line can be retraced to the initial state while the second column
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`line is being driven by the analog signal thus, reducing the delays associated with ramp
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`retrace .
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`To this end, a first aspect of the present invention provides a column driving
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`circuit for driving pixels in a column row matrix. The circuit comprises: (1) a multiplexing
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`circuit for receiving a signal; and (2) a first and a second column line, wherein the column
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`lines receive the signal from the multiplexing circuit, and wherein the first column line is in
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`10
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`communication with different rows of the matrix than the second column line.
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`A second aspect of the present invention provides a method for driving pixels
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`in a column row matrix. The method comprises the steps of: (1) receiving a signal in a
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`multiplexing circuit; (2) selectively sending the signal from the multiplexing circuit to a first
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`and second column line; and (3) communicating the column lines with rows of the matrix to
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`15
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`drive the pixels, wherein the first column line communicates with different rows than the
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`second column line.
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`Therefore, the present invention provides a column driving circuit and method
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`for driving pixels in a column row matrix. The present invention reduces the problems
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`associated with high column capacitance and ramp retrace.
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`20
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`Further advantageous embodiments are defined in the dependent claims.
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`These and other features and advantages of this invention will be more readily
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`understood from the following detailed description of the various aspects of the invention
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`taken in conjunction with the accompanying drawings in which:
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`25
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`Fig. 1 depicts a first prior art column driving circuit;
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`Fig. 2 depicts a second prior art column driving circuit;
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`Fig. 3idepicts a column driving circuit in accordance with the present
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`invention;
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`7
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`Fig 4 depicts a first alternative embodiment of a column driving circuit in
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`30
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`accordance with .t
`Fig
`Fig
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`sent invention;
`r'epicts a multiplexing circuit in accordance with the present invention;
`depicts an alternative embodiment of a multiplexing circuitinfi
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`accordancexNith the present invention; and
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`Fig. 7 depicts a second alternative embodiment of a column driving circuit in
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`accordance with the present invention.
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`It is noted that the drawings of the invention are not necessarily to scale. The
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`drawings are merely schematic representations, not intended to portray specific parameters of
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`the invention. The drawings are intended to depict only typical embodiments of the
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`invention, and therefore should not be considered as limiting the scope of the invention. In
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`the drawings, like numbering represents like elements.
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`As stated, the present invention comprises an improved column driving circuit
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`10
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`and method for driving pixels in a column row matrix. Generally, the present invention splits
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`each column of the matrix into a plurality (preferably two) column lines. Each column line
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`communicates with, or is joined, to a unique subset of rows in the matrix. Accordingly, the
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`different column lines of a single column communicate with different (e.g., alternating) rows.
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`An analog ramp signal then is alternately applied to the column lines within each column.
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`15
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`The resulting configuration reduces the capacitance on each column line. Moreover, as the
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`analog signal is being applied to a first column line, a second column line can be retraced to
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`an initial state. Therefore, there is negligible delay for a column line to retrace to the initial
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`state.
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`Referring first to Fig. 1, a prior art column driving circuit 10 is depicted. The
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`circuit is for driving pixels in a column row matrix 11. As shown, the matrix comprises
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`columns 24, 26, and 28 and rows 30, 32, 34, and 36. Digital input signals 12, 14, and 16 are
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`received by each column via digital to analog converter (DACs) 18, 20, and 22. Each DAC
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`converts the digital signal to an analog signal, which is then used to drive a particular column
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`within the matrix. Specifically, the analog signal exits each DAC 18, 20, and 22 and is
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`25
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`received by columns 24, 26, and 28, respectively. Each column 24, 26, and 28 includes a
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`junction 40A-L to each row 30, 32, 34 and 36. Accordingly, each row controls one junction
`of each column. Each junction 40A-L generally comprises a pixel transistor 42, a capacitor
`44, a pixel 46 and a ground 48. It should be understood that the capacitor 44 represents a
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`capacitance associated with pixel 46. Accordingly, pixels 46 are not explicitly shown for
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`30
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`each junction 40A:L. However, it should be understood that each junction 40A-Lflincludes a
`pixer43}
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`' When a video display that includes matrix 11 is refreshed, each pixel 46 must
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`be driven To accomplish this, each row will be individually activated for a brief period of
`time Thls allows the analog signal1n each column 24,26 and 28 to paSs throughthe
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`junctions 4OA-L corresponding the activated row and drive the pixels. For eXample, if row
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`30 is to be refreshed, it will first be activated. The analog signals will thenpass from
`columns 24, 26, and 28 through junctions 4OA-C to drive the pixels in row 30. This will then
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`be repeated for rows 32, 34, and 36.
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`As indicated above, however, this architecture presents many problems. In
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`particular each column 24, 26, and 28 has a relatively high capacitance both from the lines
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`and any un-activated pixel transistors, which requires more voltage, and results in reduced
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`accuracy and bandwidth of the matrix. Moreover, before any column 24, 26, and 28 can
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`receive the analog signal, it must first be retraced to an initial state. This delay associated
`with retrace reduces the maximum time available for sampling by the rows, which is
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`10
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`especially problematic in larger matrices.
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`Fig. 2 shows a second prior art column driving circuit 50. This circuit 50
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`includes similar elements as circuit 10 and drives column row matrix 51. Specifically, circuit
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`50 receives digital signals 12, 14 and 16 in DACs 18, 20, and 22 and converts the signals
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`15
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`from digital to analog. The analog signals are then passed to the columns 24, 26, and 28,
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`which communicate with selectively activated rows 30, 32, 34 and 36. In embodiment of
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`Fig. 2, however, each column communicates with pairs of rows instead of individual rows.
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`For example, if row 30 is to be refreshed, it will first be activated. The analog signal will
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`then pass through junctions 40A-C and drive the pixels therein.
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`20
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`The circuit 50 of Fig. 2 possesses the same drawbacks as circuit 10.
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`Specifically, each column 24, 26, and 28 has a relatively high capacitance that requires more
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`time to reach the capacity. This increase in time to reach capacity results in reduced accuracy
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`and bandwidth of the matrix. Specifically, each un-activated transistor 42 has a parasitic
`capacitance slows the time to drive the column. Moreover, as indicated above, each column
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`25
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`must be retraced to the initial state prior to communicating the analog signal through the
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`junctions 40A-L. This retrace causes delay in the cycle and thus, reduces the maximum time
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`available for sampling by the rows.
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`Referring now to Fig. 3, a column driving circuit 60 for driving pixels in a
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`column row matrix 61 in accordance with the present invention is shown. As depicted,
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`30
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`(as shown in Figs. 1 and 2), the signal is outputted over multiple lines. Although each
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`column is shown as being split into two column lines, it should be understood that any
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`quantity of column lines could be formed (e.g., 4, 6, 8, etc.).
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`By splitting each column into two column lines, the capacitance of each
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`column line is approximately one-half that of each column of circuits 10 and 50. As will be
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`described in further detail below, the multiplexing circuits 74, 76, and 78 alternate the
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`respective analog signal between the two column lines in each pair. Thus, for example, while
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`one column line 80A receives the analog signal, the corresponding column line 80B does not.
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`Thus, under the present invention, it is not necessary for each column line to be in
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`10
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`communication with each row 86, 88, 90, and 92 thereby reducing the parasitic capacitance
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`for each column line. Specifically, as shown in Fig. 3, each column line preferably includes
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`junctions 94A—L to a unique subset of rows. For example, column lines 80A, 82A, and 84A
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`are in communication with rows 86 and 90, while column lines 80B, 82B, and 84B are in
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`communication with rows 88 and 92. By not requiring each column line to communicate
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`15
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`with each row, the effects of the parasitic capacitance of each junction are reduced.
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`As further shown in Fig. 3, the junctions generally comprise transistor 96,
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`capacitor 98, pixel 100, and ground 102. It should be understood, however, that a pixel is
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`shown only in junction 94A for clarity purposes, and all junctions include a pixel. To refresh
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`the display on which the column row matrix 61 is implemented, each row is selectively
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`2O
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`activated for a period of time, which allows the analog signal to pass from the column lines,
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`through the junctions corresponding to the activated row, and drive the pixels therein. For
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`example, if row 86 were activated, the analog signals would pass from column lines 80A,
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`82A, and 84A, through junctions 94A-C, and drive pixels 100 (not shown in every junction).
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`Contrary to the teachings of circuits 10 and 50, as column lines 80A, 82A, and
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`25
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`84A are driving the pixels on row 86, column lines 80B, 82B, and 84B are being retraced to
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`an initial state. The switches in the multiplexing circuits 74, 76, and 78 (described below) are
`configured such that while one column line 80A is receiving the analog signal, the
`corresponding column line 80B is being retraced to the initial state (i.e., the analog signal is
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`30
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`alternated betweentthe column lines in each pair). Thus, when row 86 is later deactivated so
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`more) column lines not only reduces the line capacitance and ramp retrace delay, but also
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`reduces parasitic capacitance by allowing each column line in a single pair to communicate
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`with different rows of the column row matrix 61.
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`Fig. 4 shows an alternative embodiment of the present invention. Specifically,
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`column driving circuit 104 drives the pixels 100 in column row matrix 105. Although the
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`components of circuit 104 are similar to that of circuit 60, the architecture thereof is distinct.
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`In particular, digital signals 62, 62, and 66 are received in DACs 68, 70, and 72, where they
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`are converted to analog signals. From the DACs 68, 70, and 72, the analog signals are
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`communicated through multiplexing circuits 74, 76, and 78, which splits each column into
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`10
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`multiple (preferably two) column lines 80A-B, 82A-B, and 84A-B. However, instead of the
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`column lines of each pair communicating with alternating rows as shown in Fig. 3, the
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`column lines of each pair communicate with pairs or adjacent subsets of rows. Thus, rows 86
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`and 88 would be refreshed by a first column line 80A, 82A, and 84A while rows 90 and 92
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`would be refreshed by a second column line SOB, 82B, and 84B. For example, for row 86
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`15
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`was to be refreshed, it would first be activated. Then, the analog signals would pass from
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`column lines 80A, 82A, and 84A through junctions 94A-C and drive the pixels 100.
`As indicated above, the analog signals are alternated between the column lines
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`in each pair so that while one column line is receiving the signal, the corresponding column
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`line can be retraced back to the initial state. Once row 86 has been refreshed, it would be
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`2O
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`deactivated and, for instance, row 90 would be individually activated. Thus, the analog
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`signal would be received by column lines 80B, 82B, and 84B and pass through junctions
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`94G-I to drive the pixels therein. Because retrace occurred while the signal passed through
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`column lines 80A, 82A, and 84A, there is no delay in waiting for column lines 80B, 82B, and
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`84B to be retraced before driving the pixels.
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`25
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`30
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`Referring now to Fig. 5, a first embodiment of the multiplexing circuit 74 is
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`depicted. Asishown, a digital signal 62 is received and converted by DAC 68 to analog. The
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`multlplexmgjcircuit 74 then receives the analog signal from DAC 68. As indicated above,
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`the multip xing circuit alternates the analog signal between column line 80A and 80B.
`Moreover, While one column liners receiving the analog signal, the other will receive a
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`reference voltage 112 to pass through column line 80B to retrace column line 80B to the
`initial state while column line 80A is receiving the analog signal. The switches 104, 106, ,
`108, and 110 are controlled by signals 114, 116, 118, and 120, respectively. These signals
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`activate the transistors in each switch to connect the column lines to the analog signal or
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`voltage.
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`Once the rows corresponding to column line 80A have been refreshed and are
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`deactivated, the rows corresponding to column line 80B can be activated for refreshing. As
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`this occurs, signal switch 104 and voltage switch 110 will be turned “off” while signal switch
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`106 and voltage switch 108 are turned “on.” This allows for the pixels of the rows
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`10
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`corresponding to column line 80B to be driven with the analog signal while column line 80A
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`is retraced to the initial state by reference voltage 112. As indicated above, this architecture
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`and method eliminate the delay and problems associated with ramp retrace.
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`Referring now to Fig. 6, an alternative embodiment of the multiplexing circuit
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`122 is shown. Similar to Fig. 5, the multiplexing circuit 74 receives a digital signal 62 and
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`15
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`includes DAC 68, transistor signal switches 104 and 106 (controlled by signals 114 and 116),
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`transistor voltage switches 112 (controlled by signals 1,18 and 120), and column lines 80A
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`and 80B. However, multiplexing circuit 122 also includes hold signals 128 and 130 and
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`“AND” gates 124 and 126. The hold signals 118 and 120 originate from the DAC 68, which
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`in this embodiment is a “track and hold” DAC. By including a hold signal, the sampling
`switch is opened at the moment sampling is to occur. The difference between a “track and
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`20
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`hold” and “sample and hold” is the duration the sampling switch is closed. Specifically, in a
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`“sample and hold” embodiment, the sampling switch is closed for the shortest possible time.
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`In “track and hold,” the switch is closed from the very beginning of each cycle until it opens
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`at “hold.” Similar to the multiplexing circuit 74 of Fig. 5, the multiplexing circuit 122 will
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`25
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`alternate the analog signal between the column lines 80A and 80B. The column line that is
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`not receiving the analog signal will receive the reference voltage 112 for retracing to the
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`initial state.
`7
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`0 Referring now to Fig. 7, it should be appreciated a circuit according to the
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`30
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`present invention need not require a DAC to drive the pixels. Specifically, if analog signals
`d
`:6 are provided directly to the multiplexing circuits 74, 76, and 78, there is no
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`DAC. Thus, column driving circuit 150 (used to drive pixelsin column row
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`:
`. eceive input (analog) signals 152, 154, and 156 directly at multiplexing
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`circults74, 76,and 78. Multiplexing circuits 74, 76, and 78 will then selectively apply the
`signalsto column lines 80A-B, 82A-B, and 84A—B by alternating the Signalbetweenthe two
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`column lines of each column. Pixel driving will then occur as described above in conjunction
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`with Figs. 3 and/or 4.
`The foregoing description of the preferred embodiments of this invention has
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`‘
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`been presented for purposes of illustration and description. It is not intended to be exhaustive
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`or to limit the invention to the precise form disclosed, and obviously, many modifications and
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`variations are possible. Such modifications and variations that may be apparent to a person
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`skilled in the art are intended to be included within the scope of this invention as defined by
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`the accompanying claims.
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`CLAIMS:
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`PCT/IB02/00903
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`1.
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`A column driving circuit [60] for driving pixels [100] in a column row matrix
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`[61], comprising:
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`a multiplexing circuit [74] for receiving a signal [62 or 152]; and
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`a first and a second column line [80A and 80B], wherein the column lines
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`5
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`[80A and 80B] receive the signal [62 or 152] from the multiplexing circuit [74], and wherein
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`the first column line [80A] is in communication with different rows [86, 88, 90, and 92]of the
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`matrix [61] than the second column line [80B].
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`2.
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`The circuit of claim 1, wherein the multiplexing circuit [74] receives the signal
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`10
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`[62 or 152] from a digital to analog converter (DAC) [68].
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`3.
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`The circuit of claim 1, wherein the multiplexing circuit [74] comprises a
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`plurality of signal switches [104 and 106] for alternating the signal [62 or 152] between the
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`first and second column lines [80A and 80B].
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`15
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`4.
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`The circuit of claim 3, wherein the multiplexing circuit [74] fiirther
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`comprising a plurality of voltage switches [118 and 120] for alternating a reference voltage
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`[112] between the first and second column lines [80A and 80B].
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`20
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`5.
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`The circuit of claim 4, wherein the multiplexing circuit [74] further
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`comprising a hold signal [130] for maintaining voltage in the first and second column lines
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`[80A and 80B].
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`6.
`
`The circuit of claim 3, wherein when the first column line [80A] is receiving
`
`25
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`the signal. [62m 152], the second column line [80B] is receiving the reference voltage [112].
`
`7.
`
`A method for driving pixels [100] in a column row matr1x[61], COmprising the
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`steps fof: ‘
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`recéiying aSignal [62 or 152] in a multiplexing C1rCu1t[74]’
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`selectively sending the signal [62 or 152] from the multiplexing circuit [74] to
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`a first and second column line [80A or 80B]; and
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`communicating the column lines [80A and 80B] with rows [86, 88, 90, and
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`92] of the matrix [61] to drive the pixels [100], wherein the first column line [80A]
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`5
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`communicates with different rows [86, 88, 90, and 92] than the second column line [80B].
`
`8.
`
`The method of claim 7, wherein the column lines [80A and 80B] communicate
`
`with the rows [86, 88, 90, and 92] through junctions [94A, 94D, 94G, 94J], and wherein each
`
`junction [94A, 94D, 94G, 94J] joins one of the column lines [80A or 80B] to one of the rows
`
`10
`
`[86, 88, 90, and 92].
`
`9.
`
`The method of claim 8, wherein each junction [94A, 94D, 94G, 94]]
`
`comprises:
`
`a transistor [96];
`
`15
`
`a pixel [100]; and
`
`I
`
`a ground [102].
`
`10.
`
`The method of claim 9, wherein the multiplexing circuit [74] receives the .
`
`signal [62 or 152] from a DAC [68].
`
`20
`
`11.
`
`The method of claim 10, wherein the multiplexing circuit [74] further
`
`comprises:
`
`a plurality of signal switches [104 and 106] for alternating the signal [62 or
`152] between the first and second column lines [80A and 80B]; and
`
`25
`
`a plurality of voltage signals [108 and 110] for alternating a reference voltage
`
`[112] between the first and second column lines [80A and 80B].
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`1/6
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`1o
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`/
`
`400
`/
`
`Row(m4)
`
`40F
`
`18
`
`12
`
`-
`
`DAC(n-1)
`
`14
`
`16
`
`20
`
`DAC (n)
`
`22
`
`DAC (n+1)
`
`24
`
`40A
`
`26
`
`403
`
`28
`
`/
`Tp (m-1)
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` 1
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`18
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`12
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`'14
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`2/6
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`DAC(n-1)
`
`20
`
`DAC (n)
`
`22
`
`DAC (n+1)
`
`24
`
`26
`
`Row(m+2)
`
`30
`
`32
`
`34
`
`36
`
`16
`
`28
`
`50
`
`/
`
`R0w(m-1)
`
`} 7 «40C
`
`1
`
`‘— 40F
`
`Row(m)
`
`<— 51
`
`Row (m+1)
`
`I l: <— 401
`
`*- 40L
`
`1
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`62
`
`10
`
`80A
`
`I 808
`0 I
`f9]
`
`82A
`
`(O 03
`
`98
`
`
`
`i
`
`l
`
`I
`7
`
`*- 940
`
`Row(m-1)
`
`86
`
`<— 94F
`
`‘— 61
`Row (m)
`
`88
`
`<— 941
`
`Row (m+1)
`
`90
`
`<- 94L
`
`Row (m+2)
`
`Col (nm,
`
`92:“
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`104
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`Row (m—1)
`
`<— 94C
`
`Row (m+2)
`
`‘— 94L
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`
`
`80A-
`
`I
`
`808
`
`HG 6
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