(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2002/0186190 A1
`
` Janssen et al. (43) Pub. Date: Dec. 12, 2002
`
`
`US 20020186190A1
`
`(54) DEVICE AND METHOD FOR ADDRESSING
`LCD PIXELS
`
`Publication Classification
`
`(75)
`
`Inventors: Peter J. Janssen, Scarborough, NY
`(US); Lucian R. Albu, New York, NY
`(Us)
`Correspondence Address:
`Corporate Patent Counsel
`US. Philips Corporation
`580 White Plains Road
`Tarrytown, NY 10591 (US)
`
`(73) Assignee: Koninklijke Philips Electronics N.V.
`
`(21) Appl. N0.:
`
`09/877,426
`
`(22)
`
`Filed:
`
`Jun. 8, 2001
`
`Int. Cl.7 ....................................................... G09G 3/36
`(51)
`(52) US. Cl.
`................................................................ 345/87
`
`(57)
`
`ABSTRACT
`.
`.
`.
`.
`.
`An electro-optic dev1ce comprising a matrix array of an
`LCD display element, the device having shared-source adja-
`cent transistors in contiguous rows, thereby reducing the
`capacitive loading on drivers providing voltage signals
`Which modulate the display elements. In addition, a method
`is provided for utilizing a matrix design that incorporates
`non-contiguous, multi-row addressing and shared-source
`transistors. The device and method provide a display device
`With large pixel count, yet With high display definition and
`performance.
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`

`Patent Application Publication Dec. 12, 2002 Sheet 1 0f 3
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`US 2002/0186190 A1
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`Patent Application Publication Dec. 12, 2002 Sheet 2 0f 3
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`US 2002/0186190 A1
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`Patent Application Publication Dec. 12, 2002 Sheet 3 of 3
`
`US 2002/0186190 A1
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`US 2002/0186190 A1
`
`Dec. 12, 2002
`
`DEVICE AND METHOD FOR ADDRESSING LCD
`PIXELS
`
`FIELD OF THE INVENTION
`
`[0001] The present invention relates to the field of electro-
`optic display devices. More specifically, the present inven-
`tion relates to active matrix liquid crystal displays which are
`multi-row addressable.
`
`BACKGROUND OF THE INVENTION
`
`[0002] LCD devices used in such applications as high
`definition television are known to those skilled in the art.
`
`Examples of such devices, and in particular active matrix
`display devices, are provided by US. Pat. Nos. 4,239,346
`and 5,056,895. In the interest of brevity, familiarity with
`these devices is assumed and the aforementioned patents are
`incorporated herein by reference in their entirety.
`
`In modern uses of LCD devices, such as high
`[0003]
`definition television, there is an increasing need for greater
`display definition and performance. One way of increasing
`definition is to increase the number of pixel elements within
`a constant display area. However, increasing the number of
`elements in a prior art device tends to degrade the perfor-
`mance of the display.
`
`[0004] One reason this degradation occurs is that adding
`pixels decreases the available scanning transfer time T8 for
`a row of elements, in a row-by-row scanning sequence,
`relative to the time needed to scan the entire matrix. Unfor-
`
`tunately, because pixels are connected to storage capacitors,
`CpiX, which require some time to fully charge, any reduction
`in Ta can degrade display performance.
`
`reason is that adding pixel elements
`[0005] Another
`increases the total capacitive load seen by a column driver
`driving the pixel elements. In a typical LCD matrix array
`using transistors switches, a column driver is electrically
`connected to each transistor source, s, and associated sub-
`strate capacitance, CS, within a column of the array. There-
`fore a column driver sees CpiX, the storage capacitor of a
`target pixel, as well as all CS capacitors located in a column
`in a parallel combination. The combination of all CS capaci-
`tors is substantial relative to the value of a single CpiX. The
`charging speed for the pixel capacitor, CpiX, may be slowed
`if the numbers of CS capacitors within a column increases.
`Thus, adding pixels not only reduces the available scanning
`transfer time, T8, but compounds the problem by increasing
`the capacitive load seen by a column driver. Both effects can
`combine to slow the transfer of a voltage signal to an LCD
`pixel.
`
`In view of current applications requiring high dis-
`[0006]
`play definition and high pixel count, it would be desirable to
`provide an array display device that reduces capacitive load
`seen by a column driver, and moreover, a method to increase
`scanning time, T8, and thereby improve display perfor-
`mance.
`
`SUMMARY OF THE INVENTION
`
`[0007] One aspect of the invention provides an electro-
`optical display device which may include: an M row by N
`column matrix array of display elements; a plurality of pairs
`of transistor switches including a shared source, the source
`operably connected to the plurality of pairs of display
`
`elements, wherein the two elements are separately located in
`adjacent rows; a plurality of driving connectors operably
`connected to a plurality of Q non-contiguous rows of display
`elements; and a plurality of switch connectors operably
`connected to Q non-contiguous rows of display elements to
`allow electrical connection with driving signals from col-
`umn drivers. Q can be a whole number 2 or greater. Sharing
`the transistors sources can eliminate one-half of substrate
`
`capacitance, CS and the plurality of switch connectors allows
`concurrent, multi-row addressing of non-contiguous rows of
`elements.
`
`In addition, the display device may include means
`[0008]
`to produce switching signals, such as row drivers, which
`enable a connection between a transistor source and the
`
`pixel storage capacitor, CpiX. And further, the device may
`include means for producing driving signals, such as column
`drivers having A/D converters that output analog voltage
`signals which charge Cpix and modulate light in the LCD
`pixel element.
`
`In a preferred embodiment, each of M row drivers
`[0009]
`may be electrically connected to Q number of non-contigu-
`ous rows of transistors gates, and each of N column drivers
`may be electrically connected to M/Q*2 rows of transistor
`sources.
`
`[0010] Another aspect of the invention provides a method
`of addressing an array of M by N display elements. The
`method can include: providing paired transistors, which act
`as switches to the display elements, the paired transistors
`sharing a source, and wherein the paired transistors are in
`contiguous
`rows; delivering Q number of concurrent
`enabling switching signals to Q rows of elements through
`electrical connections, wherein the rows of elements are
`non-contiguous; delivering independent signals to each
`enabled element in the non-contiguous rows; and transfer-
`ring the signals to each enabled display element to modulate
`light. The method may further include: successively repeat-
`ing the above steps to other groups of Q non-contiguous
`rows having elements not yet enabled, until the entire array
`has been addressed so that each element is enabled at least
`
`once. Q can be selected as a whole number two or greater.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0011] FIG. 1 is a schematic diagram of one embodiment
`of an active matrix liquid crystal display (AMLCD) device
`having shared-source transistors in contiguous rows;
`
`[0012] FIG. 2 is a schematic diagram of one embodiment
`of an AMLCD device having double the number of column
`drivers and a multi-row addressing scheme; and
`
`[0013] FIG. 3 is a schematic diagram of one embodiment
`of an AMLCD device in accordance with the present inven-
`tion.
`
`BRIEF DESCRIPTION OF THE PRESENTLY
`PREFERRED EMBODIMENTS
`
`[0014] FIG. 1 depicts a schematic diagram of an AMLCD
`device having shared-source transistors in contiguous rows
`of the display array. The array panel 10 includes M rows and
`N columns of display elements 20. Each display element,
`representing one pixel of the panel, can be connected to an
`IGFETS transistor 30 or 35, which acts as a switching
`element. Adjacent, paired transistors in contiguous rows
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`US 2002/0186190 A1
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`Dec. 12, 2002
`
`. (M—1, M) share a source, s. The transistor
`.
`(1,2), (3,4) .
`source, s, can be electrically connected to the output of a
`column driver 40, via electrodes 60.
`
`In a conventional array panel where transistors do
`[0015]
`not share a source (panel not shown), a column driver sees
`a load represented by a parallel combination of all CS
`capacitors in one column of transistors. These CS capaci-
`tances, as well as auxiliary capacitances (not shown), pro-
`vide significant capacitive loading which reduces the speed
`at which a target Cpix can be charged. The shared-source
`transistor arrangement shown in FIG. 1, however, cuts the
`number of CS capacitors in a column by one-half.
`
`In FIG. 1, row driver 70 can be connected to output
`[0016]
`electrode 50, which in turn can be connected to gate, G, of
`every transistor in a particular row. The transistor drain, D,
`can be connected to CpiX, 25. The pixel 20, which may be an
`LCD, can modulate light as various voltages are applied
`across CpiX.
`
`In operation one frame of video information can be
`[0017]
`generated by a video source 75. This frame of analog
`information can be converted to a digital form and stored in
`digital picture memory 80. To transfer the video frame
`information in the picture memory to the LCD pixels, the
`controller circuit 90 can enable address decoder 100 for row
`driver 1. This switches on all transistors in row 1 such that
`
`each LCD pixel 20 in that row can accept a voltage signal
`from its respective column driver 40. With row 1 enabled,
`the controller can instruct the picture memory to transfer the
`video data for the entire row 1 through the data bus 110
`which connects to each of the column drivers 40. The digital
`data can be stored in the column drivers 1 to N and converted
`
`into analog data voltages.
`
`[0018] Then, the analog voltages can be delivered to each
`Cpix 25 within row 1. Next, the controller 90 can turn off all
`transistor switches 30 in row 1 and also turn on all transistor
`
`switches 35 in row 2. However, although the transistors in
`row 1 are switched off, the images already delivered to the
`pixels 20 in row 1 persist because the voltages are main-
`tained by each respective pixel capacitor, CpiX, and any
`auxiliary storage capacitance (not shown). Hence, the rows
`of transistors can be sequentially addressed from row 1 to
`row M, providing row-by-row scanning for the entire LCD
`matrix array. A completed scan of the entire M by N array
`thus can represent one frame of video information. Subse-
`quent frames of video information can be displayed by the
`LCD device by re-addressing rows 1 through M.
`
`[0019] FIG. 2 depicts a schematic diagram of another
`AMLCD device. Instead of row-by-row addressing,
`this
`AMLCD device employs concurrent, multi-row addressing.
`Additionally,
`the device in FIG. 2 does not use shared-
`source transistors. In FIG. 2, contiguous row pairs (1,2),
`(3,4)
`.
`.
`.
`(M—1, M) can be switched on or “enabled”
`concurrently. To permit multi-row addressing,
`the device
`employs double the number of column drivers 40. Each
`column driver 40 may be composed of two separate column
`sub-drivers, A and B, which divide up the addressing load
`within a single column.
`
`In operation, rows (1,2) can be switched on con-
`[0020]
`currently. Next, rows (3,4) can be switched on, then (5,6),
`and so forth, until the final rows (M—1, M) are switched on.
`Both column sub-drivers A and B can transfer unique
`
`voltage signals simultaneously to their enabled, target pixel
`elements. Thus, an application of multi-row addressing as
`described for the device in FIG. 2, requires concurrently
`addressing paired, contiguous rows. While FIG. 2 shows a
`device that addresses two rows concurrently, multi-row
`addressing may be accomplished by concurrently address-
`ing, three, four or more rows at a time.
`
`[0021] FIG. 3 provides an exemplary embodiment of an
`M by N matrix display in accordance with the invention,
`combining shared-source transistors 30, 35 and multi-row
`addressing of non-contiguous rows. The transistors can be
`IGFETS and the display elements can be LCDs. In this
`embodiment there are N column drivers 40 and three column
`
`sub-drivers, A, B, and C, composing each column driver.
`Each sub-driver can be attached to the source, s, of paired
`transistors.
`
`[0022] Enabling signals can be generated by row drivers
`70, each driver having multiple output connections 71, 72,
`and 73, which connect
`to gates G of respective target
`transistor rows. In this example, a row driver connects only
`to non-contiguous rows and the number of output connec-
`tions of a row driver, which is three, equals the number of
`column sub-drivers as represented by A, B and C.
`
`In the exemplary device shown in FIG. 3, transis-
`[0023]
`tors in paired rows (1,2), (3,4), (5,6) .
`.
`. (M—1, M) share a
`common source, s. Column sub-driver Acan be connected to
`the common source for transistors of paired rows (1,2),
`(11,12), (13,14), (23,24) .
`.
`.
`; sub-driver B can be connected
`to the source for transistors of paired rows (3,4), (9,10),
`(15,16), (21,22) .
`.
`.
`; and sub-driver C can be connected to
`the source for transistors of paired rows (5,6), (7,8), (17,18),
`(19,20) .
`.
`. Row driver 1 connects to the gates G of
`transistors of rows (1,3,5); row driver 2 connects to rows
`(2,4,6); row driver 3 connects to rows (7,9,11); and row
`driver 4 connects to rows (8,10,12).
`
`In operation, multi-row addressing is employed by
`[0024]
`sequentially addressing each row driver 1, 2, 3 .
`.
`. M. In
`other words, in the first Ta, rows (1,3,5) may be concurrently
`enabled in the next Ta, rows (2,4,6) can be concurrently
`enabled, and in the next Ta, rows (7,9,11) can be enabled,
`and so forth, until all rows in the display matrix have been
`addressed and enabled.
`
`It will be appreciated by one skilled in the art that
`[0025]
`application of this multi-row addressing method may be
`employed with other devices having shared-source transis-
`tors, other than as shown in the exemplary device of FIG. 3.
`If Q represents the number of rows addressed concurrently,
`Q may also represent the number of column sub-drivers.
`FIG. 3 represents an exemplary case where Q equals three.
`
`is
`it
`invention,
`In accordance with the present
`[0026]
`possible to construct other embodiments of an M by N
`matrix array having Q other than three. In general Q must be
`a whole number two or greater,
`the selection of Q is
`dependent solely on the available integration technologies
`and the size of the desired LCD device. The display device
`can include a matrix array having shared-source transistors
`in contiguous rows in combination with multi-row address-
`ing. In the case where Q is three,
`the number of output
`connections for each column driver 1 through N may be
`represented as M/2, and thus, the number of output connec-
`tions for a sub-driver can be M/6. Generally, each of M row
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`US 2002/0186190 A1
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`Dec. 12, 2002
`
`drivers can be electrically connected to Q number of non-
`contiguous rows of transistors gates, and each of N column
`drivers can be electrically connected to M/Q*2 rows of
`transistor sources.
`
`a plurality of switch connectors operably connected to Q
`non-contiguous rows of display elements to allow
`electrical connection with driving signals from column
`drivers; and
`
`[0027] The result of the method of the present invention
`employing simultaneous, multi-row addressing is to increase
`the available scanning time T8 for a row. In particular, for Q
`number of column sub-drivers, and each row driver having
`Q row connections, the scanning time, T8, for each row can
`be extended according to Ta=(total frame time)/M*Q. Thus,
`multi-row addressing can increase the available scanning
`time for a single row, thereby improving display perfor-
`mance. An attendant benefit of the invention is that each
`
`column sub-driver sees N/Q*2 number of Cs capacitors and,
`thus, the overall capacitive load can be reduced, improving
`display performance. The present invention, thus described,
`may permit high pixel count, while maintaining high display
`performance.
`
`[0028] Another embodiment of the method of addressing,
`however, goes further by employing a “pre-write” strategy.
`Referring again to FIG. 3, this addressing method can be as
`follows. In the first Ta, row drivers 1, 2, and 3 are turned on
`concurrently. This enables rows (1,3,5), (2,4,6) and (7,9,11),
`respectively and allows signals to be received from the
`column drivers. The column sub-drivers, A, B, and C, may
`then provide voltage signals meant for rows (1,3,5) of the
`array. Note that the other enabled rows (2,4,6), (7,9,11) also
`receive the same voltage information in this first step, but
`only for the purpose of “pre-writing”.
`
`In the second Ta, row driver 1 can be switched off,
`[0029]
`while row drivers 2 and 3 remain switched on, and row
`driver 4 can also be switched on concurrently. The column
`drivers then provide voltage signals meant for rows (2,4,6).
`Again, rows (7,9,11) connected to row driver 3 and rows
`(8,10,12) connected to row driver 4 can receive pre-write
`data. In the next Ta, row drivers 1 and 2 can be turned off and
`row drivers 3, 4 and 5 can be switched on. This pattern is
`repeated for the entire array until one frame is completed.
`Pre-writing can reduce cross-talk between source-sharing
`transistors, which are in contiguous rows and thus can
`eliminate row-based artifacts.
`
`[0030] The invention has been described in terms of
`exemplary embodiments. The invention, however,
`is not
`limited to the embodiments depicted and described and it is
`contemplated that other embodiments, which may be readily
`devised by persons of ordinary skilled in the art based on the
`teachings set forth herein, are within the scope of the
`invention.
`
`What is claimed is:
`
`1. An electro-optical display device comprising:
`
`an M row by N column matrix array of display elements;
`
`a plurality of pairs of transistor switches including a
`shared source, the source operably connected to the
`plurality of pairs of display elements, wherein the two
`elements are separately located in adjacent rows,
`
`a plurality of driving connectors operably connected to a
`plurality of Q non-contiguous rows of display ele-
`ments; and
`
`wherein Q is a whole number 2 or greater,
`
`wherein sharing the sources eliminates one-half of sub-
`strate capacitance, Cs and the plurality of switch con-
`nectors allows concurrent, multi-row addressing of
`non-contiguous rows of elements.
`2. The display device of claim 1 wherein the transistors
`are IGFETS.
`
`3. The display device of claim 1 wherein the display
`elements are LCDs.
`
`4. The display device of claim 1 wherein:
`
`the plurality of driving connectors is operably connected
`to M row drivers;
`
`the plurality of switching connectors is operably con-
`nected to N column drivers; and
`
`wherein each of M row drivers are electrically connected
`to Q non-contiguous rows of transistors gates, and each
`of N column drivers is electrically connected to M/2
`transistor sources and each of Q number of column
`sub-drivers is connected to M/(2*Q) sources.
`5. The display device of claim 4 wherein the row drivers
`are D/A converters.
`
`6. The display device of claim 4 wherein Q is 3, and the
`number of row drivers is M/Q and these drivers are electri-
`cally connected to gates of transistors in the rows in the
`sequence: row driver 1 (rows: 1,3,5), row driver 2 (rows:
`2,4,6), row driver 3 (rows: 7,9,11), row driver row driver 4
`(rows: 8,10,12) .
`.
`. row driver M/Q (rows: M—4, M—2, M);
`and column drivers are each subdivided into three sub-
`drivers, A, B, and C, which are connected to a column source
`as follows: column 1, sub-driver A connected to source of
`transistors between rows (1,2),(11,12),(13,14) .
`.
`.
`, sub-
`driver B (3,4), (9,10), (15,16) .
`.
`.
`, sub-driver C (5,6), (7,8),
`(17,18).
`7. A method of addressing an array of M by N display
`elements comprising:
`
`providing paired transistors, which act as switches to the
`display elements,
`the paired transistors sharing a
`source, and wherein the paired transistors are in con-
`tiguous rows;
`
`delivering Q number of concurrent enabling switching
`signals to Q rows of elements through electrical con-
`nections, wherein the rows of elements are non-con-
`tiguous, and Q is a whole number 3 or greater;
`
`delivering independent signals to each enabled element in
`the non-contiguous rows; and
`
`transferring the signals to each enabled display element,
`to modulate light.
`8. The method of claim 7, further comprising:
`
`successively repeating steps (b)-(d) to another set of Q
`non-contiguous rows having elements not yet enabled,
`until the entire array has been addressed.
`9. The method of claim 7, wherein the step (b) of
`delivering Q number of enabling signals is accomplished by
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`

`US 2002/0186190 A1
`
`Dec. 12, 2002
`
`a row driver simultaneously delivering Q electrical signals
`to respective transistor gates thereby enabling the connected
`display element.
`10. The method of claim 9, wherein the step (c) of
`delivering independent signals is accomplished by N column
`drivers, each column driver consisting of Q column sub-
`drivers, each sub-driver delivering an independent signal,
`which signal is delivered electrically to the source of the
`transistor associated with a display element, wherein the
`total number of independent signals delivered is Q*N.
`11. The method of claim 7 wherein the display element is
`an LCD connected to a storage capacitor Cpix in turn
`connected to the transistor drain.
`12. The method of claim 11 wherein the transistor is an
`IGFETS.
`
`13. A device for addressing an array of M by N display
`elements comprising:
`
`paired transistors, which act as switches to the display
`elements, the paired transistors sharing a source, and
`wherein the paired transistors are in contiguous rows;
`
`means for delivering Q number of concurrent enabling
`switching signals to Q rows of elements through elec-
`trical connections, wherein the rows of elements are
`non-contiguous, and Q is a whole number 2 or greater;
`
`means for delivering independent signals to each enabled
`element in the non-contiguous rows; and
`
`means for transferring the signals to each enabled display
`element, to modulate light.
`14. The device of claim 13, wherein the means for
`delivering Q number of enabling signals is accomplished by
`a row driver simultaneously delivering Q electrical signals
`to respective transistor gates thereby enabling the connected
`display element.
`15. The device of claim 14, wherein the means of deliv-
`ering independent signals is accomplished by N column
`drivers, each column driver consisting of Q column sub-
`drivers, each sub-driver delivering an independent signal,
`which signal is delivered electrically to the source of the
`transistor associated with a display element, wherein the
`total number of independent signals delivered is Q*N.
`16. The device of claim 13 wherein the display element is
`an LCD connected to a storage capacitor Cpix in turn
`connected to the transistor drain.
`17. The method of claim 13 wherein the transistor is an
`IGFETS.
`
`SAMSUNG EX. 1003 - 8/8
`
`SAMSUNG EX. 1003 - 8/8
`
`