United States Patent
`
`[19]
`
`[11] Patent Number:
`
`6,031,513
`
`Ikeda
`
`[45] Date of Patent:
`
`Feb. 29, 2000
`
`IJS006031513[\
`
`[54] LIQUID CRYSTAL DISPLAY
`
`[75]
`
`Inventor: Naoyasu Ikeda, Tokyo, Japan
`
`[73] Assignee: NEC Corporation, Tokyo, Japan
`
`9/1993
`5.249925
`7/1994
`6—202138
`7/1996
`3479731
`8605325 11/1996
`
`Japan.
`Japan.
`JaPa11~
`Japan .
`
`Primary Exami/1er—Xiao Wu
`Attorney, Agent, or Firm—Sughrue, Mion, Zinn, Macpeak
`& S
`, PLLC
`eas
`
`.
`
`ABSTRACT
`[57]
`.
`.
`.
`.
`Cgifrfifiz alirglggrlgigfiolggrdallgl gtafi:
`filllslqfiigrlgigl
`substrate, a plurality of thin-film transistors disposed on a
`substrate near regions Where the data bus lines and the gate
`has hhes Cross at
`the right angles to each other, and a
`plurality of columns of pixel electrodes disposed on the
`substrate and connected respectively to the thin-film tran-
`sistors. The data bus lines are grouped into a plurality of sets
`of at least two data bus lines for supplying signals to the
`columns of pixel electrodes along the data bus lines. The
`data bus lines in each of the sets have respective lengths
`dlfferent from each .0ther~ Each Of the PIXC1 electrodtis 1“
`each Of the Columhs 15 Cohhected t0 One Of the data bus hhes
`in each of the sets through one of the thin-film transistors.
`
`[21] App], No; 09/019,162
`[22]
`Filed:
`Feb. 6, 1998
`_
`_
`_
`_
`_
`[30]
`Foreign Application Priority Data
`Feb. 6, 1997
`[JP]
`Japan .................................... 9—o23834
`[51]
`Int. Cl.7
`....................... .. G09G 3/36
`[52] U_s_ C]_ .......... N
`. 345/92; 345/103; 345/87
`[58] Field of Search .................................. 345/87, 88, 89,
`345/98, 99, 100, 103, 92, 93, 147, 149;
`349/54’ 74
`
`
`
`[56]
`
`References Cited
`
`US PATENT DOCUMENTS
`7/1986 Togashi et al.
`......................... 345/103
`4,602,292
`6/1989 Yasuda et al.
`........................ .. 345/103
`4,842,371
`FOREIGN PATENT DOCUMENTS
`
`5-19722
`
`1/1993
`
`Japan .
`
`8 Claims, 7 Drawing Sheets
`
` I
`
`(2m/3) -1
`
`'
`
`2m/3
`
`2C
`
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`

`
`U.S. Patent
`
`Feb. 29, 2000
`
`Sheet 1 of7
`
`6,031,513
`
`FIG.
`
`1
`
`(PRIOR ART)
`
`
`
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`

`
`U.S. Patent
`
`Feb. 29, 2000
`
`Sheet 2 of7
`
`6,031,513
`
`FIG. 2A (PRIOR ART)
`
`
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`
`U.S. Patent
`
`Feb. 29, 2000
`
`Sheet 3 of7
`
`6,031,513
`
`FIG. 3
`
`(2m/3)—1
`
`'
`
`3
`
`4
`
`'
`
`I
`
`1
`
`2m/3
`
`rn
`
`2C
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`
`U.S. Patent
`
`Feb. 29, 2000
`
`Sheet 4 of7
`
`6,031,513
`
`FIG.
`
`4
`
`
`
`TB
`
`1C
`
`‘D
`
`I
`
`I
`
`I :
`
`(m/2) -1
`
`(m/2)
`
`(m/2) +1
`
`(m/2) +2
`
`m-1
`
`m
`
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`
`U.S. Patent
`
`Feb. 29, 2000
`
`Sheet 5 of7
`
`6,031,513
`
`FIG. 5A
`
`
`
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`U.S. Patent
`
`Feb. 29, 2000
`
`Sheet 6 of7
`
`6,031,513
`
`FIG.
`
`6
`
`2A
`
`(m/2)
`
`(m/2) +1
`
`1B
`
`(m/2) +2
`
`‘C
`
`rn-1
`
`m
`
`I
`
`I
`
`ID
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`U.S. Patent
`
`Feb. 29, 2000
`
`Sheet 7 of7
`
`6,031,513
`
`FIG. 7B
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`
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`

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`6,031,513
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`1
`LIQUID CRYSTAL DISPLAY
`
`BACKGROUND OF THE INVENTION
`
`2
`digital assistant, the period of time for which the battery-
`powered unit can be used without being recharged is
`reduced.
`
`1. Field of the Invention
`
`SUMMARY OF THE INVENTION
`
`5
`
`The present invention relates to a liquid crystal display,
`It is an object Of the present invention to provide a liquid
`and more particularly to the art of reducing the power
`crystal display which reduces the electric charges flowing
`consumption of a liquid crystal display,
`into or out of a liquid crystal capacity for thereby reducing
`2. Description of the Related Art
`One conventional active matrix liquid crystal display in in the power Consumption of the liquid Crystal display‘
`which active elements are connected to respective pixels for
`Aooordihg to the Preseht ihVehtioh» a iidiiid orystai dis‘
`energizing a liquid crystal is known from “ELECTRONIC
`Piay oorhPrises a rhatrix or Paraiiei gate hiis iihes ahd
`DISPLAY” edited by sheuiehi Matsumetea pt 66_67, pub-
`parallel data bus lines disposed on a substrate, a plurality of
`lished by Ohm-sha. Aliquid crystal display described in this
`thih'hirh trahsistors tdisPosed oh the substrate hear regiohs
`literature is illustrated in FIG. 1 of the aeeempanying is where the data bus lines and the gate bus lines cross at right
`drawings.
`angles to each other, and a plurality of columns of pixel
`The lidiiid eiystal display shewh ih FIG. 1 eeihpiises a
`electrodes disposed on the substrate and connected. respec-
`matrix of data bus lines 2 and gate bus lines 3 (l_ih) which
`tively to. the thin-film transistors. The data bus lines. are
`cross at right angles to each other, and a plurality of thin-film
`grouped into a plurality of sets of at least two data bus lines
`transistors (TFTs) 4 disposed near regions where the data 20 for supplying signals to the eoluinns onpixel eleetiodes
`bus lihes 2 ahd the gate bus lihes 3 eiess eaeh ethep fer
`along the data bus lines. The data bus lines in each of the sets
`eehtiehihg eiiiiehts hewihg from the data bus lihes 2 to
`have respective lengths different from each other and each of
`pixel electrodes 1 With signals supplied from the gate bus
`the pixel electrodes in each of the columns is connected to
`lines 3. FIG. 1 shows a section of the liquid crystal display
`one oi the data bus lines in each of the sets through one of
`which corresponds to one of the data bus lines 2.
`25 the tnin'nlin transistors‘
`t
`Signals, described below, are supplied to the liquid crystal
`During aPer1°d of time When pixel eieetiedes ale seleeted
`display to energize same. FIGS. 2A and 2B are timing charts
`folteonneetlon a snoltel one of tne data bus lines in tne
`of such signals. When the gate bus lines 3 are successively
`period of one naine> sinee tne area of the data. bus line is
`selected and turned on at given periods, as shown in FIG.
`slnallel> tne quantity of eleetlle enalges nowlng into and out
`2A’ a TFT 4 Connected to the selected gate bns line 3 is 30 of the data bus line is less than in the conventional liquid
`turned on’ Writing a signal from the data bus line 2’ which
`crystal display. If each of the sets has two data bus lines and
`is being energized by an alternating_enrrent signal with
`one of the data bus lines has a length which is half the length
`respect to a eenfrenting eleetrede Voltage’ into the eerre_
`of the other data bus line, then since the area of the shorter
`spending pixel electrode 1 (see FIG. 2B). This Operation is
`data bus line is half the area of the longer data bus line, the
`repeated from the first gate bus line 3 to the mth gate bus line 35 total quantity of eieetlie enalges nowing into and out of the
`3 for thereby completing the display of one frame. When one
`snoltel data bus line is tnalt tne total duantltytln tne eonVen'
`cycle of scanning up to the mth gate bus line 3 is finished,
`tlenai lidnld eiystal dlspiaytdnling tne period of time in
`another eyele of seanning is started from the first gate bus
`which a signal is being supplied to the shorter data bus line.
`line 3.
`Since the power consumption of the liquid crystal display
`In the conventional liquid crystal display, since each time 40 ih this Period is iess thah the Power oohsiirhPtioh or the
`a gate bus line 3 is turned on a signal voltage is applied to
`oohVehtiohai
`iidiiidt orystai disPiaY> tthe totai PoWer ‘ooh’
`the data bus line 2, the total quantity of electric charges
`siiiiiptioii of tile iidiiid eiystai display is iediieed-iii tile iidiiid
`supplied to and removed, for example, from one data bus
`orystai disPiaY aooordihg to the Preseht ihVehtioh is ihoor'
`line during a period of one frame when a solid black image
`Poiated iii a Personal digital tastsistaiits> tiieii the Period of
`is displayed on the entire display panel is expressed by:
`45 time for which the personal digital assistants can be used is
`prolonged.
`
`The above and other objects, features, and advantages of
`Q am
`the present invention will become apparent from the fol-
`i
`lowing description with reference to the accompanying
`where Qi represents the amount of electric charges required
`for one data bus line 2 and m represents the number of gate 50 drawings which illustrate examples of the present invention.
`bus lines.
`
`Since the entire quantity of electric charges for the entire
`disPiaY Pahei is oaioiiiated by rhiiitiPiYihg the aooVe totai
`quantity of electric charges by the number of data bus lines,
`the calculated entire quantity of electrictcharges is large 55
`enough to increase the power consumption of the liquid
`crystal display. Because the above charges are proportional
`to the area of the data bus lines, the power consumption
`increases as the size of the data bus lines increases even if
`the number of pixels used remains the same. Consequently,
`even if the number of pixels nsed remains the same’ as the
`display panel size increases, the electric power required to
`energize the liquid crystal capacity increases though the
`electric energy consumed by a signal processing system
`does not increase.
`Therefore, if the conventional liquid crystal display is
`incorporated in a battery-powered unit such as a personal
`
`60
`
`65
`
`BRiEF DESCRiiaTiON OF THE DRAWiNGS
`FIG. 1 is a circuit diagram of a conventional liquid crystal
`display;
`FIGS. 2A ahd 2B are tiihihg Charts of signals iii the
`eehvehtiehai hdiiid Crystal display;
`.
`.
`.
`.
`.
`.
`.
`FiG'. 3 is a Ciiciiit diagram of a iidiiid Ciyetai disiiiay
`accoidiiig to a iaist diiibddiiiieiit Oi the iiiteseiit iiiveiitidii’
`FiG'. 4 is a elleult dlaglaln of a liquid elystal display
`according to a second embodiment of the present invention;
`FIGS 5A ahd 5B are tirhihg oharts or sighais ih a iidiiid
`erystai disPiaY aooordihg to a third erhhodirheht or the
`Preseht ihVehtioh;
`FIG. 6 is a circuit diagram of a liquid crystal display
`according to a fourth embodiment of the present invention;
`and
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`6,031,513
`
`3
`FIGS. 7A and 7B are timing charts of signals in a liquid
`crystal display according to a fifth embodiment of the
`present invention.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`As shown in FIG. 3, a liquid crystal display according to
`a first embodiment of the present invention has a matrix of
`pixel electrodes 1 providing a vertical column of m dots and
`a horizontal row of n dots on a substrate. The liquid crystal
`display also has vertical data bus lines 2A, 2B, 2C and
`horizontal gate bus lines 3 (l—m), and a plurality of TFTs 4
`disposed as switching elements near regions where the data
`bus lines 2A, 2B, 2C and the gate bus lines 3 cross each
`other. FIG. 3 shows a section of the liquid crystal display
`which includes a column of TFTs 4 and a column of pixel
`electrodes 1 along the data bus lines. The TFTs 4 have
`respective gate electrodes connected to the gate bus lines 3,
`respective source electrodes connected to the data bus lines
`2A, 2B, 2C, and respective drain electrodes connected to the
`pixel electrodes 1. When the gate bus lines 3 are selected,
`signals from the data bus lines 2A, 2B, 2C are supplied to the
`pixel electrodes 1. In FIG. 3, the pixel electrodes 1 and the
`data bus lines 2A, 2B, 2C are shown as blank blocks
`represented by solid lines.
`Operation of the liquid crystal display according to the
`first embodiment will be described with reference to FIG. 3.
`
`During a period of time in which the first through (m/3)th
`gate bus lines 3 are selected, a signal is supplied to the data
`bus line 2A whose length is ‘/3 of the length of the data bus
`line 2C for applying a voltage to the corresponding pixel
`electrodes 1. During a period of time in which (m/3) gate bus
`lines, i.e., the {(m/3)+1}th through {(m/3)><2}th gate bus
`lines 3, are selected, a signal is supplied to the data bus lines
`2B whose length is 2/3 of the length of the data bus line 2C
`for applying a voltage to the corresponding pixel electrodes
`1. During a period of time in which (m/3) gate bus lines, i.e.,
`the {(2m/3)+1}th through mth gate bus lines 3, are selected,
`a signal is supplied to the data bus line 2C for applying a
`voltage to the corresponding pixel electrodes 1.
`When signals are applied to the pixel electrodes over the
`display panel, the sum of electric charges supplied to one
`vertical column during the period of one frame is expressed
`by:
`
`(Q/3)><(m/3)+{(%)><Q}><(m/3)+Q>< (m/3)=(Z/3)><m><Q
`
`where Q represents electric charges supplied to the data bus
`line 2C while one gate bus line is being selected. Since the
`electric charges m><Q are consumed when the pixel elec-
`trodes are charged and discharged according to the ordinary
`process,
`the liquid crystal display according to the first
`embodiment has an equivalent displaying capability simply
`by consuming electric charges which are 2/3 of the electric
`charges m><Q.
`three data bus lines are
`In the first embodiment,
`employed. However, the liquid crystal display according to
`the first embodiment may have two or more data bus lines
`which are different in length from each other. While the gate
`bus lines are selected successively downwardly in the above
`process of operation, they may be selected in any of various
`other sequences. The lengths of the data bus lines 2A, 2B,
`2C have a ratio of 1:2:3 in the illustrated embodiment.
`
`However, one of the data bus lines may be of the longest
`length, and the other data bus lines may be shorter than the
`longest data bus line.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`4
`FIG. 4 shows a liquid crystal display according to a
`second embodiment of the present invention.
`As shown in FIG. 4, the liquid crystal display according
`to the second embodiment has a matrix of pixel electrodes
`1 providing a vertical column of m dots and a horizontal row
`of n dots on a substrate. The liquid crystal display also has
`vertical data bus lines 2A, 2B and horizontal gate bus lines
`3 (l—m), and a plurality TFTs 4 disposed as switching
`elements near regions where the data bus lines 2A, 2B and
`the gate bus lines 3 cross each other. FIG. 4 shows a section
`of the liquid crystal display which includes a column of
`TFTs 4 and a column of pixel electrodes 1 along the data bus
`lines. The TFTs 4 have respective gate electrodes connected
`to the gate bus lines 3, respective source electrodes con-
`nected to the data bus lines 2A, 2B, and respective drain
`electrodes connected to the pixel electrodes 1. When the gate
`bus lines 3 are selected, signals from the data bus lines 2A,
`2B are supplied to the pixel electrodes 1. In FIG. 4, the pixel
`electrodes 1 and the data bus lines 2A, 2B are shown as
`blank blocks represented by solid lines.
`Operation of the liquid crystal display according to the
`second embodiment will be described with reference to FIG.
`
`4. During a period of time in which the first through (m/2)th
`gate bus liens 3 are selected, a signal is supplied to the data
`bus line 2A whose length is 1/2 of the length of the data bus
`line 2B for applying a voltage to the corresponding pixel
`electrodes 1. During a period of time in which (m/2) gate bus
`lines, i.e., the {(m/2)+1}th through mth gate bus lines 3, are
`selected, a signal is supplied to the data bus line 2B for
`applying a voltage to the corresponding pixel electrodes 1.
`When signals are supplied to the pixel electrodes over the
`display panel, the sum of electric charges supplied to one
`vertical column during the period of one frame is expressed
`by:
`
`(Q/2)><(m/2)+Q>< (m/2)=(%)><m><Q
`
`where Q represents electric charges supplied to the data bus
`line 2B while one gate bus line is being selected. Since the
`electric charges m><Q are consumed when the pixel elec-
`trodes are charged and discharged according to the ordinary
`process, the liquid crystal display according to the second
`embodiment has an equivalent displaying capability simply
`by consuming electric charges which are 3A: of the electric
`charges m><Q.
`two data bus lines are
`In the second embodiment,
`employed because if the number of data bus lines is
`increased, the display area per pixel is reduced because the
`area of the increased data bus lines is not capable of
`displaying images in transmissive liquid crystal displays.
`With the two data bus lines, it is possible to achieve the
`object of the present invention while preventing the display
`area per pixel from being reduced.
`A liquid crystal display according to a third embodiment
`will be described with reference to FIGS. 5A and 5B. The
`
`liquid crystal display according to the third embodiment has
`two data bus lines, and is identical to the liquid crystal
`display shown in FIG. 4. FIGS. 5A and 5B are timing charts
`of signals in the liquid crystal display according to the third
`embodiment of the present invention.
`The liquid crystal display according to the third embodi-
`ment operates as follows: As shown in FIG. 5A, the first and
`{(m/2)+1}th gate bus lines are first selected at the same time.
`At this time, a signal voltage is applied from the data bus
`lines 2A, 2B to the pixel electrodes 1A, 1C, energizing a
`liquid crystal with a predetermined voltage (see FIG. 5B).
`The above cycle of operation is repeated until the gate bus
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`5
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`6
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`6,031,513
`
`lines are successively scanned up to the (m/2)th and mth gate
`bus lines to apply the voltage up to the pixel electrodes 1B,
`1D for thereby displaying one frame.
`According to the third embodiment, the period of time
`required to display one frame may be reduced to one half by 5
`applying the voltage simultaneously to two pixel electrodes’
`so that the power consumption of a signal processing circuit
`(not shown) can be lowered. Furthermore, the period of time
`required to apply the voltage may be doubled to provide
`room for designing the device. For example, the size of the 10
`thnpfiim transistors may be reduced to one half.
`when Signals are Supplied to the pixel electrodes Over the
`display panel, the sum of electric charges supplied to one
`vertical column during the period of one frame is expressed
`by:
`
`15
`
`(m/2)th gate bus lines 3 are selected, the switch 6 is operated
`to connect the data driver IC output stage 5 to the data bus
`line 2A. In this period, an image signal is supplied only to
`the data bus line 2A. During a period of time in which (m/2)
`gate bus lines, i.e., the {(m/2)+1}th through mth gate bus
`t
`t
`.
`lines 3,. are selected, the switch 6 is operated to connect the
`daia drivertic output stage 5 lo ihe data bus line 23 iii this
`ggiod’ ah image Signal is Supplied ohly to the data bus lihe
`‘
`.
`.
`.
`.When Signals are Supplied to the pixel electrodes Over the
`display panel, the sum of electric charges supplied to one
`hlertical column during the period of one frame is expressed
`y‘
`
`(Q/2)><(m/2)+Q><(m/2)=(%)><m><Q
`where Q represents electric charges supplied to the data bus
`l11I1Cl2l3 wlhile one gage bus line is beiinghseleclted. Sirlcelthe
`
`(Q/2)X(m/2)+QX(m/2)=(%)XmXQ
`oto
`line 2B while one gate bus line is being selected. Since the 20 process’ the liquid crystal display according to the fourth
`eleeirie eharges rhXQ are eohsurhed Wheh the pixel elee'
`embodiment has an equivalent displaying capability simply
`trodes are charged and discharged according to the ordinary
`by consuming electric charges which are % of the electric
`process, the liquid crystal display according to the third
`charges rnXQ.
`embodiment has an equivalent displaying capability simply
`A liquid crystal display according to a fifth embodiment
`ply eohsurhigg eleeirie eharges which are 3”‘ or the eleeirie 25 will be described with reference to FIGS. 7A and 7B. The
`c arges m><
`.
`~
`~
`~
`~
`~
`~
`hr the third crrrhcdirhchtc twc data has hrrcs
`crhpicycd.
`l3‘i‘§§c§lytZi?fiedf?§i?§§§Zi’§iidrisgplaiytslhofxisfhhirii‘§1bé’.d§.”E1“é§S.
`However’ the liquid erysial display aeeordihg lo the third
`7A and 7B are timing charts of signals in the liquid crystal
`embodiment may have more than two data bus lines which
`display according to the fifth embodiment of the present
`are different in length from each other. While the gate bus 30 invention.
`lines are selected successively downwardly in the above
`The liquid crystal display according to the fifth ernbodi_
`proeess or operaiioha they may be selected iii ahy or Various
`ment operates as follows: As shown in FIG. 7A, the first and
`other seduehees The lehgihs or the daia pus lihes 2A’ 2B
`{(m/2)+1}th gate bus lines are first selected at the same time.
`have a ratio or i2 iii the third erribodirhehi' Howevera one
`The period of time in which the gate bus lines are selected
`of the data bus lines may be of the longest length, and the 35 has to be twice the period of time in the ordinary line
`other data bus line may be shorter than the longest data bus
`sequential scanning process. At this time’ the switch 6 is
`lines.
`~
`FIG; 6 shows a hdhid crystal display according to a fourth
`353513 f§1§3iX‘?§iai§Zr‘3§£ao‘li§§§2 i§h?$ifii§ihZ§aagtif§§£§§
`erribodirhehi or the present invention‘
`in the gate bus lines are selected, for thereby applying a
`As showh ih FiG‘ 6’ the liquid erysial display aeeordihg 40 given voltage to the data bus line 2A. In the remaining half
`to the fourth embodiment has a matrix of pixel electrodes 1
`period of time’ the switch 6 is operated to connect the data
`providing a Veriieal eolurhh or iii ‘dots arid a horizohial row
`driver IC output stage 5 to the data bus line 2B. The switch
`of n. dots on a substrate. The liquid crystal display alsorhas
`6 is operated by the signal SWG. Since the first gate bus line
`vertical data bus lines 2A, 2B and horizontal gate bus lines
`has continuously been turned on’ the voltage is being applied
`3 (l_rh)> arid a plurality or TFTs 4 disposed as swiiehihg 45 from the data bus line 2A to the pixel electrode 1A. Since the
`elements hear regions Where the data bus lilies 2A> 2B arid
`capacitive component of the data bus line 2A is sufficiently
`the gate bus lines 3 cross each other. FIG. 6 shows a section
`large as compared with the capacitive component of the
`or the liquid erysial display which iheludes a eolurhh or
`pixel electrode 1A, the given voltage can be applied to the
`TFTs 4 and a column of pixel electrodes 1 along the data bus
`pixel electrode IA even when the data bus line 2A is
`lines. The TFTs 4 have respective gate electrodes connected 50 disconnected from the data driver lc output stage 5. The
`to the gale bus lilies 3a respeeiive souree eleeirodes eon‘
`voltage applied to the data bus line 2B is applied to the pixel
`nected to the data bus lines 2A, 2B, and respective drain
`electrode 1C’ and when the two gate bus lines are not
`electrodes connected to the pixel electrodes 1. When the gate
`selected for scanning a next gate bus line’ the desired voltage
`bus lines 3 are selected, signals from the data bus lines 2A,
`is applied to the pixel electrodes IA’ 1C (see FIG. 7A). The
`2B are supplied to the pixel eleeirodes 1' iii FiG' 6a the pixel 55 above cycle of operations is repeated until the gate bus lines
`eleeirodes l arid the daia pus lihes 2A’ 2B are showh as
`are successively scanned up to the (m/2)th and mth gate bus
`blank blocks represented by solid lines. A data driver IC
`lines to apply the voltage up to the pixel electrodes 1B’ 1D
`output stage 5 is provided for each set of the data bus lines
`for thereby displaying one frame.
`2A’ 2B‘ A swiieh 6 has ah ihpui ierrhihal eohheeied lo the
`When signals are applied to the pixel electrodes over the
`data driver IC output stage 5 and a pair of output terminals 60 display panel’ the sum of electric charges supplied to one
`eohheeied respeeiively lo the daia pus lihes 2A’ 2B‘ Ah
`vertical column during the period of one frame is expressed
`output signal from the data driver IC output stage 5 is
`by:
`supplied selectively to the data bus lines 2A, 2B by the
`switch 6 which is operated by the level of a signal SWG.
`Operation of the liquid crystal display according to the 65
`fourth embodiment will be described below with reference
`
`to FIG. 6. During a period of time in which the first through
`
`(Q/2))‘rm/2)+QX(m/2)=(%)XmXQ
`where Q represents electric charges supplied to the data bus
`line 2B while one gate bus line is being selected. Since the
`
`SEC v. Surpass Tech, |PR2015—OO887
`SAMSUNG EX. 1030 — 11/12
`
`SEC v. Surpass Tech, IPR2015-00887
`SAMSUNG EX. 1030 - 11/12
`
`

`
`6,031,513
`
`8
`electrodes in each of said columns being connected to
`one of said data bus lines in each of said sets through
`one of said thin-film transistors.
`
`7
`electric charges m><Q are consumed when the pixel elec-
`trodes are charged and discharged according to the ordinary
`process, the liquid crystal display according to the fourth
`2. A liquid crystal display according to claim 1, wherein
`embodiment has an equivalent displaying capability simply
`said data bus lines are grouped into a plurality of sets of two
`by consuming electric charges which are 3A: of the electric 5
`data bus lines.
`charges m><Q.
`3. A liquid crystal display according to claim 1, wherein
`In the fifth embodiment, two data bus lines are employed.
`the gate bus lines connected to gate terminals of said thin
`However, the liquid crystal display according to the fifth
`film transistors connected to different data bus lines in each
`embodiment may have more than two data bus lines which
`are different in length from each other. While the gate bus 10 of said sets are turned on in an overlapping period of time.
`lines are selected successively downwardly in the above
`4. A liquid crystal display according to claim 3, wherein
`process of operation, they may be selected in any of various
`said data bus lines are grouped into a plurality of sets of two
`other sequences. The lengths of the data bus lines 2A, 2B
`data bus lines.
`have a ratio of 1:2 in the fifth embodiment. However, one of
`5. A liquid crystal display according to claim 1, further
`the data bus lines may be of the longest length, and the other 15 comprising a data driver IC output stage and a switch having
`data bus line may be shorter than the longest data bus line.
`an input terminal connected to said data driver IC output
`While preferred embodiments of the present invention
`stage and a plurality of output
`terminals connected to
`have been described using specific terms, such description is
`different data bus lines in each of said sets, for supplying a
`for illustrative purposes only, and it is to be understood that
`signal from said data driver IC output stage selectively to
`changes and variations may be made without departing from 20 said different data bus lines in each of said sets.
`the spirit or scope of the following claims.
`6. A liquid crystal display according to claim 5, wherein
`What is claimed is:
`said data bus lines are grouped into a plurality of sets of two
`1. A liquid crystal display comprising:
`data bus lines.
`a Substrate;
`7.
`liquid crystal display according to claim 1, further
`a matrix of parallel gate bus lines and parallel data bus 25 Comprlslng a data dnver IC Output S.tage and a.SW1tCh havmg
`lines disposed on Said Substrate;
`an input terminal connected to said data driver IC output
`.
`.
`.
`.
`.
`stage and a plurality of output
`terminals connected to
`a pluramy of thH.1'fi1m translstffis d1Sp0Sed.0n Sald Sub"
`different data bus lines in each of said sets, for supplying a
`Straw near. reglons Where Sald data bus hues and sad
`signal from said data driver IC output stage selectively to
`gate bus hues Cross each Other; and
`30 said different data bus lines in each of said sets, and the gate
`aphlrahty Of eehlmns 0fPiXe1 electrodes di5P05ed 0“ Said
`bus lines connected to gate terminals of said thin-film
`Substrate and eenneeted re5PeetiVe1Y to Said thimfilm
`transistors connected to different data bus lines in each of
`tFaI1SiSt0TS;
`said sets are turned on in an overlapping period of time.
`said data bus lines being grouped into a plurality of sets
`8. A liquid crystal display according to claim 7, wherein
`of at least two data bus lines for supplying signals to the 35 said data bus lines are grouped into a plurality of sets of two
`data bus lines.
`columns of pixel electrodes along said data bus lines,
`said data bus lines in each of said sets having respective
`lengths different from each other, each of said pixel
`
`SEC v. Surpass Tech, |PR2015—OO887
`SAMSUNG EX. 1030 — 12/12
`
`SEC v. Surpass Tech, IPR2015-00887
`SAMSUNG EX. 1030 - 12/12