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`571-272-7822
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`IPR2015-00158, Paper No. 34
`IPR2015-00159, Paper No. 45
`IPR2015-00163, Paper No. 51
`March 4, 2016
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`RECORD OF ORAL HEARING
`UNITED STATES PATENT AND TRADEMARK OFFICE
`- - - - - -
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`- - - - - -
`APPLE, INC, HTC CORPORATION, HTC AMERICA, INC., SAMSUNG
`ELECTRONICS CO. LTD., SAMSUNG ELECTRONICS AMERICA,
`INC., AMAZON.COM, INC., SONY CORP., SONY ELECTRONICS
`INC., SONY MOBILE COMMUNICATIONS AB, SONY MOBILE
`COMMUNICATIONS (USA) INC., LG ELECTRONICS, INC., LG
`ELECTRONICS USA, INC., and LG ELECTRONICS MOBILECOMM
`USA, INC.,
`Petitioners
`vs.
`MEMORY INTEGRITY, LLC
`Patent Owner
`- - - - - -
`Case Nos. IPR2015-00158, IPR2015-00159 and IPR2015-00163
`Patent No. 7,296,121
`Technology Center 2100
`- - - - - -
`
`Oral Hearing Held: Monday, February 8, 2016
`
`
`Before: JENNIFER S. BISK, NEIL T. POWELL, KERRY
`BEGLEY, Administrative Patent Judges
`
`The above-entitled matter came on for hearing on Monday,
`February 8, 2016 at the U.S. Patent and Trademark Office, 600 Dulany
`Street, Alexandria, Virginia in Courtroom A, at 10:00 a.m.
`
`
`
`APPEARANCES:
`ON BEHALF OF THE PETITIONERS
`
`APPLE, SAMSUNG, HTC, AND AMAZON:
`
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`W. KARL RENNER, ESQ.
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`ROBERTO J. DEVOTO, ESQ.
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`DAVID L. HOLT, ESQ.
`
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`Fish & Richardson P.C.
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`
`1425 K Street, N.W.
`
`
`11th Floor
`
`
`Washington, D.C. 20005-3500
`
`
`202-783-5070
`
`
`renner@fr.com
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`ON BEHALF OF PETITIONER SONY:
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`WALTER E. HANLEY, JR., ESQ.
`Kenyon & Kenyon LLP
`One Broadway
`New York, New York 10004-1007
`212-425-7200
`whanley@kenyon.com
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`APPEARANCES (Continued):
`ON BEHALF OF THE PETITIONER LG:
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`JAY GUILIANO, ESQ.
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`RYAN M. MURPHY, ESQ.
`
`
`Novak Druce Connolly Bove & Quigg LLP
`
`
`1875 Eye Street, N.W.
`
`
`Eleventh Floor
`
`
`Washington, D.C. 20006
`
`
`202-333-7111
`
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`jayguiliano@novakdruce.com
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`
`
`
`ON BEHALF OF THE PATENT OWNER:
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`
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`JONATHAN D. BAKER, ESQ.
`MICHAEL SAUNDERS, ESQ.
`Farney Daniels, P.C.
`
`411 Borel Avenue, Suite 350
`San Mateo, CA 94402
`
`424-268-5210
`jbaker@farneydaniels.com
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`P R O C E E D I N G S
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`(10:00 a.m.)
`JUDGE POWELL: Please be seated. Good
`morning. This is a consolidated hearing for the following
`three cases: IPR2015-00158, IPR2015- 00159, and
`IPR2015- 00163. IPR2015-01353 has been joined with
`IPR2015- 00163. And IPR2015-01376 has been joined with
`IPR2015- 00159.
`Each case involves U.S. Patent Number 7,296,121
`B2. In the hearing room with me I have Judge Bisk and Judge
`Begley.
`
`Can counsel please state your names for the
`record? We will start with Patent Owner, I suppose.
`MR. BAKER: Thank you, Your Honor, Jonathan
`Baker on behalf of Patent Owner, Memory Integrity.
`MR. SAUNDERS: Michael Saunders of Farney
`Daniels on behalf of Patent Owner, Memory Integrity LLC.
`MR. RENNER: Karl Renner of Fish & Richardson
`on behalf of Apple, Samsung, HTC, and Amazon.
`MR. DEVOTO: Rob Devoto on behalf of Apple,
`Samsung, HTC, and Amazon.
`MR. HANLEY: Walter Hanley of Kenyon &
`Kenyon for Petitioner Sony.
`JUDGE POWELL: Okay. With that, I will note
`that, consistent with our hearing order, that the Petitioners
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`will have 120 minutes of argument time. And the Patent
`Owner will also have 120 minutes of argument time.
`This morning we will hear arguments related to the
`original claims of the patent. After that, we will take a break
`for lunch. And then after lunch we will hear arguments
`regarding Patent Owner's motions to amend.
`So we will start with Petitioners presenting their
`case regarding the original claims of the patent. Petitioners
`may reserve time. After the Petitioners' arguments regarding
`the original claims of the patent, the Patent Owner will
`respond. And Petitioners then may use any remaining time to
`respond to Patent Owner's presentation.
`One other housekeeping item, during your
`presentations make sure to identify each demonstrative exhibit
`clearly and specifically. For example, you can refer to it by
`slide or screen number.
`With that, do we have any questions before we
`start? As I said, we will start with Petitioners.
`I guess I do have one question for Petitioners.
`MR. RENNER: Yes, Your Honor.
`JUDGE POWELL: Would you like to reserve
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`time?
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`MR. RENNER: Your Honor, it is an interesting
`proceeding. It is unusual.
`JUDGE POWELL: Right.
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`MR. RENNER: So, Your Honor, we're thinking of
`it as having two sessions, but there will be some fluidity, of
`course, between the two.
`JUDGE POWELL: Right.
`MR. RENNER: We're thinking that we would like
`to reserve roughly 30 minutes for the motion to amend
`section.
`
`JUDGE POWELL: Okay.
`MR. RENNER: And roughly 30 minutes for our
`redirect in the original claims section.
`JUDGE POWELL: Okay. So you are thinking 60
`minutes on the case-in-chief?
`MR. RENNER: That's right.
`JUDGE POWELL: Okay. Thank you.
`MR. RENNER: If I may please, counsel would
`like to approach the bench and give you copies of the slides,
`if you would like to have them in paper.
`JUDGE POWELL: Certainly. That would be
`great. Whenever you are ready then.
`MR. RENNER: May it please the Board, my name
`is Karl Renner. I'm here with Rob Devoto and David Holt,
`you just mentioned. And we're here on behalf of, as I
`mentioned, Apple, Samsung, HTC, and Amazon.
`Client representatives are here from the
`companies, from Apple and Samsung, in attendance as well.
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`
`Your Honor, at the outset we wanted to -- slide 2,
`please -- look at the structure of the hearing organizationally.
`We will focus on the Pong and the Koster reference in our
`case-in-chief against the original claims.
`You will see the slides have in them sections -- a
`section on claim construction as well. Our intent is to feather
`that into the conversation as it relates to our coverage in each
`of Pong and Koster.
`Today, just as a prefatory matter, we note that
`most of the arguments you are going to hear, they are
`arguments you have already heard. They were arguments that
`were presented in the Patent Owner preliminary response,
`particularly as it relates to "states" as we will get into, so it
`may be that you are hearing things that sound familiar to you.
`That will encourage that you have already heard most of those
`arguments. And we will remind Your Honors of exactly how
`that went when you did.
`Next slide, please.
`Briefly the '121 patent, we thought it would make
`sense to just to have literally two slides, one to the claim and
`one to the structure, to orient this morning. Main memory is
`shared by multiple processors in the '121 patent.
`And those processors, they maintain cache for the
`purpose of speeding the requests and writes to memory that
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`might otherwise occur slowly in the memory. Not atypically,
`along with speed, the cost is reliability.
`And when you have multiple copies of a piece of
`data that are being maintained in these caches, you have to
`keep track of where those copies are and exactly what the
`state of them is.
`The solution lies in cache coherence protocols.
`And these aren't new. And they are not truly the subject of
`today's conversation, other than to say this is the backdrop
`against which we are talking.
`And in those cache coherence protocols, what we
`see is there were shared versions of buses and protocols that
`were used where processors would each themselves maintain a
`directory, with a heavy load they would have to monitor the
`bus line, the shared bus line, that is, and identify all
`transactions to keep informed their directory, so that they can
`later direct requests to specific cache versions of the content
`that was otherwise in memory.
`This is, again, fairly inefficient and not scalable.
`So what we have before us is a patent and a variety of prior
`art that instead relates to a directory-based protocols. And a
`directory-based protocol, what we have is a cache coherence
`controller that maintains a map, if you will, of where the
`cached copies are in the shared memory system.
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`So that when a request comes in, be it a read or a
`write, you can direct that to the appropriate cached versions
`and not require every processor throughout the system to
`maintain its own structure.
`It is more scalable. And, most importantly, it
`requires there be a directory of some form and also some
`protocol logic.
`Next slide, please.
`Claim 1 we thought representatively we would talk
`about just for a moment and show you that in red the heart of
`the claim is the probe filtering unit. And at the heart of the
`claim, it receives and selectively transmits things called
`probes. The word probe is used frequently. Really think of a
`memory transaction. This is the read or the write.
`In green we see how that filtering is going to
`occur, how is it that the probe filtering unit is going to
`transmit probes to only select ones of the cache memory.
`Well, it is going to, in green we see, rely on states that are
`associated with the cache memory.
`In blue we see the context for this being done.
`And this is that the processors are themselves connected,
`somewhere between them is an interconnect network of
`point-to-point architecture.
`Next slide, please.
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`
`So without further adieu, getting into Pong, what
`we see is four issues that were briefed on the record; that is,
`states, probes, accumulating, and programmed were on the
`record said to distinctively distinguish the claims.
`We're going to talk today about states,
`accumulating, and programming; leaving probes to the written
`record, as we think that that suffices.
`So in slide 23 as we're talking about here, we have
`the overview in the first instance, and just a slide or two on
`Pong to orient ourselves. And then we will get into each of
`the states, probes, and -- states, accumulating, and
`programming.
`Slide 24, please.
`Here we have clips from the cogent summary that
`was given to us in the Institution decision of what Pong
`represents. At a high level, Pong is, as the first clip
`indicates, it is a multi-processor system with cache coherence;
`similar to what we have talked about.
`The second clip tells us that the processors in the
`Pong system, they are interconnected by, indeed,
`point-to-point links in a memory controller. And the third
`clip tells that there is a directory that is maintained in Pong.
`And we will see that that directory has, as you can see here, a
`presence bit vector of the type we're talking about, a map that
`allows us to know where those cached copies reside.
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`Next slide, please. This is slide 25.
`In slide 25 we look at a commonly referenced
`figure that is annotated from within Pong to show how the
`memory transactions navigate within the Pong architecture.
`Here in specific on the left upper side we have got in blue
`processor P0, and we have got numbers 1 through 7 inserted
`into the drawing -- this is from the record, of course -- that
`track what the Pong reference described as that memory
`transaction went through.
`And Dr. Horst used these numbers to describe
`exactly what was happening at each one of these stages. So
`his declaration can be consulted for a more detailed review,
`but for now I will just leave it at arrow 1 takes the memory
`transaction from the processor, that blue box in the upper left
`processor 0, where we initiate or we issue a request, and down
`to the green box, which is the memory controller, step 2
`enumerated, to the directory filter in purple in item 400 in the
`middle of that memory controller, that is arrow 3.
`And at arrow 4 we see that it escapes the memory
`directory filter and goes to the interconnect line. It is called
`here a switch, 410. That is the parallel line, the horizontal
`line below item 4.
`And from there it is being directed to that
`processor P1 and the processor P2. How? The presence bit
`vector that we talked about. Clearly in this example you can
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`see that it has been identified that each of these two
`processors has a cached copy of that, which is in the solicited
`memory.
`
`So when the transaction comes in we direct the
`traffic to them. Perhaps most notable here is there is no line
`to P3. That tells us about the selectivity that the memory
`controller, and importantly the directory filter, exacts. That
`transaction goes only to P1 and P2.
`Next slide, please.
`If we go to slide 26, in fact, we see the return
`path. Here we illustrate with just respect to one of the
`message transactions, the probes that come through, but we
`see what processor 1 does with it. And we again use this
`figure, which comes out of Dr. Horst's declaration, to show
`that the path goes from that processor P1 down to the
`interconnect switch that is shown at 422 at item 10 and
`returning up to a buffer that holds multiple pieces of data that
`is between arrow 10 and 11, so that the ultimate responses can
`all reach the processor that made the memory transaction in
`the first instance.
`Now, mind you, as we will later discuss in greater
`detail, Pong, it doesn't contemplate intelligence at the
`recipient, that P1 processor, to make intelligent decisions
`about what to do with a received request or a probe. Instead,
`if it receives a probe and it has a data copy, it replies.
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`So we will talk about the fact that when multiple
`of these requests go out, which they do, Dr. Horst tells us
`almost always they do, that almost always we're going to have
`responses, multiple of them coming back from those
`processors in the field.
`Next slide, please.
`So this is slide 27. And slides 27 through 29,
`these really provide a mapping that goes between the claimed
`language and the drawing structure we have here, very briefly
`just pointing out the processing nodes in blue are mapped to
`the blue text of the claim, that the cache memory in yellow is
`mapped to the cache memory in the processing nodes.
`Slide 28, please.
`The memory controller here is representative of
`probe filtering unit. In fact, it has got a directory at its center
`in purple which identifies with the caching -- sorry -- the use
`of states to identify where to select those memory transactions
`among the various different cached copies.
`Next slide, please.
`In slide 29 we, again, consult the enumerated
`version of this figure with 1 through 7, arrows 1 through 7
`tracking to show you that the received probe, that is the
`received probe that comes into that directory filter or the
`PFU, probed filtering unit, that it is used to send out a select
`number of probes to select of the processing nodes.
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`Next slide, please.
`Slide 30 we just use to remind Your Honors that
`you have already come to this conclusion. You have already
`seen this mapping. And, in fact, you have applied it in your
`Institution decision, so this is for your reference is all.
`Now we turn to Pong and actually "states." Next
`slide, please, 31.
`Again, to remind you, we will hit states before
`accumulating and programmed. Slide number 32, please.
`In slide 32 we see that there are two different
`issues that relate to states. One is a construction issue. The
`other is a prior art application issue.
`The first of them is that Memory Integrity would
`like you to revisit the construction that you made in the
`Institution decision. It wants you to narrow "states" from the
`plain meaning of the word "states" to something that
`contextually requires a very specific set of states.
`We will talk about why we don't believe that that's
`appropriate. The next is if Memory Integrity were to achieve
`such a narrowing, they argue that Pong is distinguished by
`that kind of interpretation.
`Again, when we look at Pong, we see quite
`differently that Pong does, indeed, apply even to the narrowed
`version of "states."
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`Now, mind you, in saying that, there is no dispute.
`Pong applies, undisputedly, to the current construction. The
`only dispute about Pong's application comes about if you
`change your mind on the construction.
`With that, let's look at that construction, please.
`
`Slide 7.
`
`As indicated earlier, our slides are, again,
`organized so that the construction lies differently than where
`we have Pong. So we're going back to slide 7 and looking at
`this construction.
`And you will see in the context of the claim that
`the probe filtering information is representative of what
`states, particular kinds of states, states associated with a very
`large -- it is a very broad term -- with cache memories,
`associated with cache memories.
`Okay. So what did we think this means? Well, we
`think this means, as indicated by the table that is here on slide
`7, that it is not a bounded term. "States" is a very broad term.
`"States" includes things like the presence of the data that's on
`the cache memories.
`JUDGE BISK: Can I ask a question? I am a little
`confused about -- it seems to me that there is two different
`parts of the claim construction we're talking about. I am a
`little confused about how they are related.
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`First of all, I am not quite clear what it means to
`be a cache-coherency state. And since in your petition, you
`seem to say that it doesn't need to be a cache-coherency state,
`so I am wondering if you know what a cache-coherency state
`is.
`
`Because, you know, there are those two examples
`in the patent, the 4 and the 5, the MOESI, and then I can't
`remember the other one.
`MR. RENNER: MESI.
`JUDGE BISK: But then there is the second part
`where presence is not a state, which seems kind of like an
`extra limitation.
`So those are bothering me. I am not sure if they
`are the same limitation or separate. If they are the same, I
`guess I need to know more about what cache-coherency state
`actually means.
`But the thing that is really confusing me is in the
`cache- coherency states, at least the one with the four in the
`patent, lists one of the four states as being an invalid state.
`And could we talk about what is the difference between
`presence that we're talking about all over the place here, you
`talked about it in your petition, and the Patent Owner has been
`talking about it a lot, what is the difference between that
`invalid state that clearly even under Patent Owner's definition
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`would be one of the states and what is the difference between
`that and present or not present?
`MR. RENNER: You ask excellent questions. I
`will try to take them in order or at least address them all.
`Please let me know, obviously, if I don't.
`JUDGE BISK: Okay.
`MR. RENNER: Cache-coherency states, that term
`or that phrase, we're using that phrase because that phrase has
`been used. Candidly we recognize the existence of states like
`the MOESI states or the MESI states, whether those are
`themselves cache-coherency states, they probably are, but the
`full range of cache-coherency states, I think the patent itself
`is quite explicit that there could be a variety of states and
`never defines anything as cache-coherency states.
`So it is our position that that's not actually itself a
`term that needs to have boundary on it, but far more important
`than that or maybe consistent with that, those states that are --
`even if you were to recognize cache coherence as a special
`and narrowed class of states, we will see -- in fact, let's go to
`the next slide. And it will help to point this out. Two slides.
`There it is. Thank you.
`We will see those kinds of states as they have been
`applied in the briefing, they only apply to memory lines
`themselves. And the claim is to the cache coherence memory
`or the cache memory.
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`So even if you were to recognize a boundary
`around something called a cache coherent state and say that it
`is only the states of MESI or MOESI, that is modified, shared,
`exclusive, and invalid, for instance, you wouldn't apply that to
`the claim that has been articulated because the claim
`articulated doesn't apply to just the data that is specific to a
`memory line.
`JUDGE BISK: Okay. This brings up actually a
`totally separate question I had, which it was interesting I saw
`in your brief that you pointed out that it uses the word
`"cache" instead of memory line there.
`And to me that made me confused about what the
`claim even meant. And every -- all the prior art and the
`patent, it all seems to be discussing a memory line. So I don't
`really even know what -- what does presence mean when you
`talk about the whole cache? Are we talking about the whole
`cache there or what are we talking about there?
`MR. RENNER: Your Honor, I think, again, you
`are hitting right where you need -- right where we plan to hit.
`And if you look, for instance, at their claim number 3, I
`believe it is -- David, do you have that handy? We can see
`that there is actually recognition of claiming that speaks to
`the distinction between the two.
`It doesn't define that distinction, but there is
`acknowledgment of the need to distinguish between something
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`that is called a memory line and a cache memory in the claims
`themselves.
`And here in claim 1, to your point, if you look at
`claim 3, if you look at the back side of this claim you have
`"memory lines stored in the selected cache memories."
`When the Patent Owner wanted to talk about the
`state of the memory lines, they used the words memory lines.
`Right? Just when they wanted to talk about memory lines,
`they used the words memory lines.
`But in claim 1, what we have is states that are
`associated with -- very broad -- something different, cache
`memories. Now, I am not here to tell you that cache
`memories don't store memory lines, but I am here to tell you
`that there is a distinction between claiming that the states -- it
`is a state of the memory line that would be one way of
`thinking about it, but converse with or contrary to that, what
`we have is a state relating to a cache memory and it is
`associated with it. It is quite broad, relative to.
`I point this out because the intrinsic record that
`has been relied upon by Patent Owner speaks to the state, the
`memory line states. That's not what is claimed.
`And even there, there is no definition as to what
`those states are. In fact, you have got a specification that is
`relatively unbounded as it relates to that term.
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`So the definition they are asking for us all to
`observe as it relates to the word "states" is enormously narrow
`relevant to the intrinsic record and the claims themselves that
`they have presented, we believe. And it is for exactly the
`reasons you are asking, Judge Bisk.
`We think that there is an incongruity as between
`the claim and what -- part of the specification, perhaps they
`now want to focus on in trying to distinguish this prior art.
`JUDGE BISK: So could you now talk about the
`difference between the invalid state and presence?
`MR. RENNER: Yes, Your Honor. And we
`planned to do that. Let me fast forward so that we can.
`As for invalid, if you look perhaps at slide number
`12 -- thank you -- in slide 12, what we see is -- bear with me
`for a moment -- because the definitions will help us to get
`there, as will the extrinsic evidence.
`The definition here that was offered at the time of
`Institution, the Microsoft Computer Dictionary, it tells us that
`the word "state" and "status" are comparable, equivalent, if
`you will, similarly seen by those of skill in the art.
`Now, you can go left, but I would rather you go
`right because it is faster. If we go right, we can see how the
`word has been used by references that are relevant to cache
`coherence.
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`Chaiken is such a reference. And it tells us that
`the status is something that includes presence or absence. So
`what we have is the word status or state, we believe, is
`encompassing, it is broader than just validity or invalidity. It
`includes presence.
`Now, we see this again if you look at the next
`slide, please.
`JUDGE BISK: So you are saying then that state
`includes invalidity and presence.
`MR. RENNER: Correct.
`JUDGE BISK: But when you say that, you are
`implying there is a difference between invalidity and
`presence? I am not sure what that difference is.
`MR. RENNER: Right. And we will talk about
`that. I wanted to first establish that -- thank you for that --
`but I wanted to first establish that the claim we believe is
`broad enough to encompass both, but there are two different
`things.
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`JUDGE BISK: Okay.
`MR. RENNER: And we will talk about how they
`collapse because of the way the teaching of the reference is.
`Next, please.
`We see three different extrinsic references
`provided by Patent Owner, actually, that call out that the not
`present state is indeed -- is indeed a state.
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`JUDGE BEGLEY: Is presence a state, though?
`MR. RENNER: Is presence a state? We believe
`that it is, yes, Your Honor.
`JUDGE BEGLEY: Where is the evidence in the
`record that presence is a state as opposed to not present?
`MR. RENNER: We think that this bears out,
`Number 1, between the contrary correlation between the two.
`We don't see in the patent any definition that would exclude
`the opposite of something. We just have extrinsic references
`talk about the negative version, invalid, but the word "state,"
`as we have mentioned, is an unbounded term in the claim.
`And it is not defined otherwise in the specification.
`So thank you, Your Honor, for the question. We
`believe that that would mean that the word "state" is broad
`enough, absent some modification to sweep in each of invalid
`or valid. But to pick up on this, it is true that invalid is the
`more commonly discussed state.
`And invalid certainly is something that is
`established by the references here, including the Sorin book.
`You will notice that in Patent Owner's materials, often Sorin
`is relied upon for the proposition, in part, that presence isn't
`part of the state. But, indeed, it is.
`Now I have not answered Judge Bisk's question,
`which is why are we talking about two different things,
`presence and state? It is a good question.
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`It is because of the way that the Pong reference is
`taught. So if we look at slide number 34, please, what we see
`is the presence bid vector I had mentioned to you. It has got
`ones and zeros. That's a vector, right?
`And that presence bid vector, a map, for any given
`memory location, memory location, it is a map of where the
`instances in cache are, a map of all the different caches in the
`network supposedly. And where there is a one, we know there
`is presence. When there is a zero, we know there is not
`presence. Okay? That's nice. And that establishes presence.
`What it also establishes, though, based on the
`quote here from Pong at paragraph 69, Pong applies something
`called a write update protocol. It is important to understand
`what that means because it implicates what presence ends up
`indicating, okay?
`When you have a write update protocol, as soon as
`there is a write that is made in your scheme, we consult in a
`write update protocol the presence bit vector. And we find all
`the copies of the data that are out in the field.
`You can tell from the name that write update
`protocol, you go and update them. So you find the map and
`then you go and update them. And what does that mean to us?
`That means that all of the copies of the data of the field are
`always updated. The protocol demands it. I am sure there is
`latency, but that's --
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`JUDGE BEGLEY: Where does Pong disclose that
`it is updated?
`MR. RENNER: The write update field. We think
`paragraph 69 tells you that write update is applied by Pong. It
`is one of the two different kinds of protocols that it can apply.
`JUDGE BEGLEY: Sorry, to be more clear, where
`does Pong disclose that the directory clears the presence bit in
`the presence bit vector?
`MR. RENNER: So there is a different kind of
`protocol -- thank you for that question -- called the write
`invalidate protocol. And when the write invalidate protocol is
`put into play, instead of updating all the instances of data, it
`is a different implementation incidentally, but when all the
`instances are consulted and you have a write, if you update
`one of the pieces of data somewhere, one of the process
`updates, it is a piece of memory that the copy the memory has
`in its cache. Or maybe the home node where the cache
`actually -- the prior memory resides is updated.
`In that case you have incongruency. You have a
`difference between. You can consult one of two different
`kinds of protocols.
`JUDGE BISK: Sorry, I have two questions on this.
`One is in some of the, like in the patent they call this dir