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`Browse Conference Publications > Security and Privacy, 1997. P
`
`A secure and reliable bootstrap
`architecture
`
`12 Full Text
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`3
`Author(s)
`
`Arbaugh, W.A.
`
`; Distributed Syst. Lab., Pennsylvania Univ., Philadelphia, PA, USA ; Farber, D.J. ; Smith, J.M.
`
`Abstract
`
`References
`
`Cited By
`
`Keywords
`
`In a computer system, the integrity of lower layers is typically treated as axiomatic by higher layers.
`Under the presumption that the hardware comprising the machine (the lowest layer) is valid, the
`integrity of a layer can be guaranteed if and only if: (1) the integrity of the lower layers is checked and
`(2) transitions to higher layers occur only after integrity checks on them are complete. The resulting
`integrity “chain” inductively guarantees system integrity. When these conditions are not met, as they
`typically are not in the bootstrapping (initialization) of a computer system, no integrity guarantees can be
`made, yet these guarantees are increasingly important to diverse applications such as Internet
`commerce, security systems and “active networks". In this paper, we describe the AEGIS architecture
`for initializing a computer system. It validates integrity at each layer transition in the bootstrap process.
`AEGIS also includes a recovery process for integrity check failures, and we show how this results in
`robust systems
`
`Published in:
`
`Security and Privacy, 1997. Proceedings, 1997 |EEE Symposium on
`Date of Conference:
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`C Ie-I III‘I.
`
`4-7 May 1997
`
`Page(s):
`65 - 71
`
`Meeting Date :
`04 May 1997-07 May 1997
`ISSN :
`1081-6011
`
`Print ISBN:
`0—8186—7828—3
`
`INSPEC Accession Number:
`5602912
`
`Conference Location :
`Oakland, CA
`
`DOI:
`10.1109/SECPRI.1997.601317
`Publisher:
`|EEE
`
`II. ‘Gz‘th‘=\“.ltl
`
`.
`
`I
`
`HTC EX. 1028
`HTC v. Ancora
`US Patent No. 6,411,941
`
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`Page 1
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`HTC EX. 1028
`HTC v. Ancora
`US Patent No. 6,411,941
`
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