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`Attorney Docket No. GRTD60-34138
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`AMENDMENTS TO THE CLAIMS
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`This listing of claims will replace all prior versions, and listings, of claims in the
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`application:
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`1.
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`(Currently Amended) A system for storing data comprising:
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`memory space containing volatile memory space and nonvolatile memory space,
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`wherein the nonvolatile memory space includes both multilevel cell (MLC) space and
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`single level cell (SLC) space;
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`at least one controller to operate memory elements and associated memory
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`space;
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`at least one MLC nonvolatile memory element;
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`at least one SLC nonvolatile memory element;
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`at least one random access volatile memory element;
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`an FTL flash translation layer, wherein the at least one controller, or FTL, or a
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`combination of both maintain an address table in one or more of the memory elements;
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`and
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`the controller controlling access of
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`the MLC and SLC nonvolatile memory
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`elements and the random access volatile memory elements for storage of data therein;
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`the controller performing a data integrity test on stored data in a given one of the
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`MLC and SLC nonvolatile memory elements after any access operation is performed
`thereon'
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`wherein the address table maps logical and physical addresses adaptable to the
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`system, wherein the mapping is performed as necessitated by the system to maximize
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`lifetime, and wherein the mapping maps blocks, pages, or bytes of data in either volatile
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`or nonvolatile, or both, memories; and
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`wherein a failure of the data integrity test performed by the controller results in a
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`remapping of the address space to a different physical range of addresses from those
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`determined to have failed the data integrity test to achieve enhanced endurance.
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`Amendment — Page 2 of 7
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`
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`Customer No. 000040672
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`Attorney Docket No. GRTD60-34138
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`2.
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`(Currently Amended) The system of Claim 1, wherein the memory elements are
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`a software module, a hardware module, a standalone device, or multi-chip package.
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`3.
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`(Currently Amended) The system of Claim 1, wherein at least one of the volatile
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`or nonvolatile memory elements memer-ies are embedded in the at least one controller.
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`4.
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`(Currently Amended) The system of Claim 1, wherein the MLC and SLC
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`nonvolatile memory elements comgrise [[is]] flash memory.
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`5.
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`(Currently Amended) The system of Claim 1, wherein the memory in the SLC
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`and MLC nonvolatile memory elements is phase-change memory.
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`6.
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`(Currently Amended) The system of Claim 1, wherein the memory in the SLC
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`and MLC nonvolatile memory elements is magnetic random access memory.
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`7.
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`(Currently Amended) The system of Claim 1, wherein the random access volatile
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`memory element is dynamic random access memory.
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`8.
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`(Currently Amended) The system of Claim 1, wherein the random access volatile
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`memory element is static random access memory.
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`9.
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`(Original) The system of Claim 1, wherein the at least one SLC nonvolatile
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`memory element includes a hard disk drive (HDD).
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`10.
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`(New) The system of Claim 1, wherein the controller, upon detection of a failure
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`of the data integrity test, remaps the data to the other of the MLC and SLC nonvolatile
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`memory elements.
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`11.
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`(New) The system of Claim 10, wherein the given one of the MLC and SLC
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`nonvolatile memory elements is the MLC nonvolatile memory element.
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`Amendment — Page 3 of 7
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`
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`Customer No. 000040672
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`Attorney Docket No. GRTD60-34138
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`12.
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`(New) The system of Claim 10, wherein the SLC memory element has a higher
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`endurance than the MLC memory element.
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`13.
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`(New) The system of Claim 1, wherein the access operation is a Read operation.
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`14.
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`(New) The system of Claim 1, wherein the access operation is a Write operation.
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`15.
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`(New) The system of Claim 1, wherein the MLC is a1 bit cell.
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`16.
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`(New) The system of Claim 1, wherein the MLC is a multilevel cell, wherein the
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`multilevel cell stores n bits per cell, wherein n is any integer greater than 1.
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`17.
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`(New) The system of Claim 16, wherein the multilevel cell is a 3 bit cell.
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`18.
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`(New) The system of Claim 16, wherein the multilevel cell is a 4 bit cell.
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`19.
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`(New) A system for storing data comprising:
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`memory space containing volatile memory space and nonvolatile memory space,
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`wherein the nonvolatile memory space includes both multilevel cell (MLC) space and
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`single level cell (SLC) space;
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`at
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`least one controller to operate memory elements and associated memory
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`space;
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`at least one MLC nonvolatile memory element;
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`at least one SLC nonvolatile memory element;
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`at least one random access volatile memory element;
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`at least one controller to maintain an address table in one or more of the memory
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`elements;
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`the controller controlling access of
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`the MLC and SLC nonvolatile memory
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`elements and the random access volatile memory elements for storage of data therein;
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`Amendment — Page 4 of 7
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`
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`Customer No. 000040672
`
`Attorney Docket No. GRTD60-34138
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`the controller performing a data integrity test on stored data in a given one of the
`
`MLC and SLC nonvolatile memory elements after any access operation is performed
`
`thereon;
`
`wherein the address table maps logical and physical addresses adaptable to the
`
`system, wherein the mapping is performed as necessitated by the system to maximize
`
`lifetime, and wherein the mapping maps blocks, pages, or bytes of data in either volatile
`
`or nonvolatile, or both, memories; and
`
`wherein a failure of the data integrity test performed by the controller results in a
`
`remapping of the address space to a different physical range of addresses from those
`
`determined to have failed the data integrity test to achieve enhanced endurance.
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`20.
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`(Currently Amended) The system of Claim 19, wherein the memory elements
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`are a software module, a hardware module, a standalone device, or multi-chip package.
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`21.
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`(Currently Amended) The system of Claim 19, wherein at
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`least one of the
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`volatile or nonvolatile memory elements are embedded in the at least one controller.
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`Amendment — Page 5 of 7
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