UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`PO. Box 1450
`Alexandria, Virginia 2231371450
`www.uspto.gov
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`16/006,299
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`06/12/2018
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`GR. MOHAN RAO
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`GRTD60—34l38
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`6732
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`MUNCK WILSON MANDALA L.L.P
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`P 0 Drawer 800889
`DALLAS, TX 75380
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`REIDLINGER. RONALD LANCE
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`ART UNIT
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`2824
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`PAPER NUMBER
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`NOTIFICATION DATE
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`DELIVERY MODE
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`01/24/2019
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`ELECTRONIC
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`Please find below and/or attached an Office communication concerning this application or proceeding.
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`The time period for reply, if any, is set in the attached communication.
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`Notice of the Office communication was sent electronically on above—indicated "Notification Date" to the
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`following e—mail address(es):
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`IPdocketing @ munekwilson.eom
`admin @ dalpat.com
`eoffieeaetion @ appeoll.eom
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`PTOL-90A (Rev. 04/07)
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`

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`Off/09 A0170” Summary
`
`Application No.
`16/006,299
`Examiner
`R LANCE REIDLINGER
`
`Applicant(s)
`RAO, GR. MOHAN
`Art Unit
`AIA Status
`2824
`No
`
`- The MAILING DA TE of this communication appears on the cover sheet wit/7 the correspondence address -
`Period for Reply
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`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE g MONTHS FROM THE MAILING
`DATE OF THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR 1.136(a). In no event, however, may a reply be timely filed after SIX (6) MONTHS from the mailing
`date of this communication.
`|f NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any earned patent term
`adjustment. See 37 CFR 1.704(b).
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`Status
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`1). Responsive to communication(s) filed on 12 June 2018.
`[:1 A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/were filed on
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`2a)D This action is FINAL.
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`2b)
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`This action is non-final.
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`3)[:] An election was made by the applicant in response to a restriction requirement set forth during the interview on
`; the restriction requirement and election have been incorporated into this action.
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`4)[:] Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Expat/7e Quay/e, 1935 CD. 11, 453 O.G. 213.
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`Disposition of Claims*
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`5)
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`Claim(s) fl is/are pending in the application.
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`5a) Of the above claim(s)
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`is/are withdrawn from consideration.
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`E] Claim(s)
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`is/are allowed.
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`Claim(s) fl is/are rejected.
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`[:1 Claim(s) _ is/are objected to.
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`) ) ) )
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`6 7
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`8
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`
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`are subject to restriction and/or election requirement
`[j Claim(s)
`9
`* If any claims have been determined aflowabte. you may be eligible to benefit from the Patent Prosecution Highway program at a
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`participating intellectual property office for the corresponding application. For more information, please see
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`http://www.uspto.gov/patents/init events/pph/index.jsp or send an inquiry to PPeredback@uspto.gov.
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`Application Papers
`10)[:] The specification is objected to by the Examiner.
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`11). The drawing(s) filed on 12 June 2018 is/are: a). accepted or b)[:] objected to by the Examiner.
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`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`12)[:] Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`Certified copies:
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`a)I:I All
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`b)D Some”
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`C)D None of the:
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`1.[:] Certified copies of the priority documents have been received.
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`2.[:] Certified copies of the priority documents have been received in Application No.
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`3:] Copies of the certified copies of the priority documents have been received in this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
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`** See the attached detailed Office action for a list of the certified copies not received.
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`Attachment(s)
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`1)
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`Notice of References Cited (PTO-892)
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`2) E] Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`Paper No(s)/Mail Date_
`U.S. Patent and Trademark Office
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`3) C] Interview Summary (PTO-413)
`Paper No(s)/Mail Date
`4) CI Other-
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`PTOL-326 (Rev. 11-13)
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`Office Action Summary
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`Part of Paper No./Mai| Date 20190119
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`

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`Application/Control Number: 16/006,299
`Art Unit: 2824
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`Page 2
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`DETAILED ACTION
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`Claims 1-9 are pending.
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`Claim 1 is independent.
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`Notice of Pre-AIA or AIA Status
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`The present application is being examined under the pre-AIAfirst to invent provisions.
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`Claim Rejections - 35 USC § 103
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`In the event the determination ofthe status of the application as subject to A|A35 U.S.C. 102
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`and 103 (or as subject to pre-AIA 35 U.S. C. 102 and 103) is incorrect, any correction of the statutory
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`basis for the rejection will not be considered a new ground of rejection ifthe prior art relied upon, and
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`the rationale supporting the rejection, would be the same under either status.
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`The following is a quotation of pre-AIA35 U.S.C. 103(a) which forms the basis for all obviousness
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`rejections set forth in this Office action:
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`(a) A pa tent may not be obtained though the i nvention is not identicallyd isclosed or described as set
`forth in section 102, ifthe differences between the subject matter sought to be patented a nd the
`priora rt are such thatthe subject matter as a whole would have been obvious atthetime the
`invention wasmade to a person havingordinaryskill in the art to which said subject matter pertains.
`Pate ntabilityshall not be negatived bythe manner in which the invention was made.
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`The text of those sections ofTitle 35, U.S. Code not included in this action can be found in a
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`prior Office action.
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`The factual inquiries set forth in Graham v. John Deere C0,, 383 U.S. 1, 148 USPQ 459 (1966),
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`that are applied for establishing a background for determining obviousness under pre-AIA 35 U.S.C.
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`103(a) are summarized as follows:
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`1. Determining the scope and contents of the prior art.
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`2. Ascertaining the differences between the prior art and the claims at issue.
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`3. Resolving the level of ordinary skill in the pertinent art.
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`

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`Application/Control Number: 16/006,299
`Art Unit: 2824
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`Page 3
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`4. Considering objective evidence present in the application indicating obviousness or
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`nonobviousness.
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`Claims 1-4 and 7-9 are rejected under pre-AIA 35 U.S.C. 103(3) as being unpatentable over
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`Gorobets et al. (U.S. Patent Application Publication No. 2010/0172179, on record in parent application
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`13/455,267) in view ofGoodson et al. (”Design Tradeoffs in a Flash Translation Layer,” on recordin
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`parent application 13/455,267).
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`Regarding claim 1, Gorobets et al. teach,
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`A system for storing data (e.g. Fig. 20) comprising:
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`memory space containing volatile memory space (Fig. 15 Cache (RAM)) and nonvolatile memory
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`space (Fig. 15, MLC Memory, including Main Memory and Binary Cache), wherein the nonvolatile
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`memory space includes both multilevel cell (MLC) (Figs. 15, 20 Main Memory of MLC Memory) space
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`(Figs. 15, 20 Main Memory of MLC Memory) and single level cell (SLC) space (Figs. 15, 20 Binary Cache of
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`MLC Memory);
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`at least one controller (Fig. 8 Memory Manager No. 300; see also Fig. 15 Controller) to operate
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`memory elements and associated memory space (Flash Memory No. 200);
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`at least one MLC nonvolatile memory element (Fig. 20 Main Portion MLC No. 2003; this is a
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`primary characteristic of flash EEPROM of which this device is, see e.g.1i [0008]);
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`at least one SLC nonvolatile memory element (Fig. 20 Binary Portion No. 2001; again, this is a
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`primary characteristic of flash EEPROM of which this device is, see e.g.1i [0008]);
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`at least one random accessvolatile memory element (see Fig. 15 Cache (RAM));
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`wherein the at least one controller (Fig. 8 Memory Manager No. 300; see also Fig. 15 Controller)
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`of both maintain an address table in one or more ofthe memory elements (see 1] [0096]); and
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`wherein the address table maps logical and physical addresses (memory managerin the
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`controller maps logical addresses to physical addresses, see 1] [0096]) adaptable to the system, wherein
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`Application/Control Number: 16/006,299
`Art Unit: 2824
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`Page4
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`the mapping is performed as necessitated by the system to maximize lifetime, and wherein the mapping
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`maps blocks, pages, or bytes of data in either volatile or nonvolatile, or both, memories (see 1] [0152-
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`154], explaining the use of spa re block pool management to increase lifetime ofthe memory device;
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`mapping would be necessary to remap any logical address pointing to a retired block so that it points to
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`a replacement block, or new physical address).
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`Gorobets et al. explain address translation layers for flash memory, but do not describe the
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`specific term ”an FTL flash translation layer.”
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`Nevertheless, Goodson et al. document the purpose and motivation for using FTL for a flash
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`memory device (see Title, ”DesignTradeoffs in a Flash Translation Layer,” and §§ 1-2, which explain the
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`purpose of flash translation layers).
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`It would have been obvious to one of ordinary skill in the art at the time ofthe invention to
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`apply the teachings of Goodson et al. tothe teachings of Gorobets et al. such that an FTL (as explained
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`by Goodson et al.) is used with the flash devide taught by Gorobets et al. for the purpose of allowing the
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`files system of the flash memory device to maintain the block interface of the disk without sacrificing
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`the tighterintegration and control over how the flash is managed and because it hides the complexity of
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`the flash by providing a logical block interface for the flash device.
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`Regarding claims 2 and 9, Gorobets et al. explain that flash memory is most commonly provided
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`in the form ofa memory card (i.e., module or standalone unit as claimed) or a flash drive (i.e., module or
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`standalone unit or hard drive, as claimed) (see background 1] [0015]). Because Gorobets et al.
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`embodiments involve flash memory, the provisions of being a module, standalone device or hard drive,
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`as claimed, are met.
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`Regarding claim 3, Gorobets et al. teach at least one of the volatile or nonvolatile memories are
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`embedded in the at least one controller (see Fig. 15 volatile Cache (RAM) 102 is embedded within
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`Cont roller).
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`Application/Control Number: 16/006,299
`Art Unit: 2824
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`Page 5
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`Regarding claim 4, Gorobets et al. teach the nonvolatile memory (Figs. 15 MLC Memory) is flash
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`memory because the device is a flash memory device (see 1] [0135]; see also, Fig. 15, which labels the
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`memory device as a ”Flash Memory Device").
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`Regarding claim 7 and 8, although Gorobets et al. teach the volatile memory (Fig. 15 Cache
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`(RAM) 102), they are silent with respect to the specific type of volatile memory—whether DRAM or
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`SRAM as claimed. Gorobets et al. does not mention or show any aspects of the type of volatile memory
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`employed
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`OFFICIAL NOTICE is taken that DRAM and SRAM are volatile memory types that have been
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`frequently used as volatile memory in computer systems, and these two types of volatile memory are
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`obvious variantsand theirtradeoffs are well-documented in the prior art. For example, although SRAM
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`is faster than DRAM, SRAM requires more components per cell because typical prior art CMOS SRAM
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`cell involve six transistors (6T-SRAM), whereas the counterpart typical DRAM cell requires one transistor
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`and one capacitor (1T1C). DRAM, however, has been well-established in the industry as a main memory
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`for computing systems. The real estate required per cell is smaller than thatfor SRAM, meaning more
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`storage ca pacity at cheaper cost. The tradeoff is that DRAM must include refresh circuitry to account for
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`decay rate of the capacitors. Although SRAM is typically used for cache memory, DRAM is often
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`employed as well.
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`It would have obvious to one of ordinary skill in the art before the invention use DRAM or SRAM
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`for the volatile memory as claimed because of the reasons discussed a bove.
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`Claim 5 is rejected under pre-AIA35 U.S.C. 103(3) as being unpatentable over Gorobets et al.
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`in view of Goodson et al., as applied to claim 1, in further view of De Ambroggi et al. (U.S. Patent
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`Application Publication No. 2009/0268513, on record in parent application 13/455,267) and Kund et
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`al. (U.S. Patent Application Publication No. 2010/0058018, on record in parent application
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`13/455,267).
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`Application/Control Number: 16/006,299
`Art Unit: 2824
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`Page 6
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`Gorobets et al. fail to teach that the memory could be anything other than flash EEPROM or
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`other types of charge trapping memory see e.g.1] [0010] describing the various types of memory.
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`De Ambroggi et al. teach that one type of resistive memory (RRAM), Phase Change (PCRAM or
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`PCM) can be configured to be partially SLC and partially MLC.
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`Kund et al. teach generallythat ”Emerging memorytechnologies such as resistive memory (e.g.,
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`resistive random access memories such as phase change random access memory ( PCRAM), conductive
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`bridge random access memory (CBRAM), and magnetic random access memory ( MRAM)) offer certain
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`advantages over DRAM, Flash and other conventional types of memory devices in terms of switching
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`speeds, size, power consumption, and non-volatility.” 1] [0016].
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`Accordingly it would have been obvious to one of ordinary skill in the art at the time of the
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`invention to replace the flash EEPROM taught by Gorobets et al. with the PCM taught by De Ambroggi et
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`al. in view of the PCM advantages over flash EEPROM taught by Kund et al. because the emerging
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`memories (such as PCRAM) offer switching speed, size, power-consumption, and non-volatility
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`advantages over flash memory.
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`Claim 6 is rejected under pre-AIA35 U.S.C. 103(3) as being unpatentable over Gorobets et al.
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`in view of Goodson et al., as applied to claim 1, in further view of Chen et al. (U.S. Patent Application
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`Publication No. 2009/0307418, on record in parent application 13/455,267) and Kund et al.
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`Gorobets et al. fail to teach that the memory could be anything other than flash EEPROM or
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`other types of charge trapping memory see e.g.1] [0010] describing the various types of memory.
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`Chen et al. teach that MRAM could be used as SLC in conjunction with some other memory type
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`being used as MLC to create a hybrid density memory. See e.g.1] [0031].
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`Kund et al. teach generallythat ”Emerging memorytechnologies such as resistive memory (e.g.,
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`resistive random access memories such as phase change random access memory ( PCRAM), conductive
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`bridge random access memory (CBRAM), and magnetic random access memory ( MRAM)) offer certain
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`

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`Application/Control Number: 16/006,299
`Art Unit: 2824
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`Page 7
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`advantages over DRAM, Flash a nd other conventional types of memory devices in terms of switching
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`speeds, size, power consumption, and non-volatility.” 1] [0016].
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`Accordingly it would have been obvious to one of ordinary skill in the art at the time ofthe
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`invention to replace the SLC flash EEPROM taught by Gorobets et al. with the SLC MRAM in view of the
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`MRAM advantages over flash EEPROM taught by Kund et al. because the emerging memories (such as
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`MRAM) offer switching speed, size, power-consumption, and non-volatility advantages over flash
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`memory.
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`Conclusion
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`Any inquiry concerning this communication or earlier communications from the examiner
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`should be directed to R LANCE REIDLINGER whose telephone number is (571)270-7353. The examiner
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`Application/Control Number: 16/006,299
`Art Unit: 2824
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`Page 8
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`Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR
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`
`/R LANCE REIDLINGER/
`
`Examiner, Art Unit 2824
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`