`
`
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`PO. Box 1450
`Alexandria, Virginia 2231371450
`www.uspto.gov
`
`16/006,299
`
`06/12/2018
`
`GR. MOHAN RAO
`
`GRTD60—34l38
`
`6732
`
`MUNCK WILSON MANDALA L.L.P
`
`P 0 Drawer 800889
`DALLAS, TX 75380
`
`REIDLINGER. RONALD LANCE
`
`ART UNIT
`
`2824
`
`PAPER NUMBER
`
`NOTIFICATION DATE
`
`DELIVERY MODE
`
`01/24/2019
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above—indicated "Notification Date" to the
`
`following e—mail address(es):
`
`IPdocketing @ munekwilson.eom
`admin @ dalpat.com
`eoffieeaetion @ appeoll.eom
`
`PTOL-90A (Rev. 04/07)
`
`
`
`Off/09 A0170” Summary
`
`Application No.
`16/006,299
`Examiner
`R LANCE REIDLINGER
`
`Applicant(s)
`RAO, GR. MOHAN
`Art Unit
`AIA Status
`2824
`No
`
`- The MAILING DA TE of this communication appears on the cover sheet wit/7 the correspondence address -
`Period for Reply
`
`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE g MONTHS FROM THE MAILING
`DATE OF THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR 1.136(a). In no event, however, may a reply be timely filed after SIX (6) MONTHS from the mailing
`date of this communication.
`|f NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any earned patent term
`adjustment. See 37 CFR 1.704(b).
`
`Status
`
`1). Responsive to communication(s) filed on 12 June 2018.
`[:1 A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/were filed on
`
`2a)D This action is FINAL.
`
`2b)
`
`This action is non-final.
`
`3)[:] An election was made by the applicant in response to a restriction requirement set forth during the interview on
`; the restriction requirement and election have been incorporated into this action.
`
`4)[:] Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Expat/7e Quay/e, 1935 CD. 11, 453 O.G. 213.
`
`Disposition of Claims*
`
`5)
`
`Claim(s) fl is/are pending in the application.
`
`5a) Of the above claim(s)
`
`is/are withdrawn from consideration.
`
`E] Claim(s)
`
`is/are allowed.
`
`Claim(s) fl is/are rejected.
`
`[:1 Claim(s) _ is/are objected to.
`
`) ) ) )
`
`6 7
`
`8
`
`
`
`are subject to restriction and/or election requirement
`[j Claim(s)
`9
`* If any claims have been determined aflowabte. you may be eligible to benefit from the Patent Prosecution Highway program at a
`
`participating intellectual property office for the corresponding application. For more information, please see
`
`http://www.uspto.gov/patents/init events/pph/index.jsp or send an inquiry to PPeredback@uspto.gov.
`
`Application Papers
`10)[:] The specification is objected to by the Examiner.
`
`11). The drawing(s) filed on 12 June 2018 is/are: a). accepted or b)[:] objected to by the Examiner.
`
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`12)[:] Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`Certified copies:
`
`a)I:I All
`
`b)D Some”
`
`C)D None of the:
`
`1.[:] Certified copies of the priority documents have been received.
`
`2.[:] Certified copies of the priority documents have been received in Application No.
`
`3:] Copies of the certified copies of the priority documents have been received in this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`
`** See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`
`1)
`
`Notice of References Cited (PTO-892)
`
`2) E] Information Disclosure Statement(s) (PTO/SB/08a and/or PTO/SB/08b)
`Paper No(s)/Mail Date_
`U.S. Patent and Trademark Office
`
`3) C] Interview Summary (PTO-413)
`Paper No(s)/Mail Date
`4) CI Other-
`
`PTOL-326 (Rev. 11-13)
`
`Office Action Summary
`
`Part of Paper No./Mai| Date 20190119
`
`
`
`Application/Control Number: 16/006,299
`Art Unit: 2824
`
`Page 2
`
`DETAILED ACTION
`
`Claims 1-9 are pending.
`
`Claim 1 is independent.
`
`Notice of Pre-AIA or AIA Status
`
`The present application is being examined under the pre-AIAfirst to invent provisions.
`
`Claim Rejections - 35 USC § 103
`
`In the event the determination ofthe status of the application as subject to A|A35 U.S.C. 102
`
`and 103 (or as subject to pre-AIA 35 U.S. C. 102 and 103) is incorrect, any correction of the statutory
`
`basis for the rejection will not be considered a new ground of rejection ifthe prior art relied upon, and
`
`the rationale supporting the rejection, would be the same under either status.
`
`The following is a quotation of pre-AIA35 U.S.C. 103(a) which forms the basis for all obviousness
`
`rejections set forth in this Office action:
`
`(a) A pa tent may not be obtained though the i nvention is not identicallyd isclosed or described as set
`forth in section 102, ifthe differences between the subject matter sought to be patented a nd the
`priora rt are such thatthe subject matter as a whole would have been obvious atthetime the
`invention wasmade to a person havingordinaryskill in the art to which said subject matter pertains.
`Pate ntabilityshall not be negatived bythe manner in which the invention was made.
`
`The text of those sections ofTitle 35, U.S. Code not included in this action can be found in a
`
`prior Office action.
`
`The factual inquiries set forth in Graham v. John Deere C0,, 383 U.S. 1, 148 USPQ 459 (1966),
`
`that are applied for establishing a background for determining obviousness under pre-AIA 35 U.S.C.
`
`103(a) are summarized as follows:
`
`1. Determining the scope and contents of the prior art.
`
`2. Ascertaining the differences between the prior art and the claims at issue.
`
`3. Resolving the level of ordinary skill in the pertinent art.
`
`
`
`Application/Control Number: 16/006,299
`Art Unit: 2824
`
`Page 3
`
`4. Considering objective evidence present in the application indicating obviousness or
`
`nonobviousness.
`
`Claims 1-4 and 7-9 are rejected under pre-AIA 35 U.S.C. 103(3) as being unpatentable over
`
`Gorobets et al. (U.S. Patent Application Publication No. 2010/0172179, on record in parent application
`
`13/455,267) in view ofGoodson et al. (”Design Tradeoffs in a Flash Translation Layer,” on recordin
`
`parent application 13/455,267).
`
`Regarding claim 1, Gorobets et al. teach,
`
`A system for storing data (e.g. Fig. 20) comprising:
`
`memory space containing volatile memory space (Fig. 15 Cache (RAM)) and nonvolatile memory
`
`space (Fig. 15, MLC Memory, including Main Memory and Binary Cache), wherein the nonvolatile
`
`memory space includes both multilevel cell (MLC) (Figs. 15, 20 Main Memory of MLC Memory) space
`
`(Figs. 15, 20 Main Memory of MLC Memory) and single level cell (SLC) space (Figs. 15, 20 Binary Cache of
`
`MLC Memory);
`
`at least one controller (Fig. 8 Memory Manager No. 300; see also Fig. 15 Controller) to operate
`
`memory elements and associated memory space (Flash Memory No. 200);
`
`at least one MLC nonvolatile memory element (Fig. 20 Main Portion MLC No. 2003; this is a
`
`primary characteristic of flash EEPROM of which this device is, see e.g.1i [0008]);
`
`at least one SLC nonvolatile memory element (Fig. 20 Binary Portion No. 2001; again, this is a
`
`primary characteristic of flash EEPROM of which this device is, see e.g.1i [0008]);
`
`at least one random accessvolatile memory element (see Fig. 15 Cache (RAM));
`
`wherein the at least one controller (Fig. 8 Memory Manager No. 300; see also Fig. 15 Controller)
`
`of both maintain an address table in one or more ofthe memory elements (see 1] [0096]); and
`
`wherein the address table maps logical and physical addresses (memory managerin the
`
`controller maps logical addresses to physical addresses, see 1] [0096]) adaptable to the system, wherein
`
`
`
`Application/Control Number: 16/006,299
`Art Unit: 2824
`
`Page4
`
`the mapping is performed as necessitated by the system to maximize lifetime, and wherein the mapping
`
`maps blocks, pages, or bytes of data in either volatile or nonvolatile, or both, memories (see 1] [0152-
`
`154], explaining the use of spa re block pool management to increase lifetime ofthe memory device;
`
`mapping would be necessary to remap any logical address pointing to a retired block so that it points to
`
`a replacement block, or new physical address).
`
`Gorobets et al. explain address translation layers for flash memory, but do not describe the
`
`specific term ”an FTL flash translation layer.”
`
`Nevertheless, Goodson et al. document the purpose and motivation for using FTL for a flash
`
`memory device (see Title, ”DesignTradeoffs in a Flash Translation Layer,” and §§ 1-2, which explain the
`
`purpose of flash translation layers).
`
`It would have been obvious to one of ordinary skill in the art at the time ofthe invention to
`
`apply the teachings of Goodson et al. tothe teachings of Gorobets et al. such that an FTL (as explained
`
`by Goodson et al.) is used with the flash devide taught by Gorobets et al. for the purpose of allowing the
`
`files system of the flash memory device to maintain the block interface of the disk without sacrificing
`
`the tighterintegration and control over how the flash is managed and because it hides the complexity of
`
`the flash by providing a logical block interface for the flash device.
`
`Regarding claims 2 and 9, Gorobets et al. explain that flash memory is most commonly provided
`
`in the form ofa memory card (i.e., module or standalone unit as claimed) or a flash drive (i.e., module or
`
`standalone unit or hard drive, as claimed) (see background 1] [0015]). Because Gorobets et al.
`
`embodiments involve flash memory, the provisions of being a module, standalone device or hard drive,
`
`as claimed, are met.
`
`Regarding claim 3, Gorobets et al. teach at least one of the volatile or nonvolatile memories are
`
`embedded in the at least one controller (see Fig. 15 volatile Cache (RAM) 102 is embedded within
`
`Cont roller).
`
`
`
`Application/Control Number: 16/006,299
`Art Unit: 2824
`
`Page 5
`
`Regarding claim 4, Gorobets et al. teach the nonvolatile memory (Figs. 15 MLC Memory) is flash
`
`memory because the device is a flash memory device (see 1] [0135]; see also, Fig. 15, which labels the
`
`memory device as a ”Flash Memory Device").
`
`Regarding claim 7 and 8, although Gorobets et al. teach the volatile memory (Fig. 15 Cache
`
`(RAM) 102), they are silent with respect to the specific type of volatile memory—whether DRAM or
`
`SRAM as claimed. Gorobets et al. does not mention or show any aspects of the type of volatile memory
`
`employed
`
`OFFICIAL NOTICE is taken that DRAM and SRAM are volatile memory types that have been
`
`frequently used as volatile memory in computer systems, and these two types of volatile memory are
`
`obvious variantsand theirtradeoffs are well-documented in the prior art. For example, although SRAM
`
`is faster than DRAM, SRAM requires more components per cell because typical prior art CMOS SRAM
`
`cell involve six transistors (6T-SRAM), whereas the counterpart typical DRAM cell requires one transistor
`
`and one capacitor (1T1C). DRAM, however, has been well-established in the industry as a main memory
`
`for computing systems. The real estate required per cell is smaller than thatfor SRAM, meaning more
`
`storage ca pacity at cheaper cost. The tradeoff is that DRAM must include refresh circuitry to account for
`
`decay rate of the capacitors. Although SRAM is typically used for cache memory, DRAM is often
`
`employed as well.
`
`It would have obvious to one of ordinary skill in the art before the invention use DRAM or SRAM
`
`for the volatile memory as claimed because of the reasons discussed a bove.
`
`Claim 5 is rejected under pre-AIA35 U.S.C. 103(3) as being unpatentable over Gorobets et al.
`
`in view of Goodson et al., as applied to claim 1, in further view of De Ambroggi et al. (U.S. Patent
`
`Application Publication No. 2009/0268513, on record in parent application 13/455,267) and Kund et
`
`al. (U.S. Patent Application Publication No. 2010/0058018, on record in parent application
`
`13/455,267).
`
`
`
`Application/Control Number: 16/006,299
`Art Unit: 2824
`
`Page 6
`
`Gorobets et al. fail to teach that the memory could be anything other than flash EEPROM or
`
`other types of charge trapping memory see e.g.1] [0010] describing the various types of memory.
`
`De Ambroggi et al. teach that one type of resistive memory (RRAM), Phase Change (PCRAM or
`
`PCM) can be configured to be partially SLC and partially MLC.
`
`Kund et al. teach generallythat ”Emerging memorytechnologies such as resistive memory (e.g.,
`
`resistive random access memories such as phase change random access memory ( PCRAM), conductive
`
`bridge random access memory (CBRAM), and magnetic random access memory ( MRAM)) offer certain
`
`advantages over DRAM, Flash and other conventional types of memory devices in terms of switching
`
`speeds, size, power consumption, and non-volatility.” 1] [0016].
`
`Accordingly it would have been obvious to one of ordinary skill in the art at the time of the
`
`invention to replace the flash EEPROM taught by Gorobets et al. with the PCM taught by De Ambroggi et
`
`al. in view of the PCM advantages over flash EEPROM taught by Kund et al. because the emerging
`
`memories (such as PCRAM) offer switching speed, size, power-consumption, and non-volatility
`
`advantages over flash memory.
`
`Claim 6 is rejected under pre-AIA35 U.S.C. 103(3) as being unpatentable over Gorobets et al.
`
`in view of Goodson et al., as applied to claim 1, in further view of Chen et al. (U.S. Patent Application
`
`Publication No. 2009/0307418, on record in parent application 13/455,267) and Kund et al.
`
`Gorobets et al. fail to teach that the memory could be anything other than flash EEPROM or
`
`other types of charge trapping memory see e.g.1] [0010] describing the various types of memory.
`
`Chen et al. teach that MRAM could be used as SLC in conjunction with some other memory type
`
`being used as MLC to create a hybrid density memory. See e.g.1] [0031].
`
`Kund et al. teach generallythat ”Emerging memorytechnologies such as resistive memory (e.g.,
`
`resistive random access memories such as phase change random access memory ( PCRAM), conductive
`
`bridge random access memory (CBRAM), and magnetic random access memory ( MRAM)) offer certain
`
`
`
`Application/Control Number: 16/006,299
`Art Unit: 2824
`
`Page 7
`
`advantages over DRAM, Flash a nd other conventional types of memory devices in terms of switching
`
`speeds, size, power consumption, and non-volatility.” 1] [0016].
`
`Accordingly it would have been obvious to one of ordinary skill in the art at the time ofthe
`
`invention to replace the SLC flash EEPROM taught by Gorobets et al. with the SLC MRAM in view of the
`
`MRAM advantages over flash EEPROM taught by Kund et al. because the emerging memories (such as
`
`MRAM) offer switching speed, size, power-consumption, and non-volatility advantages over flash
`
`memory.
`
`Conclusion
`
`Any inquiry concerning this communication or earlier communications from the examiner
`
`should be directed to R LANCE REIDLINGER whose telephone number is (571)270-7353. The examiner
`
`can normally be reached on M-F 1:00pm - 10:00pm.
`
`Examiner interviews are available via telephone, in-person, and video conferencing using a
`
`USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use
`
`the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
`
`Ifattemptsto reach the examiner by telephone are unsuccessful, the examiner’s supervisor,
`
`Rich T Elms can be reached on 571.272.1869. The fax phone number for the organization where this
`
`application or proceeding is assigned is 571-273-8300.
`
`Information rega rdingthe status of an application may be obtained from the Patent Application
`
`Information Retrieval (PAIR) system. Status information for published applications may be obtained
`
`from either Private PAIR or Public PAIR. Status information for unpublished applications is available
`
`through Private PAIR only. For more information about the PAIR system, see http://pair-
`
`direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic
`
`Business Center (EBC) at 866-217-9197 (toll-free). Ifyou would like assistance from a USPTO Customer
`
`
`
`Application/Control Number: 16/006,299
`Art Unit: 2824
`
`Page 8
`
`Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR
`
`CANADA) or 571-272-1000.
`
`/R LANCE REIDLINGER/
`
`Examiner, Art Unit 2824
`
`