Trials@uspto.gov
`571-272-7822
`
`Paper 11
`Date: April 11, 2022
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`MICRON TECHNOLOGY,INC.,
`Petitioner,
`
`V.
`
`VERVAIN, LLC,
`Patent Owner.
`
`IPR2021-01550
`Patent 10,950,300 B2
`
`Before SALLY C. MEDLEY, STACEY G. WHITE, and
`ROBERTJ. WEINSCHENK,Administrative Patent Judges.
`
`WHITE, Administrative Patent Judge.
`
`DECISION
`Granting Institution ofInter Partes Review
`IS US.C. § 314
`
`
`571-272-7822
`
`Paper 11
`Date: April 11, 2022
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`MICRON TECHNOLOGY,INC.,
`Petitioner,
`
`V.
`
`VERVAIN, LLC,
`Patent Owner.
`
`IPR2021-01550
`Patent 10,950,300 B2
`
`Before SALLY C. MEDLEY, STACEY G. WHITE, and
`ROBERTJ. WEINSCHENK,Administrative Patent Judges.
`
`WHITE, Administrative Patent Judge.
`
`DECISION
`Granting Institution ofInter Partes Review
`IS US.C. § 314
`
`
`
`IPR2021-01550
`Patent 10,950,300 B2
`
`YT.
`
`INTRODUCTION
`
`Micron Technology,Inc. (‘Petitioner’) filed a Petition requesting an
`
`inter partes review of claims 1-12 (“the challenged claims”) of U.S. Patent
`
`No. 10,950,300 B2 (Ex. 1007, “the ’300 patent”). Paper | (“Pet.”).
`Vervain, LLC (‘Patent Owncr’’) filed a Preliminary Response. Paper9
`
`(“Prelim. Resp.”).
`
`Under 35 U.S.C. § 314(a), an inter partes review maynotbeinstituted
`
`unless the information presented in the petition “showsthatthere is a
`
`reasonable likelihood that the petitioner would prevail with respect to at
`
`least 1 of the claims challenged in the petition.” The following findings of
`
`fact and conclusionsof law are notfinal, but are made for the sole purpose
`
`of determining whether Petitioner meets the threshold forinitiating review.
`
`Anyfinal decision shall be based on the full trial record, including any
`
`responsetimely filed by Patent Owner. Any argumentsnotraised by Patent
`
`Ownerin a timely-filed responsc may be deemed waived, even if they were
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`presented in the Preliminary Response.
`
`For the reasonsstated below, we determine that Petitioner has
`
`established a reasonable likelihood that it would prevail with respect to at
`
`least one claim. We herebyinstitute an inter partes review asto all of the
`
`challenged claims of the ’300 patent onall of the asserted grounds of
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`unpatentability.
`
`A. Related Matters
`
`The *300 patent is part of a family of related patents including
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`US 8,891,298 B2 (“°298 patent”); US 9,196,385 B2 (385 patent’);
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`US 9,997,240 B2 (“’240 patent”). Ex. 1007, code (60). The parties indicate
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`that the ’300 patent and the related ’298 patent, °385 patent, and ’240 patent
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`are the subject of the following district court proceedings: Vervain, LLCv.
`
`
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`IPR2021-01550
`Patent 10,950,300 B2
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`Micron Technology, Inc. et al., No. 6:21-cv-00487 (W.D. Tex.) and Vervain,
`
`LLC vy. Western Digital Corporationet al., No. 6:21-cv-00488 (W.D. Tex.).
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`Pet. 4-5; Paper 6, 2. The parties further indicate that the ’298 patent is the
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`subject of IPR2021-01547; the ’385 patent is the subject of IPR2021-01548,
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`and the °240 patentis the subject of IPR2021-01549. Pet. 5; Paper 6, 2-3.
`
`B. The ’300 Patent
`
`The ’300 patentis titled “Lifetime Mixed Level Non-Volatile
`
`Memory System.” Ex. 1007, code (54). Generally, the ’300 patent
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`describes a system that stores data in a second memory bank,in the case that
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`data which was stored in a first memory bank fails a data integrity test. Jd.
`
`at 5:10-17. Figure 1 of the °300 patent is reproduced below.
`
`FIG. 1
`
`Figure 1 showsa block diagram of a computer system 10 thatstores,
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`i.e., writes, data from dynamic random access memory (“DRAM”) 20 onto
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`non-volatile memory, e.g., multi-level cell (“MLC”) NAND flash
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`memory 26 or single-level cell (“SLC”) NAND flash memory 28. Ex. 1007,
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`4:60-61, 6:17—20; see id. at 5:23-42. DRAM 20, MLC NAND flash
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`memory 26, and SLC NAND flash memory28 are controlled by device
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`controller 14. /d. at 5:34-42. Further, device controller 14 “acts as the
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`memory controller” in a process which “write[s] aquantum of data stored in
`DRAMto aparticular location in NAND flash memory.” Jd. at 6:17—22.
`
`In the write process, “the quantum of data [to be written] is read from
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`DRAM into memory within the device controller.” Jd. at 6:20-22. Then,
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`the quantum ofdata is written to an identified physical address range in flash
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`memory. Jd. at 6:25—30; see id. Fig. 3A. In particular, the quantum of data
`initially is written to MLC NAND flash memory, rather than SLC NAND
`
`flash memory, because “MLC [NAND] flash memory is less expensive than
`
`SLC [NAND]flash memory.” Jd. at 5:51-60; see id. at 5:12-14.
`
`Further,“[a]fter each write to an address within a particular address
`
`range,” of the MLC NAND flash memory,“the device controller 14 will...
`
`perform a read on the address range to ensure the integrity of the written
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`data.” Ex. 1007, 5:61-64. In particular, the device controller compares
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`“retained data representing” the quantum ofdata to be written with “newly
`
`stored data in the [MLC] NAND flash memory.” Jd. at 6:33-39; see id. Fig.
`
`3B. If the data matches, “the write was a success.” Jd. at 6:38—40; see id.
`
`Fig. 3B. “However, if the retained data does not match the newly stored
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`data in the [MLC] NAND flash memory,” then a “quantum ofavailable SLC
`
`NAND flash memory addresses”are identified, “the failed NAND flash
`
`physical address range is remappedto the next available quantum of SLC
`
`NAND flash memory,” and the quantum ofdata is written to SLC NAND
`flash memory. fd. al 6.40—-52,see id. Fiy. 3B.
`.
`
`Additionally, in some embodiments, instead of device controller 15,
`“flash translation layer (FTL) 54 manages” the MLC and SLM NAND flash
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`
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`Patent 10,950,300 B2
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`memory banksand further conducts “control functions.” Jd. at 7:3-15 see
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`id. Fig. 4.
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`|
`
`C.
`
`Illustrative Claim
`
`Of the challenged claims, claims 1 and 12 are independent. Claims 2—
`
`11 depend from claim 1. Claim1 is illustrative.
`
`1. A system for storing data comprising:
`
`memory space containing volatile memory space and nonvolatile
`memory space, wherein the nonvolatile memory space includes
`both multilevel cell (MLC) memoryspace andsingle levelcell
`(SLC) memory space;
`
`least one controller
`at
`associated memory space;
`
`to operate memory elements and
`
`least one MLC nonvolatile memory element that can be
`at
`mapped into the MLC memory space;
`
`at least one SLC nonvolatile memory element that can be mapped
`into the SLC memory space;
`
`at least one random access volatile memory;
`
`an FTL flash translation layer, wherein the at least one controller,
`or FTL, or a combination of both maintain an address table in
`one or more of the memory elements and random accessvolatile
`memory;
`
`the controller controlling access of the MLC and SLC
`nonvolatile memory elements and the random access volatile
`memory for storage of data therein, the controller, in at least a
`Write access operation to the MLC nonvolatile memory clement,
`operable to store data in the MLC nonvolatile memory element
`and retain such stored data in the random access volatile
`
`memory;
`
`the controller performing a data integrity test on stored data in
`the MLC nonvolatile memory element after at least a Write
`access operation performed thereon by comparingthe stored data
`to the retained data in the random access volatile memory;
`
`
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`IPR2021-01550
`Patent 10,950,300 B2
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`wherein the address table maps logical and physical addresses
`adaptable to the system, wherein the mapping is performed as
`necessitated by the system to maximizelifetime, and wherein the
`mapping mapsblocks, pages, or bytes of data in either volatile or
`nonvolatile, or both, memories; and
`
`wherein a failure of the data integrity test performed by the
`controller results in a remapping of the address space to a
`different physical
`range of addresscs and transfer of data
`corresponding to the stored data to those remapped physical
`addresses from those determinedto havefailed the data integrity
`test to achieve enhanced endurance.
`
`Ex. 1007, 7:37-8:11.
`
`D. Prior Art Relied Upon
`
`Petitioner relies upon the referenceslisted below (Pet.6):
`
`Reference
`Dusija, US 2011/0099460 A1, published Apr. 28, 2011
`
`(“Dusija”
`
`Exhibit No.
`
`E.
`
` Asserted Grounds of Unpatentability
`
`Petitioner, supported by the declaration of Dr. David Liu (Ex. 1009),
`asserts the following grounds of unpatentability (Pet. 6)!:
`
`Claim(s) Challenged|35 U.S.C. § Reference(s)/Basis
`
`
`
`
`1-9, 11, 12
`
`
` Wo
`
`' For purposes of this Decision, we assumethe claimsat issue have an
`effective filing dale prior to March 16, 2013, the effcctive date of the
`Leahy-Smith America Invents Act, Pub, L. No. 112-29, 125 Stat. 284 (2011)
`(“AIA”), and we apply the pre-AIA version of 35 U.S.C. § 103. See Pet. 5—
`6 (assuming challenged claimsare entitled to benefit of July 19, 2011 filing
`date).
`
`
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`IPR2021-01550
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`Il. ANALYSIS
`
`A. Discretionary Denial Under 35 U.S.C. § 314(a)
`
`Patent Ownerarguesthat “the Board should exercise its discretion
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`under 35 U.S.C. § 314 and denyinstitution because ofthe overlap with the
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`parallel district court liliyaltiuu.” Prelim. Resp. 36. Petitioner, however,
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`contendsthat evaluation of the Apple v. Fintiv factors demonstrates we
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`should not exercise discretion to deny institution of inter partes review. Pet.
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`7-12.
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`Institution of an inter partes review is discretionary. See 35 U.S.C.
`
`§ 314(a)(stating “[t]he Director may not authorize an inter partes review to
`
`be instituted unless the Director determines that the information presented in
`
`the petition .
`
`.
`
`. showsthat there is a reasonable likelihood that the petitioner
`
`would prevail with respect to at least 1 of the claims challenged in the
`
`petition”) (emphasis added); Harmonic Inc. v. Avid Tech, Inc., 815 F.3d
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`1356, 1367 (Fed. Cir. 2016) (“[T]he PTO is permitted, but never compelled,
`
`to institute an IPR proceeding.”). In determining whetherto exercise that
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`discretion on behalf of the Director, we are guided by the Board’s
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`precedential decision in NHK Spring Co. v. Intri-Plex Techs, Inc., IPR2018-
`
`00752, Paper 8 (PTAB Sept. 12, 2018).
`
`In NHK,the Board found that the “advancedstate ofthe district court
`
`proceeding” was a “factor that weighs in favor of denying”the petition
`
`under § 314(a). NHK, Paper 8 at 20. The Board determinedthat
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`“TiJnstitution of an inter partes review under these circumstances would not
`
`be consistent with ‘an objective of the AJA ... to provide an effective and
`
`efficient alternative to district court litigation.” Jd. (citing Gen. Plastic
`
`Indus. Co., v. Cannon Kabushiki Kaisha, IPR2016-01357, Paper 19 at 16-17
`
`(PTAB Sept. 6, 2017) (precedential in relevant part)).
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`
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`IPR2021-01550
`Patent 10,950,300 B2
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`The Board’s precedential decision in Apple Inc. v. Fintiv, Inc.,
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`IPR2020-00019, Paper 11 (PTAB Mar. 20, 2020) (Fintiv’’) sets forth the
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`following six non-exclusive factors to consider when determining whetherto
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`exercise discretion to deny institution due to the advancedstate of parallel
`
`litigation:
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`1. whether the court granted a stay or evidenceexists that
`one maybegranted if a proceedingis instituted;
`
`2. proximity of the court’s trial date to the Board’s
`projected statutory deadline for a final written decision;
`
`3. investment in the parallel proceeding by the court and
`the parties;
`
`4. overlap betweenissues raised in the petition and in the
`parallel proceeding;
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`5. whether the petitioner and the defendant in the parallel
`proceeding are the same party; and
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`6. other circumstances that impact the Board’s exercise of
`discretion, including the merits.
`
`Id. at 6. ‘These factors relate to whetherefficiency, fairness, and the merits
`
`support the exercise of authority to deny institution in view ofan earliertrial
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`date in the parallel proceeding.” Jd. In evaluating these factors, we take “a
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`holistic view of whetherefficiency and integrity of the system are best
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`served by denyingorinstituting review.” Jd. (citing Patent Trial and Appeal
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`Board Consolidated Trial Practice Guide 58 (November 2019),
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`https://www.uspto.gov/TrialPracticeGuideConsolidated). We address the
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`Fintiv factors below and detail our reasons for exercising discretion to deny
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`iustitulion based on § 314(a).
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`IPR2021-01550
`Patent 10,950,300 B2
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`1. Whether a Stay Exists or Is Likely to Be Granted ifa Proceeding Is
`Instituted
`
`Underthe first Fintiv factor, we consider “whether the court granted a
`stay or evidence exists that one may be granted if a proceedingis instituted.”
`Finvtiv, Paper 11 at 6. Petitioner argues that “[nJeither party has yet
`
`requested astay, so at worst this factor is neutral because the Board ‘will not
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`attempt to predict’ how the [D]istrict [CJourt will proceed.” Pet. 11-12.
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`Patent Ownerarguesthat the District Court “rarely stay[s] a. .
`
`. patent case
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`based on an IPR.” Prelim. Resp. 38. Thus, according to Patent Owner, the
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`first factor “is neutral or weighs against institution.” Jd.
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`Neither party identities any statements by the District Court or other
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`evidencethat specifically addresses a stay of this District Court Litigation.
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`See Pet. 12; Prelim. Resp. 32. We decline to speculate based on the record
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`in this case whetherthe District Court would grant a stay of the District
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`Court Litigation. See Apple Inc. v. Fintiv, Inc., IPR2020-00019, Paper 15 at
`12 (PTAB May 13, 2020) (informative) (“Fintiv IP’). As a result, we
`
`determinethat the first Fintiv factoris neutral.
`
`2. Proximity of the Court’s Trial Date to the Board’s Projected Statutory
`Deadline
`
`Underthe second Fintiv factor, we consider the “proximity ofthe
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`court’s trial date to the Board’s projected statutory deadline for a final
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`written decision.” Fintiv, Paper 11 at 6. Petitioner notes that the District
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`Court “recently set a ‘first trial’ date .
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`.
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`. of 1/23/2023, ‘subject to the Court’s
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`availability.’” Pet. 11. Petitioner argues that thistrial date “falls a few
`
`months before the projected final written decision date,” but the District
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`Court “has an exploding docket that has madeit difficult .
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`.
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`. to hold trials on
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`the dates they are scheduled.” Jd. Thus, accordingto Petitioner, “the Board
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`IPR2021-01550
`Patent 10,950,300 B2
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`is still likely to reach the merits of the Petition before or around the same
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`time as the [D]istrict [C]ourt,” and the second factor favors institution. Jd. at
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`11. Patent Ownerargues that the second factor favors denying institution
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`becausethetrial date in the District Court Litigation “is almost three months
`
`prior”to the projected final written decision in this case. Prelim. Resp. 38.
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`The currenttrial date in the District Court Litigation is January 23,
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`2023. Ex. 1035, 3. The projected statutory deadline for a final written
`
`decision in this case is in April 2023. Becausethetrial date in the District
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`Court Litigation is only a few monthsbefore the projected statutory deadline
`for a final written decision in this case, we determine that the second Fintiv |
`factor slightly favors exercising our discretion to denyinstitution.
`
`3.
`
`Investmentin the Parallel Proceeding by the Court and Parties
`
`Underthe third Fintiv factor, we consider the “investment in the
`
`parallel proceeding by the court and the parties.” Fintiv, Paper 11 at 6.
`
`Petitioner argues that “to date, no court resources have been devotedto
`29 &&
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`analyzing priorart, invalidity, or any other substantive issue,”
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`“[n]o claim
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`construction has occurred, a motion to dismiss is pending, and there has
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`been no meaningful fact or expert discovery.” Pet. 8-9. Petitioner also
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`arguesthatit “had no pre-suit notice of the 300 patent[, nJevertheless
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`approximately four and a half months”after the District Court Litigation was
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`filed Petitioner was able to get this Petition on file. Jd. at 7, 8-9. Thus,
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`according to Petitioner, the third factor favors institution. Jd.
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`Patent Ownerarguesthat “[b]y the time the Board decides whether to
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`institute this IPR in April 2022, the [D]istrict [C]ourt and the parties will
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`have completed the following: briefing on a motion to dismiss, an amended
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`complaint, an exchangeof preliminary andfinal infringement and invalidity
`
`contentions, and claim construction.” Prelim. Resp. 39. Patent Owneralso
`
`10
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`
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`IPR2021-01550
`Patent 10,950,300 B2
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`arguesthat “[b]y .
`
`.
`
`. the estimated institution decision date, the parties will
`
`be halfway through fact discovery, have exchanged untold numbers of
`
`documents, and likely begun depositions.” Jd. at 39-40. Thus, Patent
`
`Ownercontendsthe third factor favors denying institution. J/d.
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`The evidenceofrecord indicates that the District Court and the parties
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`invested minimal resourcesin the District Court Litigation as to issues of
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`unpatentability involving the 7300 patent. Also, the parties’ evidence shows
`that fact discovery is ongoing, expert discovery has not begun, and the
`deadline for dispositive motionsis not until October 2022. Ex. 1035, 2-3.
`
`Further, Petitioner exercised reasonable diligence in filing the Petition six
`
`weeksafter receiving Patent Owner’s infringement contentionsin the
`
`District Court Litigation. Pet. 8. Thus, we determinethat the third Fintiv
`
`factor weighs against discretionary denial of institution.
`
`4. Overlap Between Issues Raisedin the Petition and in the Parallel
`Proceeding
`
`Underthe fourth Fintiv factor, we consider the “overlap between
`
`issues raised in the petition and in the parallel proceeding.” Fintiv, Paper 11
`
`at 6. Petitioner argues that “should the Board institute an IPR proceeding on
`
`the [’]300 patent, [Petitioner] stipulates that it will not pursue any instituted
`
`groundsas invalidity defenses in the District Court thus, eliminating any
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`overlap in issues.” Pet. 10; Ex. 2013, 2 n. 1 (repeating the samestipulation
`
`in its Invalidity Contentions for the District Court Litigation). Petitioner
`
`also notes that claim 6 is challenged in this proceeding even thoughitis not
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`asserted in the District Court Litigation. Id.
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`Patent Ownerarguesthat the District Court Litigation “involves the
`
`same °300 [p]atent” and “the Dusija and Sutardja priorart.” Prelim. Resp.
`
`40. Patent Owneralso contendsthat “Petitioner’s narrowstipulationis
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`11
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`hollow in that it leaves open the possibility of parallel litigation for the same
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`claims using printed publications and various system combinations not
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`asserted in the Petition.” /d. at 41-42. Further, Patent Ownerasserts “that
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`Petitioner challenged dependent claim 6 in order to manufacture an
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`arguinent on Fintiv factor 4.” Jd. at 42. Thus, Patent Owner contendsthat
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`the fourth factor favors denying institution. Id.
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`The Petition challenges claims 1~12 and relies on Dusija for eleven of
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`the challenged claims and the combination of Dusija and Sutardja for claim
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`10. Pet. 6. Petitioner’s invalidity contentions in the District Court Litigation
`
`address claims 1—5 and 7-12 and rely on Dusija and Sutardja. Ex. 2013, 1,
`89-91. ‘Nonetheless, Petitioner’s proposed stipulation that it will not pursue
`the same groundsin this case and the District Court Litigation mitigates to
`
`some degree concerns about duplicative efforts and potentially conflicting
`
`decisions. See Sand Revolution II, LLC v. Continental Intermodal Grp. —
`
`Trucking LLC, IPR2019-01393, Paper 24 at 12 (PTAB June 16, 2020)
`
`(informative). In addition, we are persuaded that Patent Owner’s assertions
`
`regarding the reason whyPetitioner is challenging claim 6 in this proceeding
`
`are mere attorney argument based on speculation. We decline to speculate
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`as to Petitioner’s rationale for challenging the patentability of claim 6. Thus,
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`for all of the foregoing reasons, we determine that the fourth Fintiv factor
`
`weighsslightly against discretionary denial of insUlution.
`
`5. Whether the Petitioner and the Defendant in the Parallel Proceeding
`Are the Same Party
`
`Underthe fifth Fintiv factor, we consider “whether the petitioner and
`
`the defendantin the parallel proceeding are the sameparty.” Fintiv,
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`Paper 11 at 6. Here, Petitioner is the defendant in the District Court
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`12
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`Litigation. Pet. 10-11; Prelim. Resp. 43. Thus, this factor does not weigh
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`against exercising discretionary denial.
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`6. Other Circumstances that Impact the Board’s Exercise ofDiscretion,
`Including the Merits
`
`Underthe sixth Fintiv factor, we consider “other circumstances that
`
`impact the Board’s exercise of discretion, including the merits.” Fintiv,
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`Paper 11 at 6. Petitioner argues that the sixth factor favors institution
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`because“the merits of the Petition are strong.” Pet. 9. Patent Owner argues
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`that the sixth factor favors denial because “the merits of the Petition are
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`weakfor several limitations.” Prelim. Resp. 43.
`
`Weconsideredthe parties’ arguments and evidence of record. As
`discussed below,on this record, Petitioner demonstrates a reasonable
`
`likelihood of prevailing in showingthat at least one of the challenged claims
`
`of the ?300 patent is unpatentable. Nonetheless, we need not decide whether
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`the merits of Petitioner’s asserted groundsare particularly strong becauseit
`
`would not impact our ultimate determination under § 314(a). Thus, we
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`determinethat the sixth Fintiv factoris neutral.
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`7. Balancing the Fintiv Factors
`
`Thus, based on ourholistic view of the Fintiv factors, we decline to
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`exercise our discretion under § 314(a) to deny the Petition.
`
`B. Level of OrdinarySkill in the Art
`
`In determiningthe level of ordinary skill in the art, various factors
`
`may be considered, including the “type of problems encounteredin the art;
`
`prior art solutions to those problems; rapidity with which innovationsare
`made; sophistication of the technology; and educationallevel of active
`
`workersin the field.” Jn re GPAC, Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995)
`
`(quotation omitted).
`
`13
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`Here, Petitioner asserts that a person having ordinary skill in the art
`
`in the technology field of the 300 patent would be a person with
`at least a Bachelor of Science degree in electrical engineering,
`computer engineering, or a closely related field, along with at
`least 3—5 years of experience in the design of non-volatile
`memory devices, An individual with an advanced degree in a
`relevant field would require less experience in the design of non-
`volatile memory devices.
`
`Pet. 31.
`
`Patent Owner’s declarant Dr. Sunil Khatri provides the same
`
`description of a person ofordinary skill in the art. Ex. 2001
`
`22; see also
`
`id. | 23 (noting agreement with Petitioner’s declarant onthis definition).
`Weadopt Petitioner’s description for purposes of this Decision, except that
`
`wedelete the qualifier “at least” to prevent the description from extending
`
`beyondthe level of ordinary skill in the art.
`
`C. Claim Construction
`
`In an inter partes review proceeding basedona petition filed on or
`
`after November13, 2018, a patent claim shall be construed using the same
`claim construction standard that would be used to construe the claim in a
`civil action under 35 U.S.C. § 282(b). 37 C.F.R. § 42.100(b) (as amended
`
`Oct. 11, 2018).? This rule adopts the same claim construction standard used
`
`by Article III federal courts, which follow Phillips v. AWH Corp., 415 F.3d
`
`1303 (Fed. Cir. 2005) (en banc), and its progeny. Underthis standard, the
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`words of a claim are generally given their “ordinary and customary
`
`meaning,” which is the meaning the term would haveto a person ofordinary
`
`skill at the time of the invention, in the context of the entire patent including
`
`2 See Changesto the Claim Construction Standard for Interpreting Claimsin
`Trial Proceedings Before the Patent Trial and Appeal Board, 83 Fed. Reg.
`51,340 (Oct. 11, 2018) (final rule).
`
`14
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`the specification. See Phillips, 415 F.3d at 1312-13. Petitioner proposes
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`constructions for the phrases “data integrity test,” “comparing the stored data
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`to the retained data,” and the term “periodically.” Pet. 23-28. Patent Owner
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`argues that each phrase should haveits plain and ordinary meaning. Prelim.
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`Resp. 17-23. We determine that no claim terms require express construction
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`for purposesof this Decision.
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`D. Overview ofthe Asserted Prior Art
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`1. Dusija (Exhibit 1010)
`
`Dusija notes that “[d]ata errors in non-volatile memory inevitably
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`increase with usage and with higher density of bits stored per cell.” Ex.
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`1010, code (57). In an effort to purportedly address this issue, Dusija
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`discloses a flash memory system having “an array of memory cells is
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`configured with a first portion and a second portion” ; data written in the
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`first portion is rewritten in the second portionif the data in the first portion
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`has excessive errors. Jd. at code (57), | 18. Figure 1 is a block diagram
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`showinga flash memory device, and is reproduced below. Jd. J 29.
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`SENSE MODULES
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`FLASH MEMORY DEVICE 9g
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`Memory Chip 100
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`Momory Areny
`2
`
`FIG. 1
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`15
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`IPR2021-01550
`Patent 10,950,300 B2
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`Figure 1, reproduced above,“illustrates a host in communication with
`
`a memory device.” Jd. As shown in Figure 1, host 80 “sends data to be
`
`stored at the memory device 90.” Id. § 59. To write data to the memory
`
`array of memory device 90, host 80 communicates and interacts with
`
`memory chip 100 via controller 102, which manages memory chip 100. Jd.
`
`{7 59-60. Further, “memory chip 100 includes a memory array 200 of
`
`memory cells with each cell capable of being configured as a multi-level cell
`
`(‘MLC’) for storing multiple bits of data.” Id. 459. Figure 14B depicts
`
`memory array 200 and is reproduced below. Id. { 116; see id. ¢ 109.
`MEMORYARRAY 200
`
`Wess robust but higher density storage)
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`terczzz second copy of data page 22
`
`Input data
`raps
`
` Read
`
`FAILED
`
`REWRITE
`
`First Portion 410
`(more robust but lower densily storage)
`
`FIG. 14B
`Figure 14B, reproduced above,illustrates a rewrite of a second copy
`
`of a data pageinto the first portion of a memory array. [d. 4 45. As shown
`
`in Figure 14B,“array of memorycells 200is partitioned into a first portion
`
`410 and a secondportion 420.” Id. | 109; see id.
`
`116. “[S]econd portion
`
`420 has the memory cells configured as high density storage with eachcell
`
`storing multiple bits of data” while “first portion 410 has the memory cells
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`configured as lower density storage with each cell storing less number of
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`16
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`IPR2021-01550
`Patent 10,950,300 B2
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`bits than that of the second portion.” Jd. | 109. “For example, a memory
`
`cell in the first portion is configured to store 1 bit of data as comparedto 3
`
`bits of data in the second portion.” Jd.
`
`Regarding the data writing process, Dusija explains that, “[w]hen a
`
`page of incomingdata is to he written to the memory array 2.00,it is
`
`preferably stored in the high density second portion for the sake of
`
`efficiency and high capacity.” Jd. 4111. “Later, the first copy of the data
`
`page is read back in a ‘post write read’ to determineif there are any errors.”
`
`Id. J 112. ‘he post write read may be “accomplished .
`
`.
`
`. by comparison
`
`with the original copy which may be cached.” Jd. If a “numberoferrorbits
`
`_
`
`in the data page has exceeded[a] predetermined amount, a second copy of
`the data page is rewritten to the first portion.” Jd. § 116. “The second copy
`
`is of the original data which may he cached.” Jd.
`
`Furthermore,in “an alternative embodiment, the first portion serves as
`
`a cache for incoming data, so a cache copyofthe input data is programmed
`
`into the cache.” Jd. | 127; see id. J¥ 131-134, Figs. 16A—16B. Thatis, in
`
`that embodiment,the first portion of the memory array acts as a cache for
`
`the original data to be written in the second portion of the memory array.
`
`See id. JJ 127-129, 131-134.
`
`2. Sutardja (Ex. 1011)
`
`Sutardja notes that charge storage devices “can sustain a limited
`
`numberof write cycles after which the charge storage devices can no longer
`
`reliably store data.” Ex. 1011 94. In an effort to purportedly addressthis
`
`issue, Sutardja describes a system in which “{l]arge amounts of low cost
`
`memory may be combined with smaller amounts of memory having a higher
`
`write cycle lifetime. The memory having the higher write cycle lifetime can
`
`be used for storing frequently changing data.” Jd. § 102. Sutardja discloses
`
`17
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`IPR2021-01550
`Patent 10,950,300 B2
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`a memory system havinga first nonvolatile semiconductor (NVS) memory
`
`and a second nonvolatile semiconductor (NVS) memory. Jd. at code (57).
`
`Figure 3 of Sutardja is a functional block diagram of such a memory system
`
`and is reproduced below. Id. { 87.
`
`260
`
`Wear Leveling Module
`
`Bata Stifhey
`Module
`
`FIG. 3
`Asshown in Figure 3, the memory systemis a solid state disk drive
`
`and includes“first solid-state nonvolatile memory 204 [that] may include
`
`single-level cell (SLC) flash memory or multi-level cell (MLC) flash
`
`memory”and “second solid-state nonvolatile memory 206 [that] may
`
`include single-level cell (SLC) flash memory or multi-level cell (MLC)flash
`
`memory.” Jd. J 108-109. Eitherthe first or the second NVS memory is
`
`written to, based on respective wearlevels. Jd. 11; see id. { 152.
`
`Further, “wear leveling module [260] may measure or estimate the
`
`wearacrossthe solid-state nonvolatile memories and change the mapping to
`
`equalize wearacross the solid-state nonvolatile memories.” Jd. 4110. “At
`varioustimes, such as periodically, the wear leveling module may analyze
`
`the wear levels of the blocks” of data stored in an NVS memory “and remap.
`
`relatively frequently rewritten logical addresses to blocks with low wear
`
`levels.” Jd. 167. Such “[r]Jemapping may involve swapping data in two
`
`blocks.” Id.
`
`18
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`IPR2021-01550
`Patent 10,950,300 B2
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`E. Obviousness over Dusija
`
`Petitioner asserts that claims 1—9, 11, and 12 are unpatentable under
`
`35 U.S.C. § 103(a) as obvious over Dusija, citing the Declaration of Dr.
`
`David Liu for support. Pet. 31-61 (citing Ex. 1009). Patent Owner,
`
`supported by the Declaration of Dr. Sunil P. Khatri (Ex. 2001), counters that
`Petitioner does not show that Dusija teaches or suggests every limitation
`recited by the claims and that Petitioner did not show it would have been
`
`|
`
`obvious to modify Dusija in the mannerasserted. Prelim. Resp. 44-61.
`
`I.
`
`Independent Claims I and 12
`
`Uponconsideration of parties’ contentions and supporting evidencein
`
`this current record, we are persuaded by Petitioner’s showing andfind that
`
`Petitioner has demonstrated sufficiently for purposes of this Decision that
`the limitations recited in claims 1 and 12 would have been obvious over
`
`Dusija. See Pet. 31-53, 58-61. Independentclaims 1 and 12 recite
`substantially identical language and Petitioner relies on substantially the
`same arguments and evidence for these claims. See id. at 58-61 (arguments
`
`for claim 12 including several mentionsthat limitations are identical or
`
`effectively identical to limitations of claim 1); see also Ex. 1009 JJ 208-216
`
`(Dr. Liu’s testimony noting that limitations of claim 12 are identical or
`
`effectively identical to limitations of claim 1). Thus, we will address these
`
`claimstogether.
`
`a) Summarizing Petitioner ’s Contentions
`Petitioner’s arguments are summarized as follows: With respect to
`3
`
`“[a] system for storing data comprising,” Petitioner asserts
`
`the preamble?
`
`3 We need not decide whetherthe preamble recitation is limiting because,
`Petitioner establishes a reasonable likelihood that Dusija teachesit.
`
`19
`
`
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`TIPR2021-01550
`Patent 10,950,300 B2
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`that Dusija teaches this limitation through its discussion of a flash memory
`
`device that stores data in a memory array. Pet. 32 (citing Ex. 1010 759,Fig.
`
`1;Fx 1009 4 125).
`Asto the limitation “memory space containing volatile memory space
`and nonvolatile memory space,” Petitioner asserts that this limitation would
`
`have been obviousover Dusija. Pet. 33-36 (citing Ex. 1010 J] 59, 61-62,
`
`68, 111-117, Fig. 1; Ex. 1048, 497, 558; Ex. 1019 ¢ 132; Ex. 1028. 9f 27,
`
`32, 119, 197, Fig. 1; Ex. 1049, 12:20-35, 13:24—42, 13:58-14:11; Ex. 1009
`{{ 127-138). Asto the non-volatile memory space,Petitioner directs us to
`Dusija’s discussion offlash memory. Pet. 33.
`Asto the recited volatile memory space, Petitioner directs us to
`
`Dusija’s discussion of caching data. Pet. 33 (citing Ex. 1010 ff 111-117).
`
`According to Petitioner, a person of ordinary skill in the art “would have
`
`understood (and certainly would have found it obvious) that a cacheis
`
`typically implemented in random access volatile memory.” /d. In support
`
`of this assertion, Petitioner directs us to passages from the Microsoft
`
`Dictionary and the Examinertaking official notice of volatile memory often
`used as cache memory during the prosecutionofthe application that led to
`
`the °300 patent. /d. at 33-34 (citing Ex. 1048, 497, 558; Ex. 1008, 48, 78).
`
`Petitioner also directs us to Dusija’s controller that manages memory
`
`operations. Jd. at 34 (citing Ex. 1010 4 62, Fig. 1). Petitioner argues that an
`
`ordinarily skill artisan “would have understood, and at least foundit
`
`obvious,that the controller includes RAM to buffer data and commands,
`
`execute the firmware, and manage the memory operations.” Jd. (citing Ex.
`
`1009 ¥ 130). In addition, Petitioner directs us to Dusija’s reference to
`
`
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`IPR2021-01550
`Patent 10,950,300 B2
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`Paley.’ Id. (citing Ex. 1010
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