Trials@uspto.gov
`571-272-7822
`
`Paper 12
`Date: September 15, 2023
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`XILINX, INC.,
`Petitioner,
`
`V.
`
`POLARIS INNOVATIONSLIMITED,
`Patent Owner.
`
`IPR2023-00516
`Patent 6,157,589
`
`Before JEAN R. HOMERE, BARBARA A. PARVIS, and MINN CHUNG,
`Administrative Patent Judges.
`
`CHUNG,Administrative Patent Judge.
`
`DECISION
`Granting Institution of Inter Partes Review
`3S US.C. $ 314
`
`
`571-272-7822
`
`Paper 12
`Date: September 15, 2023
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`XILINX, INC.,
`Petitioner,
`
`V.
`
`POLARIS INNOVATIONSLIMITED,
`Patent Owner.
`
`IPR2023-00516
`Patent 6,157,589
`
`Before JEAN R. HOMERE, BARBARA A. PARVIS, and MINN CHUNG,
`Administrative Patent Judges.
`
`CHUNG,Administrative Patent Judge.
`
`DECISION
`Granting Institution of Inter Partes Review
`3S US.C. $ 314
`
`
`
`IPR2023-00516
`Patent 6,157,589
`
`I. INTRODUCTION
`
`Xilinx, Inc. (“Petitioner’’) filed a Petition (Paper 2, “Pet.”) requesting
`
`an inter partes review of claims 1, 2, and 8—13 (the “challenged claims’’) of
`
`U.S. Patent No. 6,157,589 (Ex. 1001, “the °589 patent”). Polaris
`
`Innovations Limited (“Patent Owner’) timely filed a Preliminary Response.
`
`Paper 11 (Prelim. Resp.”).
`
`Wehaveauthority to determine whether to institute an inter partes
`
`review. See 35 U.S.C. § 314; 37 C.F.R. § 42.4(a). Under 35 U.S.C.
`
`§ 314(a), institution of an inter partes review is authorized when “the
`
`information presented in the petition... and any response .
`
`.
`
`. showsthat
`
`there is a reasonable likelihood that the petitioner would prevail with respect
`
`to at least 1 of the claims challengedin the petition.” Taking into account
`
`the arguments and evidence presented in Patent Owner’s Preliminary
`
`Response, we determinethat the information presented in the Petition
`
`establishes that there is a reasonable likelihood that Petitioner would prevail
`
`in showing the unpatentability of at least one challenged claim.
`
`Accordingly, we institute an inter partes review ofall challenged claims of
`
`the ’589 patent, based on all groundsraised in the Petition.
`
`Il. BACKGROUND
`
`A. Related Matters
`
`According to the parties, the °589 patent is involved in the following
`
`proceeding: Polaris Innovations Ltd. y. Xilinx, Inc., No. 1:22-cv-00174-
`
`RGA(D. Del.). Pet. 1; Paper 3, 2. Patent Ownerfurther states that the °589
`
`patent is also the subject of Polaris Innovations Limited v. Broadcom,Inc.,
`
`No. 2:22-cv-00347 (E.D. Tex.). Paper 10, 2-3.
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`
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`IPR2023-00516
`Patent 6,157,589
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`B. Real Parties-in-Interest
`
`Petitioner identifies itself, Advanced Micro Devices, Inc., and ATI
`
`Technologies ULCasthe real parties-in-interest. Pet. 1. Patent Owner
`
`identifies itself, Wi-LAN Inc., Owlpoint IP Opportunities JVF LP, and
`
`Quarterhill Inc. as the real parties-in-interest. Paper 10, 2.
`
`C. The ’589 Patent
`
`The *589 patent issued December 5, 2000 from U.S. Patent
`
`Application No. 09/343,431, filed June 30, 1999. Ex. 1001, codes (21), (22),
`
`(45).
`
`The *589 patent describes an initialization circuit for a dynamic
`
`semiconductor memory device (“DRAM”).
`
`/d. at 1:10-13, Abstract. As
`
`background, the ’589 patent describes that for proper operation of a
`
`semiconductor memory device,
`
`1s necessary to ensure during the switch-on operation
`it
`(“POWERUP’)that the internal control circuits .
`.
`. are reliably
`held in a defined desired state, in order to prevent undesirable
`activation of output transistors that would cause, on the data
`lines, a short circuit
`(so-called “bus contention” or “data
`contention”) or uncontrolled activation of internal current loads.
`
`Id. at 1:23-30. According to the °589 patent, “[t]he solution to the problem
`
`turns out to be difficult” due to “a fundamental unpredictability of the time
`
`characteristic of the supply voltage and of the voltage level or levels at the
`
`external control inputs during the switch-on operation of the semiconductor
`
`memory.” /d. at 1:30-35. The *589 patent describes that, to address this
`
`problem, the JEDEC standard for dynamic semiconductor memories
`
`specified that a predeterminedinitialization sequence of commands—e.g., a
`
`sequence comprising PRECHARGE, AUTOREFRESH,and
`
`3
`
`
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`IPR2023-00516
`Patent 6,157,589
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`MODE-REGISTER-SET commands—umustbe applied in a defined
`
`chronological order before proper operation of the control circuits 1s
`
`allowed.
`
`/d. at 1:35-61. According to the °589 patent, “[a]fter the
`
`identification of such a defined initialization sequence, the memory module
`
`is normally in a so-called IDLE state .. . and prepared for proper
`
`operation”—1.e., “all the control circuits of the component have been
`
`unlatched.” /d. at 1:62—67.
`
`Against this backdrop, the °589 patent describes embodiments of a
`
`DRAM initialization circuit that contains a control circuit for controlling
`
`operations and an enable circuit that outputs an enable signal after
`
`identifying a predetermined properinitialization sequence of externally
`
`applied further commandsignals, the enable signal effecting an unlatching
`
`of the control circuit for proper operation of the semiconductor memory
`
`device. /d. at 2:15—37.
`
`Figure | of the *589 patent is reproduced below.
`
`Fig!
`
` internal Voltage
`Regulation and
`Detection
`
`
`
`
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`IPR2023-00516
`Patent 6,157,589
`
`Figure | is a block diagram of components of the *589 patent’s initialization
`
`circuit which controls a switching-on operation of a semiconductor memory
`
`operating according to the JEDEC standard. /d. at 3:28—31, 3:44-48.
`
`With reference to Figure 1, the °589 patent describes:
`
`The initialization circuit has an input circuit 1, to whose input 2
`command and clock signals that are externally applied in
`reference to the semiconductor memory are provided. The
`commandand clock signals are amplified and conditioned before
`being received by a command decoder 3 connected downstream
`of the input circuit
`1 and at whose output 4, inter alia, the
`commandsignals PRE or PRECHARGE(preparation command
`for word line activation), ARF or AUTOREFRESH (refresh
`command) and MRS or MODE-REGISTER-SET (loading
`configuration register command) are output.
`
`Id. at 3:51-61. Theinitialization circuit further includes circuit 5 for internal
`
`voltage regulation and/or detection, which supplies an active POWERON
`
`signal if, after the POWERUPphase of the memory device, the internal
`
`supply voltages present at output 8 have reached the values necessary for
`
`proper operation of the component.
`
`/d. at 3:61—4:8.
`
`According to the 589 patent,
`
`the initialization circuit furthermore has an enable circuit 9
`connected downstream of the circuits 3 and 5. The command
`signals PRE, ARF and MRSare applied to an input 10 of the
`enable circuit 9 and the POWERONsignalis applied to an input
`11 of the enable circuit 9. An enable signal CHIPREADY is
`supplied at an output 12 of the enable circuit 9 after the
`identification of a predetermined properinitialization sequence
`of the commandsignals applied to the semiconductor memory
`device is achieved. The enable signal effects unlatching of
`control circuits
`13 provided for proper operation of the
`semiconductor memory device.
`
`
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`IPR2023-00516
`Patent 6,157,589
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`Id. at 4:9-20.
`
`Figure 2 of the *589 patent is reproduced below.
`
`POWERON
`
`Fig 2
`
`Figure 2 shows an exemplary enable circuit that supplies an enable signal
`
`(CHIPREADY).
`
`/d. at 3:32—33, 4:24—25.
`
`As shown in Figure 2, enable circuit 9 contains three bistable
`
`multivibrator stages 14, 15 and 16, each havinga set input S, a reset input R,
`
`and also an output Q.
`
`/d. at 4:25—28. The commandsignals PRE, ARF,
`
`MRSare applied to the respective set inputs S of the bistable multivibrator
`
`stages 14, 15, 16, whereas the POWERONsignalis applied to the reset
`
`inputs R. /d. at 4:36—-38, 4:41-45.
`
`According to the 589 patent,
`
`activation of the enable signal CHIPREADYatis the output 12
`to logic HIGH is generated only when a predetermined
`chronological initialization sequence of the command signals
`
`6
`
`
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`IPR2023-00516
`Patent 6,157,589
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`PRE, ARF and MRSandactivation of the POWERONsignal to
`the logic level HIGH are detected. Only then are the control
`circuits 13 unlatched on account of the activation of the enable
`signal CHIPREADY.
`
`Id. at 4:50-57.
`
`Figure 3 of the ’589 patent is reproduced below.
`
`SIGNAL
`
`aee
`HIGH
`POWERONeeee LOW
`
`PRE
`
`ARF
`
`MRS
`
`CHIPREADY
`
`
`
`Fig 3
`
`ame
`
`Time
`
`Figure 3 is a schematic time sequence diagram illustrating exemplary
`
`command sequencesdetected by enable circuit 9 of Figure 2.
`
`/d. at 3:34—-35,
`
`4:59-63.
`
`According to the *589 patent,
`
`In case situation C, a correct chronological order of the
`commands
`PRECHARGE,
`AUTOREFRESH, MODE-
`REGISTER-SET1s present conforming to the JEDEC standard,
`in a logically consistent manner, since the POWERONsignal is
`also at logic HIGH, an enable signal CHIPREADY at logic
`HIGHis now supplied.
`Illustrated using dashed lines, another
`further conceivable initialization sequence that is allowed and
`therefore triggers an enable signal is represented by the symbol
`
`7
`
`
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`IPR2023-00516
`Patent 6,157,589
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`D; activation of the command MODE-REGISTER-SETto logic
`LOW is allowed at any time after
`the activation of the
`POWERONsignal.
`
`Td. at 5:10-21.
`
`D. Illustrative Claim
`
`Of the challenged claims, claims 1 and 11 are independent. Claim | is
`
`illustrative of the challenged claims and is reproduced below with line
`
`breaks and indenting added to improvereadability.
`
`1. A dynamic semiconductor memory device of a random
`access type, comprising:
`
`an initialization circuit controlling a switching-on operation
`and supplying a supply voltage stable signal once a supply
`voltage has been stabilized after
`the
`switching-on
`operation,
`
`for
`said initialization circuit having a control circuit
`controlling operations and an enable circuit receiving the
`supply voltage stable signal and externally applied further
`commandsignals,
`
`said enable circuit outputting an enable signal after a
`predetermined proper
`initialization sequence of
`the
`externally applied further
`command signals being
`identified and the enable signal effecting an unlatching of
`said control circuit.
`
`Ex. 1001, 5:31-44.
`
`FE. Prior Art and Declaration Evidence
`
`Petitioner cites the following referencesin its challenge to
`
`patentability:
`
`U.S. Patent No. 5,559,753, issued Sept. 24, 1996 (Ex. 1004, “Kocis”);
`
`
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`IPR2023-00516
`Patent 6,157,589
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`U.S. Patent No. 5,703,510, issued Dec. 30, 1997 (Ex. 1007,
`
`“Tketani”);
`
`U'S. Patent No. 5,774,402, issued June 30, 1998 (Ex. 1005, “Lee’’);
`
`and
`
`JEDEC Standard No. 21-C, Jan. 1997 (Ex. 1006, “JESD 21-C”).
`
`Petitioner supports its challenge with a declaration from Stephen W.
`
`Melvin (Ex. 1003, “Melvin Declaration”). Patent Owner’s Preliminary
`
`Response does not rely on the testimony of any declarant.
`
`F’. Asserted Grounds of Unpatentability
`
`Petitioner asserts that the challenged claims are unpatentable based on
`
`the following grounds(Pet. 3).
`
`
`
`
`
`
` 1,9, 11, 13 Kocis
`
`
`
`2, 8, 10, 12
`
`1,11
`
`1,11
`
`2,8, 10,12
`
`2, 8,10, 12
`
`Kocis, JESD 21-C
`
`Lee
`
`Lee
`
`Lee, JESD 21-C
`
`103
`
`Lee, Iketani, JESD 21-C
`
`' The Leahy-Smith America Invents Act, Pub. L. No. 112-29, 125 Stat. 284
`(2011), amended 35 U.S.C. §§ 102 and 103 effective March 16, 2013.
`Becausethe *589 patent hasa filing date prior to the effective date of the
`applicable AIA amendments, werefer to the pre-AJA versions of §§ 102 and
`103.
`
`
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`IPR2023-00516
`Patent 6,157,589
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`
`
`
`
`Il. ANALYSIS
`
`A. Level of Ordinary Skill in the Art
`
`The level of ordinary skill in the pertinent art at the relevant time is a
`
`factor in how weconstrue patent claims. See Phillips v. AWH Corp., 415
`
`F.3d 1303, 1312-13 (Fed. Cir. 2005) (en banc). It is also one of the factors
`
`we consider when determining whether a patent claim is obvious over the
`
`prior art. See Graham vy. John Deere Co., 383 U.S. 1, 17-18 (1966).
`
`To assess the level of ordinary skill, we construct a hypothetical
`
`“person of ordinary skill in the art,” from whose vantage point we assess
`
`obviousness and claim interpretation. See In re Rouffet, 149 F.3d 1350,
`
`1357 (Fed. Cir. 1998). This legal construct “presumesthat all prior art
`
`referencesin the field of the invention are available to this hypothetical
`
`skilled artisan.” /d. (citing Jn re Carlson, 983 F.2d 1032, 1038 (Fed. Cir.
`
`1993)).
`
`Citing testimony from Dr. Melvin, Petitioner asserts a person of
`
`ordinary skill in the art (“POSITA”) at the relevant time would have had “a
`
`Bachelor’s degree in Electrical Engineering or Computer Science and two
`
`years of experience” or “equivalent education, work, or experiencein this
`
`field.” Pet. 21 (citing Ex. 1003 4§ 31-34). According to Dr. Melvin,
`
`“Tmore education could substitute for experience, and vice versa.”
`
`Ex. 1003 33.
`
`10
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`IPR2023-00516
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`Patent Ownerstates that “[flor the limited purpose of this Preliminary
`
`Response, Patent Ownerdoes not contest Petitioner’s definition of a person
`
`of ordinary skill in the art, but it reserves the right to do so in the event that
`
`trial is instituted.” Prelim. Resp. 11.
`
`For purposes of this Decision, based on our review of the ’589 patent,
`
`the types of problemsand solutions described in the *589 patent, and cited
`
`prior art, we adopt and apply Petitioner’s unopposeddefinition of a person
`
`of ordinary skill in theart.
`
`B. Claim Construction
`
`In an inter partes review, we construe a patent claim “using the same
`
`claim construction standard that would be used to construe the claim in a
`
`civil action under 35 U.S.C. 282(b).” 37 C.F.R. § 42.100(b) (2022). In
`
`applying such standard, claim terms are generally given their ordinary and
`
`customary meaning, as would be understood by a person of ordinary skill in
`
`the art, at the time of the effective filing date of the patent application and in
`
`the context of the entire patent disclosure. Phillips, 415 F.3d at 1312-13.
`
`“In determining the meaning of the disputed claim limitation, we look
`
`principally to the intrinsic evidence of record, examining the claim language
`
`itself, the written description, and the prosecution history, if in evidence.”
`
`DePuy Spine, Inc. v. Medtronic Sofamor Danek, Inc., 469 F.3d 1005, 1014
`
`(Fed. Cir. 2006) (citing Phillips, 415 F.3d at 1312-17).
`
`Petitioner asserts that “construction of terms is unnecessary becauseit
`
`is not dispositive to this case—the art teaches the limitations under any
`
`construction under the Phillips standard.” Pet. 21. Patent Ownerstates that
`
`11
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`IPR2023-00516
`Patent 6,157,589
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`weneed not construe any claim term for purposes of this Decision. See
`
`Prelim. Resp. 11.
`
`Based on the record presented, we need not construe any claim term
`
`for purposesof this Decision. See Realtime Data, LLC v. Iancu, 912 F.3d
`
`1368, 1375 (Fed. Cir. 2019) (“The Board is required to construe ‘only those
`
`terms... that are in controversy, and only to the extent necessary to resolve
`
`the controversy.” (quoting Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200
`
`F.3d 795, 803 (Fed. Cir. 1999))).
`
`C. Asserted Grounds of Unpatentability Based on Lee or the Combination of
`Lee and Iketani
`
`Petitioner contends that independent claims 1 and 11 are unpatentable
`
`under 35 U.S.C. § 103(a) over Lee. Pet. 46-58. In addition, Petitioner
`
`asserts that the subject matter of claims 1 and 11 would have been obvious
`
`over the combination of Lee and Iketani.
`
`/d. at 59-63. Petitioner also
`
`contendsthat claims | and 11 are unpatentable as anticipated by Lee. /d. at
`
`46-58. Patent Owner disputes Petitioner’s contentions. Prelim. Resp. 32—
`
`37.
`
`1. Relevant Principles ofLaw
`
`A claim is unpatentable under 35 U.S.C. § 102 only if a single prior
`
`art reference expressly or inherently describes each and every limitation set
`
`forth in the claim. See Perricone v. Medicis Pharm. Corp., 432 F.3d 1368,
`
`1375 (Fed. Cir. 2005); Verdegaal Bros., Inc. v. Union Oil Co., 814 F.2d 628,
`
`631 (Fed. Cir. 1987). Further, a reference cannotanticipate “unless[it]
`
`discloses within the four corners of the documentnotonly all of the
`
`limitations claimed][,| but also all of the limitations arranged or combined in
`
`12
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`Patent 6,157,589
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`the same wayasrecited in the claim.” Net MoneyIN, Inc. v. VeriSign, Inc.,
`
`545 F.3d 1359, 1371 (Fed. Cir. 2008). Although the elements must be
`
`arranged in the same wayasin the claim, “the reference need not satisfy an
`
`ipsissimis verbis test,”1.e., identity of terminology 1s not required. /n re
`
`Gleave, 560 F.3d 1331, 1334 (Fed. Cir. 2009); In re Bond, 910 F.2d 831,
`
`832 (Fed. Cir. 1990).
`
`A claim is unpatentable under 35 U.S.C. § 103(a) if the differences
`
`between the claimed subject matter and the prior art are such that the subject
`
`matter, as a whole, would have been obviousat the time the invention was
`
`madeto a person having ordinary skill in the art to which the subject matter
`
`pertains. KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007). The
`
`question of obviousnessis resolved on the basis of underlying factual
`
`determinations, including:
`
`(1) the scope and contentof the prior art; (2) any
`
`differences between the claimed subject matter and the priorart; (3) the level
`
`of skill in the art; and (4) where in evidence, so-called secondary
`
`considerations. Graham, 383 U.S. at 17-18.
`
`Additionally, the obviousness inquiry typically requires an analysis of
`
`“whether there was an apparent reason to combine the knownelements in
`
`the fashion claimed by the patent at issue.” KSR,550 U.S. at 418 (citing
`
`In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006) (requiring “articulated
`
`reasoning with somerational underpinning to support the legal conclusion of
`
`obviousness”’)); accord Kinetic Concepts, Inc. v. Smith & Nephew, Inc., 688
`
`F.3d 1342, 1366-67 (Fed. Cir. 2012) (holding that “some kind of motivation
`
`must be shown from somesource, so that the [trier of fact] can understand
`
`whya person of ordinary skill would have thought of either combining two
`
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`or more references or modifying one to achieve the patented [invention]’’)).
`
`Petitioner cannotsatisfy its burden of proving obviousness by employing
`
`“mere conclusory statements.” Jn re Magnum Oil Tools Int’l, Ltd., 829 F.3d
`
`1364, 1380 (Fed. Cir. 2016).
`
`Weanalyze the asserted grounds of unpatentability with the principles
`
`identified above in mind.
`
`2. Overview ofLee (Ex. 1005)
`
`Lee describes an initialization circuit for a semiconductor memory
`
`device, which includes an initialization signal generator that generates an
`
`initialization signal in response to a specific sequence of reset control
`
`signals. Ex. 1005, Abstract.
`
`As background, Lee describes that semiconductor memory devices
`
`require initialization circuits for resetting the various functional circuits
`
`within the chip.
`
`/d. at 1:18—21. According to Lee, conventional
`
`initialization circuits, called “power onreset circuits,” generate a reset signal
`
`in response to a powersupply voltage being applied to the chip. /d. at 1:22—
`
`24. Figure | of Lee (not reproduced herein) describes one such conventional
`
`initialization circuit. /d. at 1:30—45, Fig. 1. Lee describes that conventional
`
`poweron reset circuits may malfunction and fail to initialize the circuits
`
`within the chip if input power supply voltage is unstable.
`
`/d. at 2:4—14.
`
`Against this backdrop, Lee purports to disclose improvedinitialization
`
`circuits that reliably initialize a semiconductor memory device in response to
`
`external logic signals.
`
`/d. at 2:18—23.
`
`14
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`Figure 3 of Lee is reproduced below.
`
`Pe L
`
`@iNIT
`
`_@VCCH|na
`VGSURELYSUPPLY}
`
`VONSeretor|DETECTOR | a
`|
`vecf-
`VOLTAGE. GEN LoOebereAse reccees :
`
`
`sieaSoo
`
`
`
`
`weeeee
`
`DSF
`
`|
`
`@DSF
`
`
` “INPUT
`BUFFER
`
`| 28 @MSH
`
`Figure 3 is a schematic diagram of an embodimentof Lee’s initialization
`
`circuit. /d. at 3:1-3.
`
`As shown in Figure 3, Lee’s exemplary initialization circuit comprises
`
`first initialization signal generator 46, second initialization signal
`
`generator 16, and transfer unit 56.
`
`/d. at 3:10-14. According to Lee, second
`
`initialization signal generator 16, which is “essentially the same”as the
`
`conventional poweronreset circuit of Figure 1, generates a second
`
`initialization signal oINIT in response to the power up of a power supply
`
`VCC. /d. at 3:17-20. First initialization signal generator 46 generatesa first
`
`initialization signal OSET in response to a sequence ofreset control signals
`
`DSF, RASB, and CASB.
`
`/d. at 3:14-16. Transfer unit 56 combinesthefirst
`
`initialization signal OSET and the secondinitialization signal oINIT to
`
`15
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`IPR2023-00516
`Patent 6,157,589
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`generate a reset Signal ORST for resetting the circuits within the memory
`
`device.
`
`/d. at 3:20—23, 4:59-62.
`
`3. Overview ofIketani (Ex. 1007)
`
`Iketani describes a DRAM device with a poweronreset circuit that
`
`initializes the internal circuitry of the DRAM whenthe poweris turned on.
`
`Ex. 1007, 1:7-12.
`
`Figure 6 of Iketani is reproduced below.
`
`FIG, 6
`
`CIRCUIT
`
`CONTROL
`
`|
`
`64
`
`[NODE
`aRCT
`
`51
` MEMORY CELL ARRAY
`
`57
`
`
`
`57
`57
`DATA INPUT/OUTPUT CIRCUIT
`
`Figure 6 is a block diagram showing an example of Iketani’s DRAM for
`
`which a poweronresetcircuit is used. /d. at 2:40-41.
`
`Iketani describes that the DRAM shownin Figure 6 includes memory
`
`cell array 51, control circuit 62 for controlling internal circuitry, and power
`
`on reset circuit 20. /d. at 5:4—20. Iketani further describes that power on
`
`16
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`reset circuit 20 generates a poweron reset signal that initializes the DRAM
`
`circuits, including control circuit 62. /d. at 5:20-26.
`
`4. Independent Claims 1 and 11
`
`Petitioner presents essentially the same analysis regarding
`
`independentclaims | and 11, asserting that the independentclaims recite
`
`similar limitations. See Pet. 58, 61-63. Patent Ownercontests Petitioner’s
`
`showing, addressing claims | and 11 together. Prelim. Resp. 32—37. At this
`
`stage of the proceeding, Patent Owner’s dispute mostly focuses on the
`
`limitation “the enable signal effecting an unlatching of said control circuit”
`
`recited in claim 1. Seeid.
`
`Because the parties do not dispute, and we agree, that claims 1 and 11
`
`recite substantially similar limitations, our discussion below focuses on
`
`claim 1. Unless otherwise noted, our analysis below applies equally to both
`
`independent claims 1 and 11.
`
`Figure 3 of Lee as annotated by Petitioner is reproduced below.
`
`
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`17
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`IPR2023-00516
`Patent 6,157,589
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`Pet. 48. Annotated Figure 3 of Lee reproduced aboveillustrates Petitioner’s
`
`alleged identification in Lee of certain elements of claim 1.
`
`/d. at 48—50.
`
`Referencing annotated Figure 3 of Lee reproduced above,Petitioner
`
`asserts that Lee discloses the recited “initialization circuit” (Lee’s circuit
`
`components 12, 14, 16, 46, and 56, annotated in yellow) for “controlling a
`
`switching-on operation and supplying a supply voltage stable signal.”
`
`Pet. 48 (citing Ex. 1003 § 120). Petitioner contends that Lee’s initialization
`
`circuit controls a switching-on operation(1.e., the process for powering on
`
`the memory chip) because
`
`these types of “initialization circuits are
`Lee explains that
`typically referred to as power on reset circuits and generate a
`reset signal in response to a power supply voltage VCC being
`applied to the [DRAM] chip. The typical power on reset circuit
`operates by sensing the level of the power supply voltage VCC
`and generating an initialization signal for a predetermined length
`of time when the power supply voltage reaches a predetermined
`level.”
`
`Id. at 48—49 (quoting Ex. 1005, 1:18—29). Petitioner further asserts that the
`
`oINIT signal in Figure 3 of Lee (annotated in green in annotated Figure 3 of
`
`Lee reproduced above) teaches the recited “supply voltage stable signal”
`
`because Lee’s oINIT signal is generated in response to the power-up of a
`
`power supply VCC. /d. at 49-50 (citing Ex. 1005, 1:31-34, 1:47—54, 3:9-
`
`23; Ex. 1003 § 123).
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`18
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`
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`IPR2023-00516
`Patent 6,157,589
`
`Figure 3 of Lee as annotated and modified by Petitioner is reproduced
`
`below.
`
` OUILEIEILEIELLIISLLILIDLELELLIIEPLSISIESLETDLES,$Ҥ
`
`
`
`Pet. 51 (citing Ex. 1003 § 125). Petitioner-modified Figure 3 of Lee
`
`reproduced aboveillustrates Petitioner’s contentions regarding Lee’s alleged
`
`teachings of certain elements of claim 1, including the recited “enable
`99 ¢¢
`
`circuit,”
`
`“enable signal,” and “control circuit.” /d. at 48-58.
`
`Referencing modified Figure 3 of Lee reproduced above, Petitioner
`
`asserts that Lee’s first initialization signal generator 46 and transfer unit 56
`
`(annotated in blue above) disclose “an enable circuit receiving the supply
`
`voltage stable signal and externally applied further commandsignals,” as
`
`recited in claim 1, because Lee’s enable circuit “receives both the supply
`
`voltage stable signal (shownin green above) and externally applied further
`
`commandsignals (shown in brown above).” Pet. 51. Petitioner explains
`
`that, as shownin Figure 3 of Lee, transfer unit 56 of Lee’s enable circuit
`
`19
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`IPR2023-00516
`Patent 6,157,589
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`receives the OINIT signal (the claimed “supply voltage stable signal”).
`
`/d.
`
`(citing Ex. 1005, 4:33-35, 4:59-62, Fig. 3).
`
`Petitioner further contends that the CASB, RASB, and DSFsignals
`
`(annotated in brown in modified Figure 3 of Lee reproduced above), which
`
`are received byfirst initialization signal generator 46 of Lee’s enable circuit,
`
`teach the recited “externally applied further commandsignals” because a
`
`person of ordinary skill in the art would have understood that Lee’s CASB,
`
`RASB, and DSFsignals are similar to and related to the PRECHARGE,
`
`AUTOREFRESH, and MODE-REGISTER-SET commandsdescribed in the
`
`°589 patent as examples of the claimed “externally applied further command
`
`signals.” Pet. 52—53 (citing Ex. 1001, 2:50—54; Ex. 1005, 3:14—16, 3:37-49;
`
`Ex. 1003 9 127, 128; Ex. 1019, 10). In particular, Petitioner relies on the
`
`testimony of Dr. Melvin that “the CASB and RASBsignals are further
`
`commandsignals because a POSITA would have understood that they can
`
`be used to generate the PRECHARGE, AUTOREFRESH, and MODE-
`
`REGISTER-SET commandsdisclosed in the *589 Patent.” Ex. 1003 § 128.
`
`In support of his testimony, Dr. Melvin cites to a “TRUTH TABLE”ina
`
`DRAMspecification that describes how the Precharge, Auto Refresh, and
`
`Mode Register Set commandsare related to the CAS and RASsignals. /d.
`
`(citing Ex. 1019, 10).
`
`Further, Petitioner asserts that Lee’s reset signal ORST (annotated in
`
`purple above in modified Figure 3 of Lee reproduced above, the claimed
`
`“enable signal”) output by Lee’s enable circuit teaches “said enable circuit
`
`outputting an enable signal after a predetermined properinitialization
`
`sequence of the externally applied further commandsignals being
`
`20
`
`
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`IPR2023-00516
`Patent 6,157,589
`
`identified,” as recited in claim 1, because Lee describes that the reset signal
`
`ORSTis activated only after the CASB, RASB, and DSFsignals produce “a
`
`predetermined bit pattern in the proper sequence.” Pet. 55—56 (citing
`
`Ex. 1005, 4:38-61).
`
`Next, Petitioner asserts that a person of ordinary skill in the art would
`
`have understood that Lee teaches or renders obvious “a control circuit for
`
`controlling operations” recited in claim 1 because a person of ordinary skill
`
`in the art would have understood that Lee includes “a control circuit that
`
`receives external commandsand controls the internal operation of the
`
`memory device so as to properly respond to the commands.” Pet. 54 (citing
`
`Ex. 1003 4 130). As discussed above, Petitioner contends that Lee’s
`
`external commandsinclude the CASB and RASB commands, which are
`
`described in Lee as a “first control signal” and a “second control signal”
`
`used to control the read operation of the memory device. /d. at 52 (citing
`
`Ex. 1005, 3:37-49; Ex. 1003 § 127). In the cited paragraph ofhis
`
`Declaration, Dr. Melvin states that “CASB is a column addressstrobe signal
`
`and RASBis arow address strobe signal,” which are “primarily used to
`
`instruct the memory chip to activate or open a row and then to read a column
`
`within the activated row.” Ex. 1003 § 127. Dr. Melvin provides a similar
`
`explanation in the “Technology Background”section of his Declaration,
`
`citing a DRAMspecification as support.
`
`/d. 7 53 (citing Exs. 1017, 1018).
`
`Petitioner further contends that a person of ordinary skill in the art
`
`would have understood that Lee’s reset signal ORST initializes the control
`
`circuit because Lee discloses that the reset signal initializes “circuit[s] within
`
`the memory device”or “circuit[s] within the chip.” Pet. 53-55 (citing
`
`21
`
`
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`IPR2023-00516
`Patent 6,157,589
`
`Ex. 1005, 1:20-21 (“[Semiconductor memory] devices require initialization
`
`circuits for resetting the various functional circuits within the chip.”), 3:19-
`
`22 (“The transfer unit 56 generates a reset signal ORST for resetting a circuit
`
`within the memory device responsive to the first and second initialization
`
`signals.”), 4:20—24 (“transfer unit 56 for sending the reset signal ORST to a
`
`circuit to be initialized within the chip’), 4:35-37 (“all circuits within the
`
`chip which are connected to the output terminal of transfer unit 56 [are] held
`
`in the initialized state”), 4:59-62 (“The transfer unit 56 .
`
`.
`
`. activates the
`
`reset signal ORST.. . thereby initializing the circuits within the chip.”),
`
`5:11—13). Petitioner’s contention is illustrated by Petitioner’s modification
`
`of Figure 3 of Lee (reproduced above) to add a Control Circuit (in red color)
`
`that receives the reset signal ORST.
`
`/d. at 51, 53.
`
`In the alternative, Petitioner asserts that the combination of Lee and
`
`Iketani teaches the recited “control circuit.” Pet. 59-63.
`
`Annotated and modified Figure 6 of Iketani illustrating Petitioner’s
`
`proposed combination of Lee and Iketani is reproduced below.
`
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`22
`
`
`
`IPR2023-00516
`Patent 6,157,589
`
`Pet. 60. The figure reproduced above showsPetitioner’s illustration of the
`
`proposed combination of Lee and Iketani.
`
`/d. at 59-61.
`
`Asillustrated in the Petitioner-modified Figure 6 of Iketani
`
`reproduced above, in the proposed combination of Lee and Iketani, Lee’s
`
`initialization circuit replaces Iketani’s power on reset circuit 20, with Lee’s
`
`reset signal ORST providingthe initialization signal for Iketani’s control
`
`circuit. Pet. 59-60. Petitioner contends that a person of ordinary skill in the
`
`art would have recognized that the initialization circuit of Lee is compatible
`
`with the controller of Iketani because “[b]oth the power on reset circuit of
`
`Iketani and the initialization circuit of Lee perform similar functions and are
`
`used for the same purpose.” /d. (citing Ex. 1005, 2:4—6, 2:18—20; Ex. 1007,
`
`2:1-4; Ex. 1003 4 140). Citing Iketani’s disclosure that the power on reset
`
`signal generated by Iketani’s poweronreset circuit 20 is supplied to control
`
`circuit 62 of Iketani, Petitioner asserts that “a POSITA would have
`
`understood that Lee’s initialization circuit is... compatible with Iketani’s
`
`control circuit.” /d. at 61 (citing Ex. 1007, 5:20—26; Ex. 1003 4 142).
`
`Petitioner argues that Lee and Iketani expressly provide the
`
`motivation to combine the references because “[w]hile Lee does expressly
`
`illustrate the ‘circuitry’ that is initialized by the reset signal ORST output
`
`from its initialization circuit, Iketani illustrates and describes in detail the
`
`variouscircuits, including the controlcircuit, that receive and are initialized
`
`by such an initialization signal.” Pet. 59 (emphasis added) (citing Ex. 1003
`
`4] 140). Petitioner further asserts that the proposed combination “amountsto
`
`a simple substitution of one component(1.¢e., Lee’s initialization circuit) for
`
`another (1.e., Iketani’s poweron reset circuit), and a POSITA would have
`
`23
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`
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`IPR2023-00516
`Patent 6,157,589
`
`understood that this substitution would yield predicable results.” /d. at 61
`
`(citing Ex. 1003 § 143).
`
`Lastly, Petitioner contends that Lee’s reset signal ORST (the claimed
`
`“enable signal”) teaches “the enable signal effecting an unlatching of said
`
`control circuit,” as recited in claim 1, because a person of ordinary skill in
`
`the art would have understoodthat initialization of the control circuit
`
`“causesthe start of normal operation”of the control circuit. Pet. 57 (citing
`
`Ex. 1005, 4:13-24, 4:59-5:4; Ex. 1003 4 133). In the combination of Lee
`
`and Iketani, Petitioner further argues that “the control circuit is unlatched by
`
`an enable signal through Iketani’s disclosure that the control circuit is
`
`initialized by the reset signal.” /d. at 63 (citing Ex. 1007, 5:12—26; Ex. 1003
`
`44 148, 151).
`
`In the Preliminary Response, Patent Ownerasserts that Lee “contains
`
`no disclosure that this [reset signal ORST] .. . unlatches any control circuit
`
`for normal operation.” Prelim. Resp. 33. Similarly, Patent Ownerargues
`
`that “[l]ike Lee, the initialization of the control circuit as described in Iketani
`
`fails to disclose that the control circuit is unlatched for operation.” /d. at 37.
`
`Although we agree with
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