Docket No.: 49657-318
`
`|
`
`UTILITY PATENT APPLICATION
`UNDER37 CFR1.53(b)
`
`gre Hy
`92,|all
`135
`09/26;5My
`MOAN
`
`“Box PATENT APPLICATION
`mAssistant Commissioner for Patents
`= AWashington, DC 20231
`Sir:
`
`Transmitted herewith for filing is the patent application of:
`
`INVENTOR: Hideto HIDAKA
`FOR: SEMICONDUCTOR MEMORY DEVICE WITH IMPROVED FLEXIBLE
`REDUNDANCY SCHEME
`
`Mlng6g°!
`OHAO
`
`oa
`no
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`Enclosedare:
`Xx
`83 pagesof specification, claims, abstract.
`i]
`Declaration and Powerof Attorney.
`><]
`Priority Claimed.
`x Certified copy of|Japanese Patent Application No. 10-160466 and Japanese Patent
`Application No. 10-293421
`31 sheets of formal drawing.
`An assignment of the invention to Mitsubishi Denki Kabushiki Kaisha
`and the assignment recordationfee.
`An associate powerofattorney.
`A verified statement to establish small entity status under 37 CFR 1.9 and 37 CFR 1.27.
`Information Disclosure Statement, Form PTO-1449andreference.
`Return Receipt Postcard
`
`
`
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`6
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`\]
`Xx
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`LJ
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`he filing fee has been calculated as shown below:
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`NO. OF
`CLAIMS |
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`
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`Total Claims
`Independent Claims
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`20
`4
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`+}
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`s
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`$0.00
`$18.00
`__—|_—
`$78.00
`$78.00
`Multiple Dependent Claim(s)
`$0.00
`
`Basic Fee
`$760.00
`|
`
`Total of Above Calculations
`$838.00
`
`Less % for Small Entity
`$0.00
`
`Assignment & Recording Fee
`$40.00|
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`eS +s & RK S|
`a
`=
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`4 a
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`RATE
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`AMOUNT
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`xX]
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`x
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`Xx
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`Please charge my Deposit Account No. 500417 in the amount of $878.00. A duplicate
`copy ofthis sheet is enclosed.
`The Commissioner is hereby authorized to charge payment of the following fees
`associated with this communication or credit any overpayment to Deposit Account No.
`500417. A duplicate copy is enclosed.
`Any additionalfiling fees required under 37 CFR 1.16.
`
`The Commissioner is hereby authorized to charge payment of the following fees during
`the pendency of this application or credit any overpayment to Deposit Account No.
`500417. A duplicate copy ofthis sheet is enclosed.
`<j Anypatent application processing fees under 37 CFR 1.17.
`Anyfiling fees under 37 CFR 1.16 for presentation of extra claims.
`
`Respectfully submitted,
`
`MCDERMOTT, WILL & EMERY
`}
`fife.
`
`
`
`) J ON
`
`Stephen A. Becker
`Registration No. 26,527
`
`
`
`3
`Q
`
`600 13" Street, N.W.
`Washington, DC 20005-3096
`(202) 756-8000 SAB:dtb
`Date: February 17, 1999
`Facsimile: (202) 756-8087
`
`

`

`TITLE OF THE INVENTION
`Semiconductor Memory Device with Improved Flexible Redundancy
`Scheme
`
`BACKGROUNDOF THE INVENTION
`
`Field of the Invention
`
`The present invention relates generally to semiconductor memory
`devices, and more particularly, to a semiconductor memory device having a
`memory array divided into a plurality of memory blocks. Morespecifically,
`the present invention relates to a redundancycircuit for repairing a
`defective memorycell in a semiconductor memory device having such an
`array-divided arrangement and a powersupply circuit provided
`corresponding to each block.
`Description of the Background Art
`In the semiconductor memory device, a defective memorycell is
`replaced with a spare memorycell in order to equivalently repair the
`defective memorycell to raise the yield of the products. A flexible
`redundancy schemehas been proposed in order to improve the use
`efficiencies of spare lines (wordlinesor bit lines) and spare decoders for
`selecting spare lines in a redundancycircuit configuration including spare
`memory cells (spare wordlines andbit lines) for repairing such defective
`memory cells (see, for example, "A Flexible Redundancy Techniquefor
`High-Density DRAM's", Horiguchi et al., IEEE Journal of Solid-State
`Circuits, Vol. 26, No. 1, January 1991, pp. 12 to 17).
`Fig. 53 is a schematic diagram of the general configuration of a
`semiconductor memory device having a conventional flexible redundancy
`scheme.
`In Fig. 53, the semiconductor memory device includes four
`memory arrays MAO to MA3.
`In each of memory arrays MAO to MA3, a
`spare wordline to repair a defective memorycell row is provided.
`In
`memory array MAO, spare word lines SW00 and SW01 are provided, and in
`memory array MA1, spare word lines SW10 and SW11 are provided.
`In
`memory array MA2, spare word line SW20 and SW21 are provided, and in
`memory array MA3, spare word lines SW30 and SW31 are provided.
`Row decoders XO to X3 each for decoding an addresssignal to drive a
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`normal word line provided corresponding to an addressed row into a
`selected state are provided corresponding to memory arrays MAO to MAS.
`A column decoder YO is provided between memory arrays MAO and MAIto
`decode a column addresssignal to select an addressed column, and also a
`column decoder Y1 is provided between memory arrays MA2 and MA3.
`The semiconductor memory device furtherincludes spare decoders
`SDO to SD3 to store a row address at which a defective memorycell is
`present, maintain a word line (defective normal word line) corresponding to
`this defective row address in a non-selected state when the defective row is
`addressed and drive a corresponding spare wordline into a selected state,
`an ORcircuit GO to receive output signals from spare decoders SDO and
`SD1, and an ORcircuit G1 to receive output signals from spare decoders
`SD2 and SD3.
`
`The output signals of OR circuits GO and G1 are provided in common
`to spare word line drivingcircuits included in row decoders XO to X3.
`Spare decoders SDO to SD3 are commonlyprovided with array address
`signal bits an-2 and an-1 to address one of memory arrays MAO to MA3 and
`with intra-array addresssignals bits a0 to an-3 to address a row in the
`memory array. Row decoders X0 to X3 are provided with array address
`signal bits an-2 and an-1, and a row decoderis activated when a
`corresponding memory array is addressed. OR circuits GO and G1 each
`correspond to two spare word lines provided for each of memory arrays
`MAO to MA3.
`
`Let us assume that normal word lines WO and W1 are defective in
`memory array MAO, that a normal word line W2 in memory array MAIis
`defective, and that a normal word line W3 in memory array MA2 is
`defective.
`In this state, the address of word line WOis programmedin
`spare decoder SDO, while the address of word line W1 is programmedin
`spare decoder SD2. The address of normal word line W2 is programmedin
`spare decoder SD3, and the address of normal word line W3 is programmed
`in spare decoder SD1.
`OR circuit GO selects one of spare word lines SW00, SW10, SW20
`and SW30, and the outputsignal of OR circuit G1 selects one of spare word
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`lines SW1, SW11, SW21 and SW31.
`When normal word line W0is addressed, the output signal of spare
`decoder SDOis driven into a selected state, and the output of OR circuit GO
`is activated.
`In this state, array address signal bits an-2 and an-1 activate
`row decoder XO, and the remaining row decoders X1 to X3 are maintained
`in a non-active state. Thus, a word line driving circuit included in row
`decoder XO drives spare word line SWO0 into a selected state in response to
`the output signal of OR circuit GO. At this time, in row decoder XO, a
`decode circuit provided corresponding to normal word line W0 is
`maintained in a non-active state. As aresult, defective normal word line
`W0is replaced with spare word line SWO0.
`Tf defective normal word line W1 is addressed, the output signal of
`spare decoder SD2 attains an H level in a selected state, the output signal
`of OR circuit G1 attains an H level, and spare word line SW01 is selected.
`If defective normal word line W2 is addressed, the output signal of spare
`decoder SD3 attains an H level in a selected state, the output signal of OR
`circuit G1 attains an H level, and spare word line SW11 is selected.
`If
`defective normal word line W3is addressed, the output signal of spare
`decoder SD1 attains an H level in a selected state, and spare word line
`SW20 is selected by OR circuit GO accordingly. More specifically, defective
`normal word lines W0, W1, W2 and W3are replaced with spare word lines
`SW00, SW01, SW11 and SW20, respectively.
`In this flexible redundancy scheme shownin Fig. 53, a single spare
`word line can be activated by any of a plurality of spare decoders. For
`example, spare word line SW20 can be driven into a selected state by spare
`decoder SDO or SD1. A single spare decoder can drive any of a plurality of
`spare word line into a selected state. For example, spare decoder SDO can
`drive any of spare word lines SW00, SW10, SW20 and SW30 into a selected
`state. Thus, the spare word line and spare decoders do not correspond in
`one-to-one relation, and therefore the spare word lines and spare decoders
`can be moreefficiently utilized. The numberof spare wordlines and the
`numberof spare row decoders in a single memory array maybeselected
`independently from each other as long as the numberssatisfy the following
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`relation:
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`L=sRsMLim
`.
`wherein M is the number of physical memory arrays, m the numberof
`memory arrays whose defective normal word lines are replaced with spare
`word lines simultaneously, R the number of spare row decoders, and L the
`numberof spare wordlines in a single memory array. Morespecifically,
`M/m is the number of memory arrays which are logically independent from
`one another. As aresult, M-L/m represents the number of spare word
`lines which are logically independent from one anotherfor the entire
`memory. Herein, the logically independent spare word lines are spare
`word lines selected by different row addresses. For example, in Fig. 53, if
`a normal word line is simultaneously selected in memory arrays MAO and
`MA2, memory arrays MAO and MA2 are not logically independent from
`each other.
`In the arrangement shown in Fig. 53, L=2, R=4, M=4 and m=1.
`By providing a spare row decoder common to memory arrays, a spare
`decoder does not have to be provided for each of spare word lines, which can
`restrain the chip area from increasing.
`The flexible redundancy scheme shown in Fig. 53 may be employed
`for repairing a defective column as well.
`In repairing a defective column,
`the previously mentioned prior art document describes a method of
`repairing a defective column where a memoryarrayis divided into a
`plurality of sub-arrays. The document particularly describes the way of
`repairing a defective column in multi-divided bit lines in a shared-sense
`amplifier arrangement and in a shared I/O scheme.
`Fig. 54 is a schematic diagram of the configuration of an array
`portion in a semiconductor memory device according to a conventional
`flexible redundancy scheme.
`In Fig. 54, two memory blocks MBi and
`MBi+1 are shown. Memory blocks MBi and MBi+1 each include a normal
`bit line pair BL and /BL provided corresponding to each memorycell
`column and a spare bit line (spare column)for repairing a defective column.
`In Fig. 54, the spare bit line included in the spare columnis not clearly
`shown.
`
`Normal bit lines BL and /BL at the same column address in memory
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`blocks MBi and MBi+1 share a sense amplifier SA.Abit line isolation
`gate ILG is provided between sense amplifier SA and memory blocks MBi
`and MBit+1. Sense amplifier SA is connected to an internal data line pair
`I/O through an IO gate IOG which conducts in response to a column
`selecting signal YS from column decoder Y. A memory block including a
`selected memorycell (MBi, for example) is connected to sense amplifier SA
`and data is read out therefrom.
`In this case, a non-selected memory block
`(MBi+1) is disconnected from sense amplifier SA.
`In the above-described shared-sense amplifier arrangement, a
`defective column address must be programmedfor each of defects in normal
`bit lines, in a single memory block columnselecting lines (YS lines) and
`sense amplifiers SA. For a normal bit line defect, the defective column
`address is programmed on a memoryblock basis. For a sense amplifier
`defect, the defective column address is so programmedas to use a spare
`column for each of memory blocks MBi and MBit+1 which sharethis
`defective sense amplifier. For a columnselecting line (YS line) defect, the
`defective column addressis programmedfor each of the memory blocks
`connected to this columnselecting line (YS line).
`At the time of programming, in order to use a single spare column
`decoder for a normal bit line defect, a sense amplifier defect and a column
`selecting line (YS line) defect, "Don't care" is programmedat the timeof
`programminga defective column address, an address to specify a memory
`block is invalidated, and spare columnsare replaced simultaneously in a
`plurality of memory blocks.
`In the previously mentioned document, a defective row is repaired by
`replacing the defective row with a spare wordline provided within a
`memory array including that defective row. Thus, a spare word line must
`be providedfor each of memory arrays, and the spare word lines are not
`efficiently utilized.
`Ifa defective normal word line in one memoryarray is
`replaced with a spare wordline in another memoryarray, the control of the
`memory array related circuits will be complicated, and therefore such
`arrangement must be avoided andis not consideredatall.
`In repairing a defective column, a spare columnis provided for each
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`of memory blocks, and spare columnsare similarly not efficiently used.
`Although the shared I/O scheme has been considered for internal data line
`arrangement, the way to repair a defective column in a memory array
`having a local/global hierarchical data line arrangement used in a recent
`block-divided arrangement has never been considered.
`Meanwhile, in a conventional CMOS (Complimentary MOS) type
`semiconductor device, the size of components (MOStransistor: insulated
`gate type field effect transistor) is reduced to increase the integration
`density.
`In order to secure the reliability of the components thus
`miniaturized and to reduce the current consumedby the entire device, the
`power supply voltage is reduced.
`In order to allow the components to
`operate at a high speed, the threshold voltage of the MOStransistor must
`be lowered depending upon the power supply voltage. This is becauseif
`the ratio of the threshold voltage to the power supply voltage is large, the
`transition timing of the MOStransistor to the on stateis delayed.
`If,
`however, the absolute value of the threshold voltage is lowered, sub-
`threshold leakage current to flow through the source-drain region when the
`MOStransistoris turned off increases. This is for the following reason.
`The threshold voltage is defined as the gate-source voltage to allow a
`prescribed drain current to flow.
`In an n-channel MOStransistor, if the
`threshold voltage is lowered, the drain current-gate voltage characteristic
`curve shifts toward the negative direction. The sub-threshold current is
`represented by the current value when gate voltage Vgs in the
`characteristic curve is OV, and therefore the sub-threshold current
`increases as the threshold voltage is lowered.
`When the semiconductor device operates, the ambient temperature
`increases, and the absolute value of the threshold voltage of the MOS
`transistor is lowered, resulting in more serious sub-threshold current
`leakage. When this sub-threshold leakage current increases, the DC
`current of the entire large scale integrated circuit increases, and
`particularly in a dynamic type semiconductor memory device, the stand-by
`current (current consumed in a stand-by state) increases.
`In order to reduce the sub-threshold leakage current, a multi-
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`threshold-voltage CMOS arrangement is employed.
`Fig. 55 is a diagram showing a conventional multi-threshold-voltage
`CMOSarrangement by wayof illustration.
`In Fig. 55, there are provided
`a main power supply line 902 transmitting a power supply voltage Vcc, a
`sub-power supply line 904 coupled to main power supply line 902 through a
`p-channel MOStransistor 903, a main groundline 906 transmitting a
`ground voltage Vss, and a sub-groundline 908 coupled to main ground line
`906 through an n-channel MOS transistor 907. MOStransistor 903
`conducts when an activation signal /pACT is at an L level, while MOS
`transistor 907 conducts when an activation signal ¢ACTis at an H level.
`MOStransistors 903 and 907 each have a relatively high threshold voltage
`(high-Vth). The internal circuit operates, with a voltage from one of power
`supply lines 902 and 904 and a voltage from one of groundlines 906 and
`908 used as both operation power supply voltages.
`In Fig. 55, as the
`internal circuit, three-stage, cascaded invertercircuits 914a, 914b and 914c
`are shown.
`Inverter circuit 914a includes a p-channel MOStransistor PQ
`having a source coupled to main power supply line 902, and an n-channel
`MOStransistor NQ having a source coupled to ground line 908. An input
`signal IN is provided in commonto the gates of MOStransistors PQ and
`NQ.
`Input signal IN is set to an L level in a stand-bycycle.
`Inverter circuit 914b operates using voltages on sub-power supply
`line 904 and main ground line 906 as both operation power supply voltages.
`Inverter circuit 914c operates with voltages on main power supply line 902
`and sub-ground line 908 as both operation power supply voltages. MOS
`transistors PQ and NQ in eachof these inverter circuits 914a to 914c have
`the absolute values of the threshold voltages set sufficiently small (dow-Vth).
`The operation of the circuit shown in Fig. 55 will be now described with
`reference to Fig. 56.
`In a stand-bycycle, input signal IN is set to an Llevel. Control
`signal pACTis at an L level, and control signal /bACTis at an H level (Vcc
`level).
`In inverter circuit 914b, MOStransistor PQ turns on, the source
`and drain thereof are at the same voltage level, and therefore no current is
`allowed to flow. Meanwhile, MOStransistor NQ is provided with input
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`signal IN at the ground voltage level at its gate and is in anoff state.
`However, the sub threshold leakage current allowed to flow through MOS
`transistor 907 in an off state is sufficiently reduced, because the threshold
`voltage of the transistor 907 is high. As a result, the sub-threshold
`current is reduced evenif the threshold voltage of MOS transistor NQ is
`small. The sub-threshold current allowed to flow through MOStransistor
`907 causes the voltage level on sub-ground line 908 to be higher than the
`ground voltage level, so that the gate-source region of MOS transistor NQ
`in invertercircuit 914a is set to a reverse bias state, and its sub-threshold
`current is further reduced.
`In inverter circuit 914b, the input signal is at an H level, and MOS
`transistor NQ is turned on, the source and drain thereof are at the same
`voltage level and therefore no sub threshold leakage current is generated.
`Meanwhile, p-channel MOStransistor PQ is provided with a signal at
`powersupply voltage Vcc level at its gate to allow sub-threshold leakage
`current to flow. However, since MOStransistor 903 is in an off state and
`MOStransistor 903 is a high-Vith transistor, the sub-threshold leakage
`current is sufficiently restrained. Thus, the sub-threshold leakage current
`in invertercircuit 914b is restrained. The sub-threshold leakage current
`of MOStransistor 903 causes the voltage level of sub-power supply line 904
`to be lower than power supply voltage Vcc, and the gate-source region of
`MOStransistor PQ is reversedly biased in inverter circuit 914b, the sub-
`threshold leakage current of which is further restrained. Similarly to
`inverter circuit 914a, the sub-threshold leakage currentis restrained in
`inverter circuit 914c.
`
`When an active cycle is started, control signal 6ACT attains an H
`level, control signal /pACT attains an L level, MOS transistors 903 and 907
`are turned on, sub-power supply line 904 is coupled to main power supply
`line 902, and sub-ground line 908 is coupled to main ground line 906.
`Thus, these inverter circuits 914a to 914c are supplied with a current from
`a corresponding powersupply line/groundline, their low-Vth transistors
`operate at a high speed, and their output signals are changed accordingto
`changein inputsignal IN.
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`In the power supply circuit arrangement as shown in Fig. 55, since
`the logical level of an input signal in a stand-by cycle is previously known,
`a connection path to a power source line is determined accordingly.
`Ifthe
`logical state of input signal IN in a stand-by cycle is not predetermined, the
`logic gate is coupled to sub-powersupply line 904 and sub-groundline 908.
`As disclosed in Japanese Patent Laying-Open No. 6-232348, ina
`DRAM (Dynamic Random Access Memory), circuits having the samecircuit
`configuration such as decode circuits and wordline drive circuits are
`provided. As the storage capacity increases, the numberof such circuits
`significantly increases.
`In repeating circuitry having repeatedly provided
`decode circuits and wordline drive circuits, a prescribed numberof
`particular circuits (addressed circuits) are selectively driven among the
`circuits having the same configuration in response to an address signal.
`these circuits are formed by low-Vth transistors, the power supply circuit
`arrangement as shown in Fig. 55 (hierarchical power supply arrangement:
`sub-threshold leakage current reducingcircuit) may be employed.
`In this
`case, as shown in Fig. 53, activation/nactivation of a power supply toa
`decoder or a wordline driver must be controlled for each of the blocks
`
`If
`
`(because a wordlineis selected on a block basis.) Control signals 6ACT
`and /pACT are activated when an active cycle is started. Asa result, the
`number of circuits connected to sub-power supply line 904 or sub-ground
`line 908 increases, and as the parasitic capacitance increases, it takes
`longer time until sub-power supply line 904 and sub-ground line 908 are
`driven to prescribed voltage (Vcc and ground voltage Vss) levels and
`therefore the operation starting timings of the internal circuits should be
`delayed until these voltages becomes stable, which impedes high-speed
`accessing operations.
`As previously described, when a defective row/columnis repaired
`using a spare decoder, a row/column to be selected is determined after
`determining if a spare is to be used/not used.
`In this case, as shown in Fig.
`53, if redundancy replacement is performed within the sameblock, a
`corresponding powersupplycircuit (a circuit transmitting any of the power
`supply voltage and groundvoltage) can be selected in response to an
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`If, however, a spare row/column
`addresssignal to control the connection.
`is used for repairing a defective cell in another memoryblock in the flexible
`redundancy arrangement, a memory block including a memorycell to be
`driven into a selected state must be specified according to a spare
`determination result, the power source voltage (power supply voltage and
`ground voltage) cannot be driven into a stable state at a high speed, and
`high speed accessing operations cannot be implemented.
`SUMMARYOF THE INVENTION
`It is an object of the present invention to provide an array-divided
`semiconductor memory device including a redundancycircuit, which
`permits the use efficiency of spare lines (spare wordlines and sparebit line
`pairs) to be significantly improved.
`Another object of the invention is to provide an array-divided
`semiconductor memory device including a redundancycircuit, which
`permits a defective normal line to be accurately repaired without erroneous
`operation.
`Yet another object of the present invention is to provide an array-
`divided semiconductor memory device including a power supply circuit
`without increasing accessing time and current consumption.
`A further object of the present invention is to provide an array-
`divided semiconductor memory device including a redundancy circuit which
`permits the spare line use efficiency to be improved and a power supply
`circuit which permits accessing time and power consumption to be reduced.
`Briefly stated, in a semiconductor memory device according to the
`present invention, spare lines are provided together as a single array, a
`plurality of memory mats are provided corresponding to the spare arrays,
`and a defective normal line in these plurality of memory mats is made
`replaceable with a spare line in a corresponding spare array.
`A powersupply circuit corresponding to a spare block is driven into a
`selected state when an active cycle is started.
`Furthermore, the selecting way of the power supply circuit is
`changed between a normal mode anda refresh mode.
`By providing a spare array exclusively for a spare line, the spare line
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`can be shared amonga plurality of memory blocks or sub arrays, and
`therefore the use efficiency of the spare lines maybe significantly improved
`over the case of providing a spare line for each memory block or sub array.
`In the array-divided arrangement, the selecting way of the power
`supply circuit is changed between a normal mode anda refresh mode, the
`numbersof bits in an address signal to be decoded can be different, and
`therefore the power supply circuit can be driven into a selected state at a
`high speed in the normal mode. Meanwhile, since a high speed responseis
`not required in the refresh mode, a large numberof address signal bits are
`decoded to select a minimum necessary power supply circuit and current
`consumption is reduced.
`If a spare element is included, in the normal mode power supply
`switch circuits for both a particular memoryblock including the spare
`element and an addressed memoryblock are driven into a selected state, so
`that the power supply circuits can be driven into a selected state without
`having to wait for a result of spare determination and that high speed
`accessing operations are implemented.
`In the refresh mode, the power supply circuit corresponding to a
`memory block including a memorycell to be selected is driven into a
`selected state according to the spare determination result, so that the
`numberof power supply circuits to be selected in the refresh mode can bea
`minimum necessary number, and the current consumption can be reduced.
`Thus, a semiconductor memory device with improveduseefficiency of spare
`elements without increase accessing time and current consumption can be
`implemented.
`The foregoing and otherobjects, features, aspects and advantages of
`the present invention will become more apparent from the following
`detailed description of the present invention when taken in conjunction
`with the accompanying drawings.
`BRIEF DESCRIPTION OF THE DRAWINGS
`Fig. 1 is a schematic diagram of a main part of a semiconductor
`memory device accordingto a first embodimentof the invention;
`Fig. 2A is a schematic diagram depicting how a defective column in a
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`memory array shown in Fig. 1 is repaired;
`Fig. 2B is a schematic diagram of a spare decoder used for repairing
`a defective column;
`Fig. 3A shows a modification of the spare decoder;
`Fig. 3B is a diagram depicting how a defective column is repaired by
`the spare decoder shownin Fig. 3A;
`Fig. 4 is a schematic diagram of an internal data readingportion in
`the array arrangement shownin Fig. 1;
`Fig. 5 is a schematic diagram of a main part of a semiconductor
`memory device according to a second embodimentof the invention;
`Fig. 6 is a schematic diagram depicting how a normal local data bus
`and a normal global data bus are connected and a spare local data bus and
`a spare global data bus are connected in the memory array shown in Fig. 5;
`Fig. 7 is a diagram showing the way to generate a spare local data
`busselecting signal;
`Fig. 8 is a schematic diagram of a columnselecting portion in a spare
`array in the memory array shown in Fig. 5;
`Fig. 9 is a schematic diagram of a main part of a semiconductor
`memory device according to a third embodimentof the invention;
`Fig. 10 is a diagram showing how a defective row in the memory
`array shownin Fig. 9 is repaired by wayof illustration;
`Fig. 11 is a schematic diagram of an array portion in a semiconductor
`memory device according to a fourth embodimentof the invention;
`Fig. 12 is a diagram showingthe effect of a memory block
`arrangement shown in Fig. 11;
`Fig. 13 is a schematic diagram of a bit line isolation instruction
`signal generation portion for solving problems associated with the
`arrangement shownin Fig. 12;
`Fig. 14 is a schematic diagram of a bit line isolation instruction
`signal generation portion in the memory block arrangement shown in Fig.
`11;
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`Fig. 15 is a schematic diagram depicting how a defective normal row
`is replaced with a spare row accordingto the fourth embodiment;
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`Fig. 16 is a diagram of a memorycell structure;
`Fig. 17 is a schematic diagram of an array portion in a semiconductor
`memory device accordingto a fifth embodimentof the invention;
`Fig. 18A showsthe correspondence between address signal bits and a
`selected memory portion in a normal operation mode in the array
`arrangement shownin Fig. 17;
`Fig. 18B shows the correspondence between address signal bits and a
`selected memory block in a test mode;
`Fig. 19 is a schematic diagram of an example of a control portion to
`select a memory block in the test mode shown in Fig. 18B;
`Fig. 20 is a schematic diagram of a modification of the fifth
`embodiment;
`Fig. 21A is a schematic diagram of a hierarchical power supply
`arrangement 1 according to a sixth embodimentof the invention;
`Fig. 21B is a diagram of a power switch circuit in a row-related
`peripheral circuit shown in Fig. 21A;
`Fig. 22 is a schematic diagram of a memory array and a power switch
`circuit according to the sixth embodiment;
`Fig. 23A is a diagram showingthe selected state of a power switch
`circuit in a normal modein hierarchical power supply arrangement 1
`according to the sixth embodiment;
`Fig. 23B is a waveform diagram representing the operation;
`Fig. 24 is a schematic diagram of the selected state of the
`hierarchical power supply arrangementin Fig. 22 in a refresh mode;
`Fig. 25 is a schematic diagram of a row-related control portion in the
`semiconductor memory device according to the sixth embodiment;
`Fig. 26 is a diagram of an example of a power supply block decoder
`shownin Fig. 21;
`Fig. 27 is a diagram of a power supply block decodecircuit for a
`power supply block selecting signal $B2;
`Fig. 28 is a schematic diagram depicting how addressbits are
`allocated in hierarchical power supply arrangement1 accordingto the sixth
`embodiment;
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`Fig. 29 is a diagram of a modification of the hierarchical power
`supply arrangement accordingto the sixth embodiment;
`Fig. 30 is a signal waveform diagram representing the operation of
`the hierarchical power supply arrangement shown in Fig. 29;
`Fig. 31 is a diagram of a repeating circuit in a row-related peripheral
`circuit in the modification of hierarchical power supply arrangement1;
`Figs. 32A and 32B are diagrams showingthe selected states of the
`powerswitch circuit in a normal mode and a refresh mode, respectively in a
`hierarchical power supply arrangement 2 accordingto the sixth
`embodimentof the invention;
`Fig. 33 is a schematic diagram of a power supply block decoder for
`Figs. 32A and 32B;
`Fig. 34 is a diagram of a power block decodecircuit for a particular
`power supply block selecting signal >B2;
`Fig. 35 is a schematic diagram of a modification of hierarchical power
`supply arrangement 2 according to the sixth embodiment;
`Fig. 36 is a schematic diagram of a control portion in a hierarchical
`powersupply arrangement3 accordingto the sixth embodiment;
`Fig. 37 is a signal waveform chart representing the operation of
`hierarchical power supply arrangement 3 according to the sixth
`embodiment;
`Fig. 38 is a diagram of an example of a power supply block decoder
`shownin Fig. 36;
`Fig. 39 is a diagram of an example of a register shownin Fig. 36;
`Fig. 40 is a schematic diagram of an example of a count up
`instruction signal generation portion shownin Fig. 36;
`Fig. 41 is a schematic diagram of hierarchical power supply
`arrangement 1 according to a seventh embodimentof the invention;
`Fig. 42 is a schematic diagram showingthe selected state of the
`powerswitch circuit in hierarchical power supply arrangement 1 according
`to the seventh embodiment in a normal mode;
`Fig. 43 is a signal waveform diagram representing the operation
`when the power switch circuit shown in Fig. 42 is selected;
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`Fig. 44 is a schematic diagram showingtheselected state of the
`power supply switch circuit and hierarchical power supply arrangement 1
`according to the seventh embodimentin a refresh mode;
`Fig. 45 is a signal waveform diagram representing the operation
`correspondingto the selected state of the memory switch circuit shown in
`Fig. 44;
`Fig. 46A is a d