Case 3:14-cv-00757-REP-DJN Document 81-3 Filed 04/10/15 Page 1 of 9 PageID# 10508
`Case 3:14-cv-00757-REP-DJN Document 81-3 Filed 04/10/15 Page 1 of 9 Page|D# 10508
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`EXHIBIT C
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`EXHIBIT C
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`Case 3:14-cv-00757-REP-DJN Document 81-Hlllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllltsog
`Case 3:14-cv-00757-REP-DJN Document 81-3 Filed 04/10/15 Page 2 of 9 PageID# 10509
`U5006287902Bl
`
`(12) United States Patent
`Kim
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 6,287,902 B1
`Sep. 11, 2001
`
`(54) METHODS OF FORMING ETCH
`INHIBITING STRUCTURES 0N FIELD
`ISOLATION REGIONS
`
`(75)
`
`Inventor: Do-hyung Kim, Seoul (KR)
`
`(73) Assignee: Samsung Electronics Co., Ltd. (KR)
`
`( ‘ ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 09/318,188
`
`(22)
`
`Filed:
`
`May 25, 1999
`
`Related U.S. Application Data
`
`(62) Division of application No. 081748.148, filed on Nov. 12,
`1996. now abandoned.
`
`(30)
`
`Foreign Application Priority Data
`
`Jun. 28, 1996
`
`(KR)
`
`........
`
`
`H01L21/338
`Int.CI.7
`(51)
`
`................
`438/183; 438/926
`(52) U.S. Cl.
`
`(58) Field of Search .
`438f183, 926,
`438-740, 233, 439
`
`96-25227
`
`............................ 437,1’195
`811995 Motonami
`5,441,916 *
`5.475.266 * 1211995 Rodder ......
`257.1750
`5,550,076 *
`811996 Chen .....
`438,1’253
`5.659.202 *
`8.-“1997 Ashida ..........
`2.577758
`5.698902 * 1211997 Uehara el al.
`257,773
`5,706,164
`1/1998 Jeng ..............
`438,239
`
`5,789,313 *
`811998 Lee ........
`438/599
`8/1999 Kim et al.
`............................ 2571395
`5,932,920 *
`
`
`
`FOREIGN PA'I'EN'I' DOCUMEN'IS
`
`2724165
`0523856A2
`53-108391
`59-76447 *
`59-76447
`60-66444
`62-177945
`4-63437 *
`8-335701 *
`9-64195 *
`
`12/1977 (DE).
`111993 (EP)
`.............................. 11011121911
`9/1978 (JP)
`...............................
`IIOlLr‘21/88
`5;"1984 (JP).
`8,4‘1984
`(JP)
`4;"1985 (JP)
`8,4‘1987
`(JP)
`2519992 (JP).
`2/1992 (JI’).
`3:"1997 (JP).
`
`[MIL/21,588
`...............................
`. HOlLr'211'76
`
`...................................... 257.1758
`
`* cited by examiner
`
`Primary Examiner—011k Chaudhuri
`Assistant [examiner—Phat X. (.‘a0
`
`(74) Attorney. Agent, or Firm—Myers Bigel Sibley &
`Sajovec
`
`(57)
`
`ABSTRACT
`
`A microelectronic structure includes a substrate having
`adjacent active and field regions. A field isolation layer
`covers the field region, and an etch inhibiting layer is
`provided on the field isolation layer adjacent
`the active
`region of the substrate. An insulating layer covers the
`substrate, the field isolation layer, and the etch inhibiting
`layer, and the insulating layer defines a contact hole therein
`exposing a portion of the active region adjacent the etch
`inhibiting layer. Related methods are also discussed.
`
`18 Claims, 2 Drawing Sheets
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`11/1992 Nagatomo ct al.
`5.164.806
`.................. 2577395
`12.11992 Yamamoto et al.
`5,174,858
`,. 156.1643
`12/1993 Ikcda
`5.273.936
`...... 4387453
`
`..
`3.51994 Nishigoori
`5293.503
`...... 1741250
`
`4/1994 Drummond .
`5.306.945
`...... 2577620
`
`5357.133 " 10.11994 Morita
`...... 257.1316
`
`5,365,111
`11/1994 Ramaswami ct al.
`2577768
`
`...... 438.1397
`5436.188
`71‘1995 Chen
`
`
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 81-3 Filed 04/10/15 Page 3 of 9 PageID# 10510
`Case 3:14-cv-00757-REP-DJN Document 81-3 Filed 04/10/15 Page 3 of 9 Page|D# 10510
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`US. Patent
`
`Sep. 11,2001
`
`Sheet 1 of 2
`
`US 6,287,902 B1
`
`1
`
`FIG.
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`(PRIOR ART)
`
`FIG. 2
`(PRIOR ART)
`
`15
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`FIG. 3
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`(PRIOR ART)
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`

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`Case 3:14-cv-00757-REP-DJN Document 81-3 Filed 04/10/15 Page 4 of 9 PageID# 10511
`Case 3:14-cv-00757-REP-DJN Document 81-3 Filed 04/10/15 Page 4 of 9 Page|D# 10511
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`US. Patent
`
`Sep. 11,2001
`
`Sheet 2 012
`
`US 6,287,902 B1
`
`FIG. 5
`
`42
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`40
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`

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`Case 3:14-cv-00757-REP-DJN Document 81-3 Filed 04/10/15 Page 5 of 9 PageID# 10512
`Case 3:14-cv-00757-REP-DJN Document 81-3 Filed 04/10/15 Page 5 of 9 Page|D# 10512
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`
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`US 6,287,902 B1
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`1
`METHODS OF FORMING ETCH
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`INHIBITING STRUCTURES ON FIELD
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`ISOLATION REGIONS
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`This application is a divisional application of US. patent
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`application Ser. No. 08/748,148 filed Nov. 12, 1996,
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`abandoned, and entitled ETCH INHIBITING STRUC-
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`TURES ON FIELD ISOLATION REGIONS AND
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`RELATED METHODS.
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`FIELD OF THE INVENTION
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`The present invention relates to microelectronic structures
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`and methods and more particularly to microelectronic struc-
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`tures and methods including isolation regions.
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`BACKGROUND OF THE INVENTION
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`As integrated circuit devices become more highly
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`integrated, the space available for individual devices formed
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`thereon is reduced. Accordingly, the sizes of patterns such as
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`gates, bit lines, and metal lines formed on integrated circuits
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`are generally reduced. Furthermore, space between these
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`patterns is also generally reduced.
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`In particular, integrated circuit memory devices include a
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`plurality of memory cells, and each memory cell is con-
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`nected to other cells by conductive (metal) lines. The cells
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`and conductive (metal) lines are connected to the substrate
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`or other conductive layers by contact holes or via holes. The
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`contact holes expose active regions of the substrate and the
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`via holes expose the surface of other conductive layers.
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`Patterned layers such as the gate electrodes should be
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`isolated from the holes, and these patterned layers are
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`generally arranged around the holes. Accordingly, the holes
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`must be accurately placed in order to maintain electrical
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`isolation with respect to the patterned layers such as the gate
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`electrodes.
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`As the space between these patterned layers is reduced,
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`however, the space available for forming the holes may also
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`be reduced. Furthermore, there may be physical limits to the
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`reductions which can be made to the size of the holes.
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`Accordingly, the increased integration reduces the margin
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`available in the placement of the holes. The margin available
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`for the placement of the holes is also influenced by the
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`process limitations of the steps for forming other adjacent
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`patterns. For example, when a LOCOS field oxide layer is
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`formed, the bird’s beak phenomenon may reduce the active
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`region. When a trench field oxide layer is formed, the inner
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`wall of the trench may encroach into the active region also
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`reducing the area available to the hole and further decreasing
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`the margin for the formation of the hole.
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`FIG. 1 is a cross-sectional view of an integrated circuit
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`device having a contact hole 16. The field oxide layer 12 is
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`formed on the semiconductor substrate 10, and the gate
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`electrode 14 is formed on an active region defined by the
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`field oxide layer 12. Spacers 15 are formed along the
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`sidewalls of the gate electrode 14. An insulating layer 20 is
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`then formed on the surface of the substrate including the gate
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`electrode 14 and the field oxide layer 12, and the contact
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`hole 16 is formed therein to expose a portion of the active
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`region of the substrate. The conductive layer 18 is formed on
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`the insulating layer 20 thus filling the contact hole 16. The
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`contact hole 16 is preferably formed over the active region
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`between the gate electrode 14 and the field oxide film 12 so
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`that neither the gate electrode 14 nor the field oxide film 12
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`is exposed.
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`While the contact hole 16 is shown centered between the
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`gate electrode 14 and the field oxide layer 12 in FIG. 1, it
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`10
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`may become more difficult to form the contact hole between
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`these structures as the device integration increases. As the
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`spaces become smaller, formation of the contact hole 16 may
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`be limited by the physical characteristics of light and the
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`ability to properly align the mask. Accordingly, the margin
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`for error during the formation of the contact hole is reduced.
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`As shown in FIGS. 2 and 3, misalignment of the contact hole
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`photomask may cause the contact hole to expose either the
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`gate electrode 14 or the field oxide layer 12.
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`As shown in FIG. 2,
`the misaligned contact hole 24
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`exposes a portion of the active region as well as a portion of
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`the field region. This misalignment may also result in the
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`formation of a well through the field oxide layer 12 thus
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`exposing a portion of a field region of the substrate when
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`etching the insulating film 20. In other words, a contact hole
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`24 may partially expose an active region of the substrate and
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`a well in the field region of the substrate. Accordingly, when
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`the contact hole 24 is filled with the conductive layer 18, the
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`conductive layer 18 is brought into contact with the well.
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`Leakage current may thus flow through the conductive layer
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`18 into the well area. The integrated circuit device may thus
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`overload leading to a delay in the operation of the device or
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`even a malfunction. If a capacitor is formed, the life of the
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`capacitor may also be reduced.
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`In FIG. 3, a misaligned contact hole exposes a portion of
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`the gate electrode 14. Accordingly, the conductive layer 18
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`filling the contact hole 25 may contact the gate electrode 14
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`thus short circuiting the device. The reliability of the inte-
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`grated circuit device may thus be reduced.
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`As discussed above, margins for forming contact holes are
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`reduced as device integration increases. For example, the
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`extension of a gate or a field region may reduce the area
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`available for a contact hole,
`thus reducing the process
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`margins. The reduction of process margins in turn causes a
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`reduction in the alignment margin for the photomask used to
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`form the contact hole. Accordingly, alignment of the pho-
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`tomask may become more difficult. The contact holes for
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`integrated circuit devices may thus be more difficult to form
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`and the alignment thereof may also be more difficult.
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`Accordingly, there continues to exist a need in the art for
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`improved contact hole structures and related methods.
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`SUMMARY OF THE INVENTION
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`It is therefore an object of the present invention to provide
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`improved contact hole structures and methods.
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`It is still another object of the present invention to provide
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`increased alignment tolerances for the formation of contact
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`holes.
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`These and other objects are provided according to the
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`present invention by structures and methods wherein an etch
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`inhibiting layer is provided on a field isolation layer adjacent
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`the active region of the substrate. This etch inhibiting layer
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`allows the misalignment of the contact hole without dam-
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`aging the field isolation, layer. Accordingly, the yield and
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`reliability of integrated circuit devices formed according to
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`the present invention can be increased at a given level of
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`integration.
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`In particular, a microelectronic structure includes a sub-
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`strate having active and field regions and a field isolation
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`layer which covers the field region, and first and second
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`patterned conductive layers. The first patterned conductive
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`layer is on the active region of the substrate spaced apart
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`from the field region, and the second patterned conductive
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`layer is on the field isolation layer adjacent the active region
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`of the substrate. The second patterned conductive layer thus
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`acts as the etch inhibiting layer protecting the field isolation
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`layer.
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`US 6,287,902 B1
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`3
`The structure can also include an insulating layer covering
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`the substrate,
`the field isolation layer, and the first and
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`second patterned conductive layers, and the insulating layer
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`includes a contact hole therein exposing a portion of the
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`active region between the first and second patterned con-
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`ductive layers. The contact hole can thus extend over the
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`field region without damaging the field isolation layer
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`because the first patterned conductive layer protects the field
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`isolation layer.
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`the first and second patterned conductive
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`layers may include insulating spacers along sidewalls
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`thereof, and the insulating layer can preferably be selectively
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`etched with respect to the insulating spacers. In particular,
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`the insulating layer can be formed from nitride.
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`The second patterned conductive layer is preferably elec-
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`trically isolated so that it serves no electrical function in the
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`completed device. This layer can thus act only as an etch
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`inhibiting layer
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`Furthermore, the field isolation layer can be formed from
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`oxide, and the field region can be a trench in the substrate
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`with the field isolation layer filling the trench.
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`According to another aspect of the invention, a method
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`includes the steps of defining adjacent active and field
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`regions on a substrate, and forming a field isolation layer on
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`the field region. An etch inhibiting layer is formed on the
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`field isolation layer adjacent the active region of the sub-
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`strate. An insulating layer is then formed on the substrate,
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`the field isolation layer, and the etch inhibiting layer, and a
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`contact hole is formed in the insulating layer. This contact
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`hole exposes a portion of the active region of the substrate
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`adjacent the etch inhibiting layer and the field isolation layer.
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`The etch inhibiting layer thus protects the field isolation
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`layer during the step of forming the contact hole.
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`The insulating layer can be nitride, and the step of
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`forming the insulating layer can be preceded by the step of
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`forming a patterned conductive layer on the active region of
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`the substrate. More particularly, the etch inhibiting layer and
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`the patterned conductive layer can each include a conductive
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`portion and insulating spacers along sidewalls thereof.
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`Preferably, the steps of forming the etch inhibiting layer and
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`forming the patterned conductive layer are performed simul-
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`taneously. In addition, the etch inhibiting layer is preferably
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`electrically isolated, and the field isolation layer can be
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`oxide.
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`The methods and structures of the present invention thus
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`provide protection for the field isolation layer during the
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`formation of a contact hole. Accordingly, a greater degree of
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`misalignment during the step of forming the contact hole can
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`be tolerated.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`FIG. 1 is a cross sectional view illustrating a contact hole
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`formed according to the prior art.
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`FIG. 2 is a cross sectional view illustrating a first mis-
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`aligned contact hole formed according to the prior art.
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`FIG. 3 is a cross sectional view illustrating a second
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`misaligned contact hole formed according to the prior art.
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`FIG. 4 is a cross sectional view illustrating a contact hole
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`formed according to the present invention.
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`FIGS. 5—7 are cross sectional views illustrating steps of a
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`method for forming a contact hole according to the present
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`invention.
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`FIG. 8 is a cross sectional view illustrating a misaligned
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`contact hole formed according to the present invention.
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`DETAILED DESCRIPTION
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`The present invention will now be described more fully
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`hereinafter with reference to the accompanying drawings, in
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`4
`which preferred embodiments of the invention are shown.
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`This invention may, however, be embodied in many different
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`forms and should not be construed as limited to the embodi-
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`ments set forth herein; rather, these embodiments are pro-
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`vided so that this disclosure will be thorough and complete,
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`and will fully convey the scope of the invention to those
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`skilled in the art. In the drawings, the thicknesses of layers
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`and regions are exaggerated for clarity. Like numbers refer
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`to like elements throughout.
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`A contact hole formed according to the present invention
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`is illustrated in FIG. 4. As shown, a field isolation layer 42
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`is formed on a field region of the substrate 40, and the field
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`isolation layer 42 can be an oxide layer. Portions of the
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`substrate 40 not covered by the field isolation layer 42 define
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`the active region where microelectronic devices will be
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`formed. As also shown, the field isolation layer 42 may be
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`formed in a trench. Alternately, the field oxide layer may be
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`formed by a LOCOS-type method.
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`First and second patterned conductive layers 44 and 44a
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`are formed respectively on the active region of the substrate
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`and on a field isolation layer 42. Insulating spacers 46 and
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`46a are formed along the sidewalls of the first and second
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`patterned conductive layers 44 and 44a. In particular, the
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`first patterned conductive layer 44 can be a gate electrode of
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`a transistor. The second patterned conductive layer 44a
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`preferably has the same structure as the first patterned
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`conductive layer 44 with the exception that
`the second
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`patterned conductive layer is electrically isolated. In other
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`words, the second patterned conductive layer 44a serves as
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`a dummy pattern.
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`An insulating layer 48 is then formed over the surface of
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`the semiconductor substrate including the first and second
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`patterned conductive layers 44 and 44a. Acontact hole 50 is
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`then formed in the insulating layer 48 thereby exposing a
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`portion of the active region of the substrate. More
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`particularly, the contact hole 50 may expose a doped layer
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`43 in the active region of the substrate. The insulating layer
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`48 is preferably formed from a material such as nitride
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`which is more susceptible to etching than the material used
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`to form the insulating spacers 46 and 46a.
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`Using the structure discussed above, some misalignment
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`of the contact hole 50 can be tolerated. In particular, if the
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`contact hole extends beyond the active region of the sub-
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`strate encroaching into the field region, a second patterned
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`conductive layer 44a reduces the likelihood that a well will
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`be formed in the field isolation layer 42. In particular, the
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`second patterned conductive layer 44a can act as an etch
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`stop if needed when etching the insulating layer 48. In other
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`words, contact hole 50 can now extend over the field region
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`without damaging the field isolation layer 42.
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`When comparing the prior art structure of FIG. 1 with that
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`of FIG. 4, the area over which the contact hole 50 can be
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`formed using the structure of the present invention is larger
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`than the area available using the structure of the prior art. In
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`particular,
`the contact hole of FIG. 1 must be formed
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`between the gate electrode 14 and the field oxide layer 12.
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`When using the structure of the present invention, however,
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`the area over which the contact hole 50 can be formed
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`extends over a portion of the field region covered by the
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`second patterned conductive layer 44a.
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`A method for forming an integrated circuit device accord-
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`ing to the present invention will be discussed with reference
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`to FIGS. 5—7. Active and isolation regions of the substrate 40
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`are defined as shown in FIG. 5. In particular, field isolation
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`layer 42 is formed on the isolation region of the substrate,
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`and the active region of the substrate is left exposed. This
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`10
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`65
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`

`Case 3:14-cv-00757-REP-DJN Document 81-3 Filed 04/10/15 Page 7 of 9 PageID# 10514
`Case 3:14-cv-00757-REP-DJN Document 81-3 Filed 04/10/15 Page 7 of 9 Page|D# 10514
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`US 6,287,902 B1
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`5
`field isolation layer can be formed from a layer of oxide.
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`Electronic devices are typically not formed in the isolation
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`region of the substrate. As shown, a trench can be formed on
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`the isolation region of the substrate and this trench can be
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`filled with the field isolation layer. Alternately, a field
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`isolation layer can be formed by other methods such as the
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`LOCOS method. Electronic devices can be formed in the
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`active region of the substrate which is left exposed.
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`First and second patterned conductive layers 44 and 44a
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`can then be formed as shown in FIG. 6. As shown, a first
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`patterned conductive layer 44 is formed on an active region
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`of the substrate 40, and a second patterned conductive layer
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`44a is formed on the field isolation layer 42. In particular, an
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`oxide layer and a conductive layer can be sequentially
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`formed on the surface of the substrate 40 including the field
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`isolation layer 42. A photoresist pattern can then be formed
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`on the conductive layer to define the patterned conductive
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`layers. The exposed portions of the conductive layer and the
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`oxide layer can then be isotropically etched to expose
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`portions of the surface of the substrate 40 and the field
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`isolation layer 42. Accordingly, the first and second pat-
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`terned conductive layers 44 and 44a are respectively formed
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`on the active and field regions of the substrate. The patterned
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`conductive layers can be defined to include an oxide layer
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`adjacent the substrate.
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`Anitride layer can then be formed over the surface of the
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`patterned conductive layers, the substrate 40, and the field
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`isolation layer 42. This nitride film can be isotropically
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`etched to form the nitride spacers 46 and 46a along the
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`sidewalls of the first and second patterned conductive layers
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`44 and 44a. As will be discussed below, a contact hole 50
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`can thus be self-aligned using the spacers 46 and 46a.
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`Unlike methods of the prior art,
`the structure formed
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`according to the present
`invention includes the second
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`patterned conductive layer 44a on the field isolation layer
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`42. The first patterned conductive layer 44 may be used as
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`a gate electrode, while the second patterned conductive layer
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`44a can be a dummy pattern serving no electrical function.
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`Instead, the second patterned conductive layer 44a is used to
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`increase a process margin for the formation of a contact hole
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`by allowing the formation of a self-aligned contact hole as
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`discussed below. Accordingly, the second patterned conduc-
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`tive layer 44a is preferably electrically isolated over the field
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`region.
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`The second patterned conductive layer 44a is formed on
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`a portion of the field isolation layer 42 where a misaligned
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`contact hole would most likely encroach. Accordingly, the
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`second patterned conductive layer 44a can be used to reduce
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`design rule constraints related to the formation of the contact
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`hole. The size of the second patterned conductive layer 44a
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`is determined in part by the size of the contact hole to be
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`formed and the likely position of the contact hole in the
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`event of misalignment.
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`A contact hole 50 is formed as shown in FIG. 7. A
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`conductive layer 43 can be formed in the active region of the
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`substrate by implanting a dopant into the substrate 40. This
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`implant can be masked in part by the patterned conductive
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`layer 44, and the implanting step may be an ion implanting
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`step. The insulating layer 48 can then be formed with a
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`thickness sufficient to cover the first and second patterned
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`conductive layers 44 and 44a. The contact hole 50 is then
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`formed in the insulating layer 48 to expose a portion of the
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`active region between the first and second patterned con-
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`ductive layers 44 and 44a. The contact hole 50 preferably
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`exposes the doped layer 43 without exposing either of the
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`patterned conductive layers.
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`6
`The contact hole 50, however, may extend into the field
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`region or into the first patterned conductive layer 44 accord-
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`ing to the alignment of the mask used to form the contact
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`hole. As shown in FIG. 8, a self-aligned contact hole 50 may
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`extend over the field region. Because the second patterned
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`conductive layer 44a serves as an etch inhibiting film, the
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`contact hole 50 is self-aligned allowing it to extend over the
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`field region. Stated in other words,
`the second patterned
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`conductive layer 44a and associated spacers 46a protect the
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`field isolation layer 42 from the etch used to form the contact
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`hole 50. Accordingly, even with a misalignment of the
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`contact hole mask over the field region and over etching to
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`insure exposure of the active region, the field isolation layer
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`42 is not damaged. The masking and etching margins can
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`thus be increased with respect to the prior art. In the event
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`the contact hole mask is aligned to the first patterned
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`conductive layer 44, a self-aligned contact hole can be
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`formed using the spacers 46.
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`In the integrated circuit devices of the present invention,
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`patterned conductive layers are simultaneously formed on
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`both the active and field regions. The patterned conductive
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`layer on the field region, however, can be electrically
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`isolated thus serving no electrical function in the completed
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`integrated circuit device. A self-aligned contact hole can
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`thus be formed over the active region of the substrate using
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`the patterned conductive layer formed in the field region to
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`protect the field isolation layer during the etch used to form
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`the contact hole. Because the patterned conductive layer
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`over the field region protects the field isolation layer, the
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`area over which the contact hole can be formed is increased
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`with respect to the prior art. Accordingly, a greater contact
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`margin is allowed when forming the contact hole.
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`Furthermore, the etching margins can be increased without
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`increasing the risk of damaging the field isolation layer.
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`Reliability of the integrated circuit device can thus be
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`increased because leakage current generated by damage to
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`the field isolation layer can be reduced. Furthermore, no
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`extra processing steps are required because the second
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`patterned conductive layer and the first patterned conductive
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`layer (which can be a transistor gate) can be formed simul-
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`taneously.
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`In the drawings and specification, there have been dis-
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`closed typical preferred embodiments of the invention and,
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`although specific terms are employed, they are used in a
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`generic and descriptive sense only and not for purposes of
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`limitation, the scope of the invention being set forth in the
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`following claims.
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`That which is claimed is:
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`1. A method for forming a contact hole for a microelec-
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`tronic structure, said method comprising the steps of:
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`defining adjacent active and field regions on a substrate,
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`and circuits thereon;
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`forming a field isolation layer on said field region;
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`forming a first patterned conductive layer on said active
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`region of said substrate spaced apart from