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`EXHIBIT C
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`EXHIBIT C
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`(12) United States Patent
`Raj appa et al.
`
`US006378082B1
`(10) Patent No.:
`US 6,378,082 B1
`(45) Date of Patent:
`Apr. 23, 2002
`
`(54) GENERATING STROBE SIGNALS AT
`DIFFERENT VOLTAGE LEVEL MODES FOR
`RECEIVING DATA AT GRAPHICS
`INTERFACE PORT
`
`(75) Inventors: Srinivasan T. Rajappa, Folsom;
`Robert J. Johnston, Fair Oaks, both of
`CA (Us)
`
`(73) Assignee: Intel Corporation, Santa Clara, CA
`(Us)
`
`( * ) Notice:
`
`subject_to any disclaimeri the term of this
`patent is extended or adJusted under 35
`U S C 154(k)) by 0 days
`
`(21) App1_N0_; 09/345,711
`
`Jun.30, 1999
`
`(22) Filed:
`(51) Int. Cl?
`(52) US. Cl.
`(58) Field of Search
`
`713/501; 713/400; 713/600
`713/322, 501,
`713/600, 400
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`6,092,212 A * 7/2000 Muljono et al.
`
`713/600
`
`*
`
`-
`-
`cited by examiner
`
`.
`.
`.
`Prlmary Ex‘lml”e’—Kenneth 5' Km
`(74) Attorney, Agent, or Firm—Blakely, Sokoloff, Taylor &
`Zafrnan LLP
`
`(57)
`
`ABSTRACT
`
`The present invention is a method and apparatus to generate
`_
`_
`_
`?rst and second strobe signals to receive data on an interface
`port of a processor operating in ?rst and second modes at
`?rst and second voltage levels, respectively. The second
`voltage level is higher than the ?rst voltage level. A selector
`provides ?rst and second selected signals from a plurality of
`signals Which corresponds to the ?rst and second rnodes.
`The selector operates at the second voltage level. A signal
`generator is coupled to the selector to generate the ?rst and
`second strobe signals from the ?rst and second selected
`signals.
`
`5,951,688 A * 9/1999 Moyer et a1.
`
`713/320
`
`30 Claims’ 4 Drawing Sheets
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`SELECTOR
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`201
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`2--
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`ADSTB
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`ADSTB#
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`MODESEL
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`SIGNAL GENERATOR
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`202
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`230
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`+
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`150
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`RCVD_STB
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`240
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`+
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`RCVD_STB#
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`

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`U.S. Patent
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`Apr. 23, 2002
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`US 6,378,082 B1
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`U.S. Patent
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`Apr. 23, 2002
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`Sheet 2 0f 4
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`US 6,378,082 B1
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`U.S. Patent
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`Apr. 23, 2002
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`US 6,378,082 B1
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`U.S. Patent
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`Apr. 23, 2002
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`US 6,378,082 B1
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`US 6,378,082 B1
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`1
`GENERATING STROBE SIGNALS AT
`DIFFERENT VOLTAGE LEVEL MODES FOR
`RECEIVING DATA AT GRAPHICS
`INTERFACE PORT
`
`2
`interface port of a processor operating in ?rst and second
`modes at ?rst and second voltage levels, respectively. The
`second voltage level is higher than the ?rst voltage level.
`Brie?y, the apparatus comprises a selector provides ?rst and
`second selected signals from a plurality of signals Which
`corresponds to the ?rst and second modes. The selector
`operates at the second voltage level. The apparatus further
`comprises a signal generator that is coupled to the selector
`to generate the ?rst and second strobe signals from the ?rst
`and second selected signals.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The features and advantages of the present invention Will
`become apparent from the folloWing detailed description of
`the present invention in Which:
`FIG. 1 is a diagram illustrating a system in Which one
`embodiment of the invention can be practiced.
`FIG. 2 is a diagram illustrating a strobe signaling interface
`according to one embodiment of the invention.
`FIG. 3A is a timing diagram illustrating a 4X transfer
`mode signaling according to one embodiment of the inven
`tion.
`FIG. 3B is a timing diagram illustrating a 2X transfer
`mode signaling according to one embodiment of the inven
`tion.
`
`DESCRIPTION
`
`The present invention is a method and apparatus for
`generating multi-mode strobe signals in a processor. The
`input signals operate in tWo modes having tWo different
`voltage requirements. The technique uses select elements
`that can sustain both voltage requirements. Differential
`ampli?ers are used to generate differential receiver strobe
`signals to comply With the processor speci?cations.
`In the folloWing description, for purposes of explanation,
`numerous details are set forth in order to provide a thorough
`understanding of the present invention. HoWever, it Will be
`apparent to one skilled in the art that these speci?c details
`are not required in order to practice the present invention. In
`other instances, Well knoWn electrical structures and circuits
`are shoWn in block diagram form in order not to obscure the
`present invention.
`FIG. 1 is a diagram illustrating a computer system 100 in
`Which one embodiment of the invention can be practiced.
`The computer system 100 includes N processors 1051
`through 105N, a host bus 110, a host bridge chipset 120, a
`system memory 130, a graphics processor 140, a digital
`video disk (DVD) device 122, a video device 142, a decoder
`124, a display monitor 144, a television
`148, an
`encoder 146, a graphics local memory 150, a primary PCI
`bus #0 155, a PCI bus #1 145, an accelerated graphics port
`(AGP) 141, K PCI slots 1601 to 160K, a netWork interface
`162, a media interface 164, a PCI-to-ISA bridge 170, mass
`storage devices 172, Input/Output (I/O) ports 174, an ISA
`bus 180, and ISA slots 1851 to 185M.
`Each of the processors 1051 to 105N represents a central
`processing unit of any type of architecture, such as complex
`instruction set computers (CISC), reduced instruction set
`computers (RISC), very long instruction Word (VLIW), or
`hybrid architecture. The invention could be implemented in
`a multi-processor or single processor computer system.
`The host bridge chipset 120 includes a number of inter
`face circuits to alloW the host processors 1051 to 105N access
`to the system memory 130, the graphics processor 140, and
`the primary PCI bus #0 155. The system memory 130
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`BACKGROUND
`1. Field of the Invention
`This invention relates to signaling. In particular, the
`invention relates to strobe signaling.
`2. Description of Related Art
`Advanced processors usually are developed as an
`improvement from previous generations. To maintain doWn
`Ward compatibility, neWer processors tend to maintain the
`same features in the older models While incorporating addi
`tional features. HoWever, When there is a signi?cant
`upgrade, maintaining compatibility With existing supporting
`circuits and/or speci?cations is a dif?cult task.
`For example, the Accelerated Graphics Port (AGP) is an
`advanced graphics interface that alloWs high performance
`graphics to be generated in a personal computer (PC)
`platform. The AGP physical interface is optimiZed for a
`point to point topology using either 1.5 volt or 3.3 volt
`signaling. The baseline performance level utiliZes a 66 MHZ
`clock to provide a peak bandWidth of 266 megabytes per
`second (MB/s). The AGP includes tWo options for higher
`performance levels.
`The ?rst option provides a peak bandWidth of 533 MB/s.
`This mode uses a double-clocked data technique to transfer
`tWice the data per each AGP clock. This AGP mode, referred
`to as the 2X transfer mode, or 2X mode, requires additional
`interface timing strobes and different signal timings from the
`baseline 1X mode.
`The second option provides a peak bandWidth of up to
`1066 MB/s. This mode uses a quad-clocked data transfer
`technique to transfer four times the data per each 66 MHZ
`clock. This mode, referred to as 4X transfer mode, requires
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`differential interface timing strobes and different signal
`timings from the 66 MHZ baseline and the 2X mode AGP
`requirements.
`The 1X and 2X modes can operate at both the 1.5 V and
`3.3 V signaling level folloWing the AGP 1.0 speci?cations.
`The 4X mode, hoWever, is restricted to the 1.5 V signaling
`level, folloWing the Accelerated Graphics Port Interface
`Speci?cation Revision 2.0 published by Intel Corporation
`dated May 4, 1998 (“AGP 2.0 Speci?cation”) because of
`signal integrity limitations. Accelerated Graphics Port Inter
`face Speci?cation Revision 10 published by Intel Corpora
`tion dated Jul. 31, 1996 (“AGP 1.0 Speci?cation”) the strobe
`input stage is sensed differentially With respect to the analog
`input reference bias Which is nominally set at 0.4. Vddq for
`a 3.3 V AGP environment. The AGP 2.0 speci?cation
`introduces the strobe complement signal and hence requires
`the strobe input stage to be fully differential sensing as
`opposed to With respect to a reference.
`It is desirable to have a physical interface that can
`accommodate both the 2X and 4X transfer modes. Tradi
`tional methods use multiple differential ampli?ers With all
`possible input combinations folloWed by tristable output
`stages. This approach is costly from a design perspective
`because it uses expensive die real estate.
`Therefore there is a need in the technology to provide a
`simple and ef?cient method to implement a multi-mode
`strobe signaling to accommodate multiple operational
`modes of advanced processors.
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`SUMMARY
`The present invention relates to a method and apparatus to
`generate ?rst and second strobe signals to receive data on an
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`represents one or more mechanisms for storing information.
`For example, the system memory 130 may include non
`volatile or volatile memories. Examples of these memories
`include ?ash memory, read only memory (ROM), or random
`access memory
`The system memory 130 is loaded
`With an operating system (OS) 131, and other programs and
`data 138. Of course, the system memory 130 preferably
`contains additional softWare (not shoWn), Which is not
`necessary to understanding the invention.
`The PCI slots 1601 to 160K provide interfaces to PCI
`devices. Examples of PCI devices include the netWork
`interface 162 and the media interface 164. The netWork
`interface 162 connects to communication channel such as
`the Internet. The Internet provides access to on-line service
`providers, Web broWsers, and other netWork channels. The
`media interface 164 provides access to audio and video
`devices.
`The graphics processor 140 is a high performance graph
`ics controller that perform graphics functions such as 3-D
`rendering operations, progressive meshes, painting,
`draWing, etc. The graphics processor 140 is coupled to the
`host bridge 120 via the AGP 141 and the PCI bus #1 145. In
`one embodiment, the AGP 141 is developed by Intel Cor
`poration of Santa Clara, Calif. The graphics processor
`includes a strobe signaling interface 152 that generate the
`strobe signals to capture data on the AGP 141. The graphics
`processor 140 has access to its oWn graphics local memory
`150. The graphic local memory 150 may contain graphics
`programs and data for displaying. The DVD device 122
`represents any digital video device or instrument. The video
`device 142 provides video input such as DVD, camera, or
`video cassette recorder (VCR) to the graphics processor 140.
`The decoder 124 decodes the video signals from the video
`device 142 to the graphics processor 140. The display
`monitor 144 displays the graphics as generated by the
`graphics processor 140. The encoder 146 receives the graph
`ics data from the graphics controller 140 and encodes into an
`analog signal to be compatible for TV display on the TV set
`148.
`The PCI-to-ISAbridge 170 provides access to the ISA bus
`180, mass storage devices 172, and I/O ports 174. The mass
`storage devices 172 include CD ROM, ?oppy diskettes, and
`hard drives. The ISAbus 180 has a number of ISA slots 1851
`to 185M to interface to ISA devices. Examples of ISA
`devices include data entry devices (e.g., keyboard, mouse),
`printers, etc.
`The AGP 141 is a physical interface port betWeen the host
`bridge chipset 120 and the graphics processor 140. Address
`and data information is transferred over the AGP 141
`synchroniZed by clock and strobe signals. Supporting
`devices such as buffers, drivers, clock circuits, and strobe
`logic circuitsW are designed to accommodate the tWo oper
`ating modes on the AGP 141, namely, the 4X and 2X transfer
`modes. The strobe signaling interface 152 provides an
`interface to accommodate both of these transfer modes.
`FIG. 2 is a diagram illustrating a strobe signaling interface
`152 according to one embodiment of the invention. The
`strobe signaling interface 152 includes a selector 201 and a
`signal generator 202.
`The selector 201 receives the address strobe high and loW
`(ADSTB and ADSTB#) signals, an AGP reference
`(AGPREF) signal, and a mode select (MODESEL) signal.
`The selector 201 generates selected signals to the signal
`generator 202. The signal generator 202 generates the strobe
`signals to receive the data on the physical interface port AGP
`of the graphics processor. The strobe signals include a
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`complementary receiver strobe high (RCVDiSTB) signal
`and a receiver strobe loW (RCVDiSTB#) signal. The
`RCVDiSTB and RCVDiSTB# signals are used to latch or
`trigger the latching of data transferred on the AGP 141 in
`FIG. 1.
`The selector 201 includes multiplexers 210 and 220. The
`multiplexers 210 and 220 have similar tolerant characteris
`tics and propagation delays. The tolerant characteristics
`include the ability to provide an output sWing of either
`betWeen 0 to 3.3 V or 0 to 1.5 V to comply With the AGP 1.0
`and 2.0 speci?cations, respectively. The multiplexers 210
`and 220 operate at the higher voltage level, namely, the 0 to
`3.3 V. Since they operate at the higher voltage level, they can
`provide signaling for both the loW and high voltage levels of
`1.5 V and 3.3 V, respectively. The multiplexers 210 and 220
`may be implemented using native devices if the process does
`support the 3.3 V requirement. If the process does not
`support the 3.3 V, the multiplexers 210 and 220 can be
`implemented in tWo Ways. In the ?rst method, the external
`voltage sWing is conditioned to a voltage that is more
`tolerable (e.g., 3.3 V) using an input conditioner With clamp
`and then multiplexing the proper reference voltage
`AGPREF. In the second method, select elements are imple
`mented using multiplexing transistors With thicker gate
`oxide thickness that could sustain the gate-oxide stress
`caused by the high voltage. The second method is simple and
`straightforWard but it may require a change in the fabrication
`process.
`The multiplexer 210 receives the address strobe high
`(ADSTB) signal and generates the ?rst selected signal to the
`differential ampli?ers 230 and 240. The multiplexer 210 can
`be con?gured so that the ADSTB signal is alWays selected,
`in Which case the multiplexer 210 acts like a delay element
`to provide a propagation delay comparable With that of the
`multiplexer 220. In one embodiment, the multiplexer 210 is
`replaced by a buffer having the same tolerant characteristics
`and propagation delay as the multiplexer 220. The ADSTB
`signal is common to both of the tWo operating modes.
`The multiplexer 220 receives the ?rst and second mode
`signals: the AGP reference (AGPREF) signal and the
`address strobe loW (ADSTB#) signal. The AGPREF signal
`represents a constant reference voltage Which is set approxi
`mately to 0.4 Vddg (for 2X transfer mode) or 0.5 Vddg (for
`4X transfer mode). The ADSTB and the ADSTB# are
`complementary signals. The multiplexer 220 receives the
`mode select (MODESEL) signal as its select signal and
`generates a second selected signal to the signal generator
`202. The MODESEL signal is used to select betWeen the 2X
`mode and the 4X mode. When MODESEL is loW, the 4X
`mode is selected and the AGPREF signal is generated at the
`output of the multiplexer 220. When MODESEL is high, the
`2X mode is selected and the ADSTB# signal is generated at
`the output of the multiplexer 220. The second selected signal
`is either the AGPREF or the ADSTB# signals depending on
`the MODESEL signal.
`The signal generator 202 includes differential ampli?ers
`230 and 240, and buffers 250 and 260. The ?rst differential
`ampli?er 230 provides a ?rst differential signal correspond
`ing to the receiver strobe signal high (RCVDiSTB). The
`positive and negative inputs of the differential ampli?er 230
`are connected to the ?rst and second selected signals from
`the multiplexers 210 and 220, respectively. When the 4X
`mode is selected, the ?rst differential ampli?er 230 generates
`the ?rst differential signal Which is the difference betWeen
`the ADSTB and the ADSTB# signals according to the AGP
`2.0 speci?cation. When the 2X mode is selected, the ?rst
`differential ampli?er 230 generates the ?rst differential
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`signal Which is the difference between the ADSTB and the
`AGPREF according to the AGP 1.0 speci?cation.
`The second differential ampli?er 240 provides the second
`differential signal corresponding to the receiver strobe signal
`loW (RCVDiSTB#). The positive and negative inputs of the
`second differential ampli?er 240 are connected to the second
`and ?rst selected signals from the multiplexers 220 and 210,
`respectively. When the 4X mode is selected, the second
`differential ampli?er 240 generates the second differential
`signal Which is the difference betWeen the ADSTB# and the
`ADSTB signals according to the AGP 2.0 speci?cation.
`When the 2X mode is selected, the second differential
`ampli?er 240 generates the second differential signal Which
`is the difference betWeen the AGPREF and the ADSTB
`according to the AGP 1.0 speci?cation.
`The ?rst and second buffers 250 and 260 are used to buffer
`the outputs of the differential ampli?ers 230 and 240 to
`generate the receiver strobe RCVDiSTB and RCVDi
`STB# signals, respectively.
`FIG. 3A is a timing diagram illustrating a 4X transfer
`mode signaling according to one embodiment of the inven
`tion.
`The MODESEL signal is loW to select the 4X transfer
`mode. The ADSTB and ADSTB# signals are complemen
`tary. The delay paths from the ADSTB and ADSTB# to the
`RCVDiSTB and RCVDiSTB# signals are approximately
`equal because the paths go through devices With similar
`process and construction, e.g., the multiplexers 210 and 220,
`the differential ampli?ers 230 and 240, and the buffers 250
`and 260. Therefore, both the RCVDiSTB and RCVDi
`STB# signals are subject the same propagation delay, shoWn
`as t4pd in the timing diagram. The complementary transi
`tions of the Waveforms RCVDiSTB and RCVDiSTB# are
`synchroniZed due to the complementary transitions of the
`ADSTB and ADSTB# signals. As an example, the sample
`points A and A‘ on the ADSTB and ADSTB# signals,
`respectively, correspond to the sample points B and B‘ on the
`RCVDiSTB and RCVDiSTB# signals, respectively.
`FIG. 3B is a timing diagram illustrating a 2X transfer
`mode signaling according to one embodiment of the inven
`tion.
`The MODESEL signal is high to select the 2X transfer
`mode. In this mode, the RCVDiSTB and RCVDiSTB#
`signals are generated as the differential outputs betWeen the
`ADSTB signal and the AGPREF signal. Again the delay
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`paths from the ADSTB and the AGPREF to the RCVDi
`STB and RCVDiSTB# signals are approximately equal
`because the paths go through devices With similar process
`and construction, e.g., the multiplexers 210 and 220, the
`differential ampli?ers 230 and 240, and the buffers 250 and
`260. Therefore, the resulting RCVDiSTB and RCVDi
`STB# signals are complementary Where the complementary
`transitions are synchroniZed. In addition, since the reference
`AGPREF signal is at constant level, the sWitching Wave
`forms are due mainly to the sWitching Waveform of the
`ADSTB signal. As an example, the sample point A on the
`ADTSB signal corresponds to the sample points B and B‘ on
`the RCVDiSTB and RCVDiSTB# signals after a propa
`gation delay of t2pd.
`Thus, the present invention is a technique to generate
`complementary receiver strobe signals for both the 4X and
`2X transfer modes of the AGP physical interface. The
`technique uses a high-voltage tolerant multiplexer to handle
`an output sWing of either betWeen 0 to 3.3V or 0 to 1.5V that
`are compliant to the 2X or 4X transfer modes.
`While this invention has been described With reference to
`illustrative embodiments, this description is not intended to
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`be construed in a limiting sense. Various modi?cations of the
`illustrative embodiments, as Well as other embodiments of
`the invention, Which are apparent to persons skilled in the art
`to Which the invention pertains are deemed to lie Within the
`spirit and scope of the invention.
`What is claimed is:
`1. A method comprising:
`selecting ?rst and second selected signals from a plurality
`of signals by a selector, the plurality of signals being
`provided by a processor operating in ?rst and second
`modes at ?rst and second voltage levels, respectively,
`the second voltage level being higher than the ?rst
`voltage level, the selector operating at the second
`voltage level; and
`generating ?rst and second strobe signals from the ?rst
`and second selected signals by a signal generator the
`?rst and second strobe signals being complementary to
`receive data on an interface port of the processor.
`2. The method of claim 1 Wherein selecting comprises:
`receiving a common signal from the plurality of signals to
`provide the ?rst selected signal by a ?rst selecting
`element in the selector; and
`receiving ?rst and second mode signals from the plurality
`of signals to provide the second selected signal in
`response to a mode select signal by a second selecting
`element in the selector.
`3. The method of claim 2 Wherein receiving the common
`signal comprises receiving the common signal complemen
`tary to the second mode signal.
`4. The method of claim 3 Wherein receiving the ?rst and
`second mode signals comprise receiving the ?rst mode
`signal, the ?rst mode signal being a reference signal having
`a voltage level proportional to one of the ?rst and second
`voltage levels.
`5. The method of claim 2 Wherein generating comprises:
`generating a ?rst differential signal corresponding to the
`?rst strobe signal by a ?rst ampli?er; and
`generating a second differential signal corresponding to
`the second strobe signal by a second ampli?er.
`6. The method of claim 5 Wherein generating further
`comprises:
`buffering the ?rst differential signal to generate the ?rst
`strobe signal; and
`buffering the second differential signal to generate the
`second strobe signal.
`7. The method of claim 2 Wherein the ?rst and second
`selecting elements have approximately equal propagation
`delays.
`8. The method of claim 2 Wherein the ?rst and second
`selecting elements are transistors having a gate-oxide thick
`ness comparable With the second voltage level.
`9. The method of claim 6 Wherein the interface port is an
`Accelerated Graphics Port (AGP).
`10. The method of claim 9 Wherein the ?rst and second
`modes are 4X and 2X transfer modes, respectively.
`11. An apparatus comprising:
`a selector to provide ?rst and second selected signals from
`a plurality of signals, the plurality of signals being
`provided by a processor operating in ?rst and second
`modes at ?rst and second voltage levels, respectively,
`the second voltage level being higher than the ?rst
`voltage level the selector operating at the second volt
`age level; and
`a signal generator coupled to the selector to generate ?rst
`and second strobe signals from the ?rst and second
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`selected signals the ?rst and second strobe signals
`being complementary to receive data on an interface
`port of the processor.
`12. The apparatus of claim 11 Wherein the selector com
`prises:
`a ?rst selecting element to receive a common signal from
`the plurality of signals, the ?rst selecting element
`providing the ?rst selected signal; and
`a second selecting element to receive ?rst and second
`mode signals from the plurality of signals, the second
`selecting element providing the second selected signal
`in response to a mode select signal.
`13. The apparatus of claim 12 Wherein the common signal
`and the second mode signals are complementary.
`14. The apparatus of claim 13 Wherein the ?rst mode
`signal is a reference signal having a voltage level propor
`tional to one of the ?rst and second voltage levels.
`15. The apparatus of claim 12 Wherein the signal genera
`tor comprises:
`a ?rst ampli?er having ?rst positive and negative inputs
`coupled to the selector to receive the ?rst selected
`signal at the ?rst positive input and the second selected
`signal at the ?rst negative input, the ?rst ampli?er
`generating a ?rst differential signal corresponding to
`the ?rst strobe signal; and
`a second ampli?er having second positive and negative
`inputs coupled to the selector to receive the ?rst
`selected signal at the second negative input and the
`second selected signal at a second positive input, the
`second ampli?er generating a second differential signal
`corresponding to the second strobe signal.
`16. The apparatus of claim 15 Wherein the signal genera
`tor further comprises:
`a ?rst buffer coupled to the ?rst ampli?er to generate the
`?rst strobe signal from the ?rst differential signal; and
`a second buffer coupled to the second ampli?er to gen
`erate the second strobe signal from the second differ
`ential signal.
`17. The apparatus of claim 12 Wherein the ?rst and second
`selecting elements have approximately equal propagation
`delays.
`18. The apparatus of claim 12 Wherein the ?rst and second
`selecting elements are transistors having a gate-oxide thick
`ness comparable With the second voltage level.
`19. The apparatus of claim 16 Wherein the interface port
`is an Accelerated Graphics Port (AGP).
`20. The apparatus of claim 19 Wherein the ?rst and second
`modes are 4X and 2X transfer modes, respectively.
`21. A system comprising:
`a processor;
`an interface port coupled to the processor to provide
`interface signals for transferring data; and
`an interface circuit coupled to the interface port compris
`ing:
`a selector to provide ?rst and second selected signals
`from a plurality of signals, the plurality of signals
`
`10
`
`25
`
`35
`
`45
`
`55
`
`8
`being provided by the processor operating in ?rst and
`second modes at ?rst and second voltage levels,
`respectively, the second voltage level being higher
`than the ?rst voltage level the selector operating at
`the second voltage level, and
`a signal generator coupled to the selector to generate
`?rst and second strobe signals from the ?rst and
`second selected signals the ?rst and second strobe
`signals being complementary to receive the data on
`the interface port of the processor.
`22. The system of claim 21 Wherein the selector com
`prises:
`a ?rst selecting element to receive a common signal from
`the plurality of signals, the ?rst selecting element
`providing the ?rst selected signal; and
`a second selecting element to receive ?rst and second
`mode signals from the plurality of signals, the second
`selecting element providing the second selected signal
`in response to a mode select signal.
`23. The system of claim 22 Wherein the common signal
`and the second mode signals are complementary.
`24. The system of claim 23 Wherein the ?rst mode signal
`is a reference signal having a voltage level proportional to
`one of the ?rst and second voltage levels.
`25. The system of claim 22 Wherein the signal generator
`comprises:
`a ?rst ampli?er having ?rst positive and negative inputs
`coupled to the selector to receive the ?rst selected
`signal at the ?rst positive input and the second selected
`signal at the ?rst negative input, the ?rst ampli?er
`generating a ?rst differential signal corresponding to
`the ?rst strobe signal; and
`a second ampli?er having second positive and negative
`inputs coupled to the selector to receive the ?rst
`selected signal at the second negative input and the
`second selected signal at a second positive input, the
`second ampli?er generating a second differential signal
`corresponding to the second strobe signal.
`26. The system of claim 25 Wherein the signal generator
`further comprises:
`a ?rst buffer coupled to the ?rst ampli?er to generate the
`?rst strobe signal from the ?rst differential signal; and
`a second buffer coupled to the second ampli?er to gen
`erate the second strobe signal from the second differ
`ential signal.
`27. The system of claim 22 Wherein the ?rst and second
`selecting elements have approximately equal propagation
`delays.
`28. The system of claim 22 Wherein the ?rst and second
`selecting elements are transistors having a gate-oxide thick
`ness comparable With the second voltage level.
`29. The system of claim 26 Wherein the interface port is
`an Accelerated Graphics Port (AGP).
`30. The system of claim 29 Wherein the ?rst and second
`modes are 4X and 2X transfer modes, respectively.
`
`*
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