Case 3:14-cv-00757-REP-DJN Document 30-4 Filed 12/19/14 Page 1 of 24 PageID# 828
`Case 3:14-cv-00757-REP-DJN Document 30-4 Filed 12/19/14 Page 1 of 24 Page|D# 828
`
`
`EXHIBIT D
`
`EXHIBIT D
`
`
`
`
`
`
`
`
`
`
`
`
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 30-4 Filed 12/19/14 Page 2 of 24 PageID# 829
`
`(12) United States Patent
`Seo et al.
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 6,819,602 B2
`Nov. 16, 2004
`
`US006819602B2
`
`(54) MULTIMODE DATA BUFFER AND METHOD
`FOR CONTROLLING PROPAGATION
`DELAY TIME
`
`(75) Inventors: Seong-young Seo, SuWon (KR);
`Jung-bae Lee, Yongin (KR); Byong-mo
`Moon, Seoul (KR)
`
`(73) Assignee: Samsung Electronics Co., Ltd.,
`Kyllngki-Do (KR)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 77 days.
`
`(21) Appl- NOJ 10/278!071
`(22) Filed:
`Oct 23, 2002
`
`(65)
`
`Prior Publication Data
`US 2003/0210575 A1 Nov. 13, 2003
`
`Related U S Application Data
`(60) Provisional application No. 60/379,665, ?led on May 10,
`2002'
`
`7
`
`"""""""""
`' """"""""" "
`
`(
`
`)
`
`-
`
`-
`
`’
`
`'
`
`’ 365/194;
`
`(58) Field of Search .......................... .. 365/18905, 191,
`365/193 194
`’
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`6,396,768 B2 * 5/2002 Ooishi ...................... .. 365/233
`6,414,517 B1
`7/2002 Kim et al.
`6,424,590 B1 * 7/2002 Taruishi et al. ...... .. 365/23008
`6,452,849 B1 * 9/2002 IWamoto ................... .. 365/201
`6,512,704 B1 * 1/2003 Wu et al. ..
`. 365/18907
`2003/0090294 A1 * 5/2003 Chang ....................... .. 326/93
`
`FOREIGN PATENT DOCUMENTS
`
`EP
`KR
`
`0322915 A3
`2002046826
`
`7/1989
`6/2002
`
`*
`
`.
`.t d b
`C1 6
`y exammer
`
`Primary Examiner—Van Thu Nguyen
`(74) Attorney, Agent, or Firm—Harness, Dickey & Pierce,
`PLC
`
`(57)
`
`ABSTRACT
`
`A data buffer, such as a data strobe input buffer or a data
`Input buffer’ Whlch may operate In multlple modes’ Such as
`a single mode (SM) and a dual mode (DM) and Where the
`mode is selected by providing a signal, such as an external
`signal such as an address signal or an external command
`signal. A data buffer Which can be used for a SM/DM
`
`dualfuse and can lmprove. a .data Pulp/hold margm A
`semiconductor memory device mcludmg one or more of the
`data buffers described above. A method for controlling
`propagation delay times Which can improve a data setup/
`hold margm in a SM/DM dual-use data buffer.
`
`6,279,073 B1 * 8/2001 McCracken et al. ...... .. 711/105
`
`29 Claims, 13 Drawing Sheets
`
`r __________ _ .. A ______ _ _
`
`F ______ _ _ L _______ _. _ _}
`
`21
`
`23
`
`,5 1 3
`
`DQS
`
`|
`
`l
`‘
`l
`:
`I NTB CNT
`; c
`/
`.
`l
`0088 D I
`;
`:CNT/CNTB‘
`|
`I
`VREF I
`:
`
`21 3
`5
`DIFFERENTIAL
`AMPLIHER
`
`"
`
`"
`
`l
`.
`CNT/CNTB
`|
`1
`:
`2-12
`"7**—’ D5
`N2 :
`;
`I
`;
`23tCNTB/CNT
`253 g
`:
`
`l
`
`_
`
`.
`
`'
`
`I
`:
`
`212
`
`21 l
`
`L _ _ _ _ _ . _ _ _ _ _ _ _ _ _ _ _ _ _ _ - .. J
`
`L _ _ . . _ . _ _ _ a _ _ _ _ . _ _ _ 1- J
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 30-4 Filed 12/19/14 Page 3 of 24 PageID# 830
`Case 3:14-cv-OO757-REP-DJN Document 30-4 Filed 12/19/14 Page 3 of 24 Page|D# 830
`
`US. Patent
`
`Nov. 16, 2004
`
`Sheet 1 0f 13
`
`US 6,819,602 B2
`
`FIG.
`
`1
`
`Prior Art
`
`DO
`
`005
`
`DIN
`
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 30-4 Filed 12/19/14 Page 4 of 24 PageID# 831
`
`U.S. Patent
`
`Nov. 16, 2004
`
`Sheet 2 6f 13
`
`US 6,819,602 B2
`
`FIG. 3A
`
`212
`
`0088 '
`
`
`
`CNTB VREF
`
`V
`
`T 211
`
`r
`
`_ CNT
`
`FIG. 38
`
`(INT
`
`7
`
`{>6
`
`* CNTB
`
`FIG. 4
`
`CNT/CNTB
`
`[15
`MODE
`REC'STER SET
`
`A
`
`COMMAND ADD
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 30-4 Filed 12/19/14 Page 5 of 24 PageID# 832
`
`U.S. Patent
`
`Nov. 16, 2004
`
`Sheet 3 6f 13
`
`US 6,819,602 B2
`
`FIG. 5A
`
`fZSi
`
`714
`
`cm
`
`FIG. 5B
`
`VOLTAGE LEVEL
`
`POWER
`
`f
`
`r-VCCH
`f
`
`T E
`
`- :M
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 30-4 Filed 12/19/14 Page 6 of 24 PageID# 833
`Case 3:14-cv-OO757-REP-DJN Document 30-4 Filed 12/19/14 Page 6 of 24 Page|D# 833
`
`US. Patent
`
`Nov. 16, 2004
`
`Sheet 4 0f 13
`
`US 6,819,602 B2
`
`FIG. 6
`
`v00
`
`14100l14200 144-00
`_g>£*--CNT
`
`14300
`
`FIG;
`
`7’
`
`’jf13
`
`23
`F ________ 24 _________
`
`CNT/CNTB
`
`E
`
`—-Ds
`
`N2
`
`‘231CNTB/CNT
`
`'
`
`DWFERENUAL
`AMPUFER
`
`-
`
`‘
`
`{DEW
`
`:232
`
`
`
`233
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 30-4 Filed 12/19/14 Page 7 of 24 PageID# 834
`
`U.S. Patent
`
`Nov. 16, 2004
`
`Sheet 5 6f 13
`
`US 6,819,602 B2
`
`Egg.
`
`2
`
`U
`
`05
`
`DO
`
`FIG.
`
`CNT
`
`DELAY
`5
`31
`
`FIG.
`
`0. D
`
`DOS
`
`DIN
`
`SM mode ‘——~- 05
`
`DM mode ——-—> DS
`
`I
`z
`
`:
`i
`
`1
`'
`
`l W
`_______7FDH
`
`I
`l
`
`I
`I
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 30-4 Filed 12/19/14 Page 8 of 24 PageID# 835
`
`U.S. Patent
`
`Nov. 16, 2004
`
`Sheet 6 6f 13
`
`US 6,819,602 B2
`
`FIG. 10
`
`/21
`
`I3 4
`/
`
`F ‘ “ _ _ _ _ " _ _ ' _ _ _ _ “ _ _ —" _ _ _ — _ ~ "*1!
`
`00s c>-—I—~—-————
`I
`
`l
`
`:
`:
`
`l
`
`j 213
`
`DIFFERENTIAL
`AMPLIFIER
`
`l
`I
`I
`I CNTB/CNT
`‘I
`l
`212
`I
`0088 I3 1
`I
`I
`I
`I CNT/CNTB ‘H
`I
`:
`I
`,
`:
`211
`I
`‘L ___________________________ "J
`
`23
`\
`i
`Cdummy
`g vREF
`
`vss
`
`_
`DO
`
`FIG. 1 1
`
`DQS
`
`VREF
`
`/ 31
`Ist
`DIFFERENTIAL
`AMPLIFIER
`
`CNT/CNTB
`f
`33
`L
`
`/ 32
`2nd
`DIFFERENTIAL
`D058 C>———-— AMPLIFIER
`
`CNTB/CNT
`34
`
`{
`
`/ 13m
`)7
`
`->-———~ 0s
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 30-4 Filed 12/19/14 Page 9 of 24 PageID# 836
`
`U.S. Patent
`
`Nov. 16, 2004
`
`Sheet 7 0f 13
`
`US 6,819,602 B2
`
`FIG. 12
`
`/ 31
`
`CNT/CNTB
`
`.130
`
`DOS
`
`VREF
`
`‘SI
`DIFFERENTIAL
`AMPLIFIER
`
`~ 33
`""——
`
`/ 32
`2nd
`DIFFERENTIAL
`AMPLIFIER
`
`CNTB/CNT
`-34
`'
`
`DELAY ""231
`
`DQSB I}
`
`FIG. 13
`
`005
`
`VR EF
`
`DQSB
`
`j 31
`1st
`DIFFERENTIAL
`AMPLIFIER
`
`CNT/CNTB
`‘I33
`
`/ 32
`
`CNTB/C NT
`
`/
`
`2nd
`DIFFERENTIAL
`AMPLIFIER
`I Cdummy
`
`VSS
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 30-4 Filed 12/19/14 Page 10 of 24 PageID# 837
`
`U.S. Patent
`
`Nov. 16, 2004
`
`Sheet 8 6f 13
`
`US 6,819,602 B2
`
`FIG. 14
`
`r____...___..___.__._____
`
`DO
`
`CNTB/CNT
`
`DIFFERENTIAL
`AMPLIFIER
`
`@212
`I
`
`060/0608
`
`21 1
`
`FIG. 15
`
`_
`
`_ I
`
`[____._____/
`
`Q B D O
`
`D
`
`_ D _
`
`_ C N _ H / C W B / _ T T _ _ N N _ _ C C _
`
`rul- I l I I I l I I I I I I I | I I I IIL
`n 2 I 1 n
`_ TNI MM. m MM. _
`
`_ _
`
`I. 2 _ EP 2“ FM "
`. I .
`
`/ WA 2
`
`_ UI _
`
`_ I_ _ _ AIMR _
`
`_ ME _
`
`
`
`.I I I I I I I I l I I I I I I . I I I I I I III“
`
`2J3
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 30-4 Filed 12/19/14 Page 11 of 24 PageID# 838
`
`U.S. Patent
`
`Nov. 16, 2004
`
`Sheet 9 6f 13
`
`US 6,819,602 B2
`
`FIG. 16
`
`21
`________.~_________I_/
`
`ems/cm
`
`I:212
`
`C l
`I
`
`DIFFERENTIAL
`AMPLIFIER
`
`Cdummy
`g VREF
`VSS
`
`I
`l
`l
`
`I
`I
`I
`L
`
`FIG. 17
`
`DO
`VREF
`
`Ist
`DIFFERENTIAL
`AMPLIFIER
`
`/ 32
`2nd
`DIFFERENTIAL
`DOB C>——-—.~ AMPLIFIER
`
`IIQ
`
`,4
`
`'>-———> DIN
`
`CNT/CNTB 36“
`
`1
`
`CN'IB/CNT
`34
`
`<
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 30-4 Filed 12/19/14 Page 12 of 24 PageID# 839
`
`U.S. Patent
`
`NOV. 16, 2004
`
`Sheet 10 0f 13
`
`US 6,819,602 B2
`
`FIG. 18
`
`DQ
`
`vREF
`
`/ 31
`1st
`DIFFERENTIAL
`AMPLIFIER
`
`cNT/cNTB
`,33
`
`6,1 10
`/
`
`/ 32
`2nd
`DIFFERENTIAL
`DOB E>—--——— AMPLIFIER
`
`cNTB/LNT
`,34
`
`»-——~- DIN
`
`DELAY ~— 231
`
`FIG. 19
`
`i1 ‘i0
`
`/ 31
`ISI
`DIFFERENTIAL
`AMPLIFIER
`
`CNT/CNTB
`,33
`
`/ 32
`2nd
`DIFFERENTIAL
`AMPLIFIER
`
`I
`
`»—-- DIN
`
`"
`cNTB/LNT
`,34
`
`DO
`
`VREF
`
`DOB
`
`$- CdurT‘Imy
`VSS
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 30-4 Filed 12/19/14 Page 13 of 24 PageID# 840
`
`U.S. Patent
`
`Nov. 16, 2004
`
`Sheet 11 6f 13
`
`US 6,819,602 B2
`
`FIG. 20
`
`17
`._____l
`
`n -
`
`/
`
`D
`
`‘Yul!
`
`
`
`Flll 1 I § I I I I | % l lllllIL
`
`W S
`D D
`
`DO [I>-—-———
`
`AB AEB
`DT DBT m U OU N P RD. C W gm V
`
`m U MS U
`j W / Err. /
`n m w MW 6
`
`N
`
`DOS
`DOSE
`VREF
`
`N C
`
`MODE
`REGISTER SET
`
`6
`
`COMMAND ADD
`
`FIG. 21
`
`COMMAND G) I\_/_\_/_\_/\_
`
`O0
`
`MWQ @QQQ —-———
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 30-4 Filed 12/19/14 Page 14 of 24 PageID# 841
`
`U.S. Patent
`
`Nov. 16, 2004
`
`0f 13
`Sheet 12
`
`US 6,819,602 B2
`
`FIG.
`
`22
`
`DIN [3
`
`CH jab 21 7b
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 30-4 Filed 12/19/14 Page 15 of 24 PageID# 842
`
`U.S. Patent
`
`Nov. 16, 2004
`
`Sheet 13 6f 13
`
`US 6,819,602 B2
`
`_..-______/_
`
`17
`j17o
`O
`D
`
`1
`l
`I
`l
`I
`I
`
`FIG. 23
`
`/11
`
`DIN
`
`Flllll
`
`DDS
`0058
`VREF
`
`/13
`DATA
`STROBE SlGNAL
`INPUT BUFFER
`
`CNT 1’
`
`/15
`MODE
`REGISTER SET
`
`i
`
`0
`
`COMMAND ADD
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 30-4 Filed 12/19/14 Page 16 of 24 PageID# 843
`
`US 6,819,602 B2
`
`1
`MULTIMODE DATA BUFFER AND METHOD
`FOR CONTROLLING PROPAGATION
`DELAY TIME
`
`CROSS REFERENCE TO RELATED
`APPLICATIONS
`This US. nonprovisional application claims priority
`under 35 U.S.C. § 119 to US. Provisional Patent Applica
`tion No. 60/379,665 ?led May 10, 2002, the entire contents
`of Which are incorporated by reference.
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`The present invention relates to a semiconductor memory
`device, and more particularly, to a multimode data buffer and
`a method for controlling propagation time delay.
`2. Description of the Related Art
`To improve system performances, innovations in the
`design of semiconductor memory devices in general, and the
`design of dynamic random access memories (DRAMs) in
`particular, continue to focus on higher integration and higher
`speed operation. That is, DRAMs capable of processing
`more data at higher speed are desired. For higher speed
`operations, DRAMs synchroniZed With a system clock have
`been developed. This synchronous feature of DRAMs has
`increased data transmission speeds.
`HoWever, since a data input/output operation in a syn
`chronous DRAM should be performed in a cycle of a system
`clock, there is a limit to increasing the bandWidth betWeen
`the synchronous DRAM and a DRAM controller, that is, the
`amount of data Which is input/output from a memory device
`in a unit time is limited. In order to increase data transmis
`sion speed, dual data rate (DDR) synchronous DRAMs in
`Which data is input/output synchroniZed both With the rising
`edge and falling edge of a clock have been developed.
`In general, a DDR synchronous DRAM uses a data strobe
`signal When the DRAM receives data from a memory
`controller or sends data to the memory controller. For
`example, in a data receiving operation, the DDR synchro
`nous DRAM receives data With a data strobe signal from the
`memory controller. Also, in a data outputting operation, the
`DDR synchronous DRAM outputs data With a data strobe
`signal to the memory controller.
`In high speed semiconductor memory devices such as
`DDR synchronous DRAMs, a single mode (SM)-type input
`buffer, Which compares a data strobe signal With a reference
`voltage, is used as a data strobe input buffer. HoWever, in a
`DDR synchronous DRAM having an SM-type data strobe
`signal input buffer, a data setup/hold time margin may be
`degraded if noise is included in a data strobe signal or
`reference voltage.
`In order to compensate for this problem, a dual mode
`(DM)-type data strobe signal input buffer Which compares a
`data strobe signal With the inverse signal of the data strobe
`signal instead of reference voltage has been introduced.
`Since an output signal is determined at the cross point of
`the tWo signals, that is, the data strobe signal and an inverse
`of the data strobe signal, in the DM-type data strobe signal
`input buffer, noise immunity improves.
`Also, more recently, in order to satisfy demands of a
`variety of users, an SM/DM dual-use data strobe signal input
`buffer has been developed. In an SM/DM dual-use data
`strobe signal input buffer, propagation delay time from an
`input terminal to an output terminal should be substantially
`the same both in the single mode (SM) and in the dual mode
`
`10
`
`15
`
`25
`
`35
`
`45
`
`55
`
`65
`
`2
`(DM). HoWever, since the gain of a differential ampli?er in
`the single mode is different from the gain in the dual mode,
`the propagation delay time in the single mode is different
`from the propagation delay time in the dual mode.
`FIG. 1 illustrates Waveforms produced in accordance With
`the prior art. As shoWn in FIG. 1, propagation delay time of
`the differential output signal (DS) in the SM mode is much
`greater than in the DM mode. Outputting the differential
`output signal (DS) at a different time in the SM mode and the
`DM mode degrades the uniformity of both the data setup
`time (tDS) and the data hold time (tDH) as illustrated in FIG.
`1. The difference in the propagation delay time may cause a
`difference in the setup/hold timing in each mode such that a
`data setup/hold margin is degraded.
`
`SUMMARY OF THE INVENTION
`Exemplary embodiments of the present invention are
`directed to a data buffer, Which operates in a multiple modes,
`such as a data strobe input buffer or a data input buffer, each
`of Which may operate a single mode (SM) and a dual mode
`(DM) and Where a mode is selected by providing a signal,
`such as an external signal such as an address signal or an
`external command signal. The signal may be supplied by a
`number of sources, such as an internal mode register set
`(MRS), a fuse circuit, or a bonding pad circuit.
`Exemplary embodiments of the present invention are also
`directed to a data buffer Which can be used for a SM/DM
`dual-use and can improve a data setup/hold margin.
`Exemplary embodiments of the present invention are also
`directed to a semiconductor memory device including one or
`more of the data buffers described above.
`In addition, exemplary embodiments of the present inven
`tion are directed to a method for controlling propagation
`delay time Which can improve a data setup/hold margin in a
`SM/DM dual-use data buffer.
`Exemplary embodiments of the present invention are also
`directed to a data buffer including a differential ampli?er
`circuit including at least tWo sWitches for passing an inverse
`data signal or a reference voltage, respectively, depending
`on a level of a control signal, and a differential ampli?er for
`receiving a data signal, and either the inverse data signal or
`the reference voltage and outputting at least tWo different
`differentially ampli?ed signals.
`In exemplary embodiments of the present invention, the
`data buffer is a data strobe input buffer, the inverse data
`signal is an inverse data strobe signal, and the data signal is
`a data strobe signal.
`In exemplary embodiments of the present invention, the
`data strobe input buffer is operable in both a single mode and
`a dual mode, Wherein in said single mode, the reference
`voltage is applied to a ?rst of the at least tWo sWitches and
`the level of the control signal is a ?rst logic state and in said
`dual mode, the inverse data strobe signal is provided to a
`second of the at least tWo sWitches 212 and the level of the
`control signal is a second logic state.
`In exemplary embodiments of the present invention, the
`data strobe input buffer is part of a semiconductor memory
`device. In exemplary embodiments of the present invention,
`the semiconductor memory device also includes a control
`circuit for outputting the control signal to the data strobe
`input buffer.
`In exemplary embodiments of the present invention, the
`control circuit includes a mode register set for receiving an
`external command and an address and generating the control
`signal, Wherein a level of the control signal determines a
`mode of the semiconductor memory device.
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 30-4 Filed 12/19/14 Page 17 of 24 PageID# 844
`
`US 6,819,602 B2
`
`3
`In exemplary embodiments of the present invention, the
`control circuit includes a fuse circuit including a fuse,
`Wherein a state of the fuse determines a level of the control
`signal.
`In exemplary embodiments of the present invention, the
`control circuit includes a bonding pad circuit, Wherein a
`connection to Vcc or ground determines a level of the
`control signal.
`In exemplary embodiments of the present invention, the
`differential ampli?er unit includes a single differential
`ampli?er.
`In exemplary embodiments of the present invention, the
`semiconductor memory device further includes a compen
`sating circuit for compensating one of the inverse data strobe
`signal, the reference voltage, or the data strobe signal or one
`of the at least tWo different differentially ampli?ed signals so
`that each of at least tWo differential output signals have
`substantially the same delay time.
`In exemplary embodiments of the present invention, the
`compensating circuit includes a delay circuit for receiving
`the differentially ampli?ed signal from said differential
`ampli?er circuit, said delay circuit including a delay for
`delaying the differentially ampli?ed signal, at least tWo
`additional sWitches for passing the differentially ampli?ed
`signal or the delayed differentially ampli?ed signal, as one
`of the at least tWo differential output signals, depending on
`the level of the control signal.
`In exemplary embodiments of the present invention, the
`compensating circuit includes a dummy load applied to one
`of the inverse data strobe signal, the reference voltage, or the
`data strobe signal.
`In exemplary embodiments of the present invention, the
`differential ampli?er unit includes at least tWo differential
`ampli?ers.
`In exemplary embodiments of the present invention, a
`gain of a ?rst of the at least tWo differential ampli?ers is
`substantially different from a gain of a second of the at least
`tWo differential ampli?ers so that each of at least tWo
`differential output signals have substantially the same delay
`time.
`In exemplary embodiments of the present invention, a
`gain of a ?rst of the at least tWo differential ampli?ers is
`substantially the same as a gain of a second of the at least
`tWo differential ampli?ers.
`In exemplary embodiments of the present invention, the
`semiconductor memory device further includes a compen
`sating circuit for compensating one of the inverse data strobe
`signal, the reference voltage, or the data strobe signal or one
`of the at least tWo different differentially ampli?ed signals so
`that each of at least tWo differential output signals have
`substantially the same delay time.
`In exemplary embodiments of the present invention, the
`compensating circuit includes a delay circuit for receiving
`the differentially ampli?ed signal from said differential
`ampli?er circuit, said delay circuit including a delay for
`delaying the differentially ampli?ed signal, at least tWo
`additional sWitches for passing the differentially ampli?ed
`signal or the delayed differentially ampli?ed signal, as one
`of the at least tWo differential output signals, depending on
`the level of the control signal.
`In exemplary embodiments of the present invention, the
`compensating circuit includes a dummy load applied to one
`of the inverse data strobe signal, the reference voltage, or the
`data strobe signal.
`In exemplary embodiments of the present invention, the
`semiconductor memory device further includes data input
`buffer for receiving a data signal and a reference voltage and
`
`10
`
`15
`
`25
`
`35
`
`40
`
`45
`
`55
`
`65
`
`4
`outputting a data input signal, a control circuit for outputting
`the control signal to the data strobe input buffer, and a data
`Write circuit for receiving the data input signal from said
`data input buffer and the Writing even number data of the
`data input signal into a ?rst latch in response to a rising edge
`of the output data signal and Writing odd number data of the
`data input signal into a second latch in response to a falling
`edge of the output data strobe signal.
`In exemplary embodiments of the present invention, the
`?rst latch includes a plurality of latches and a plurality of
`sWitches, arranged alternatively. In exemplary embodiments
`of the present invention, the plurality of sWitches are
`arranged to be triggered on the leading and falling edge of
`an inverse of the differential output signal.
`In exemplary embodiments of the present invention, a
`?rst sWitch receives the even number data of the output
`signal of the data input buffer and passes the even number
`data of the output signal to a ?rst of the plurality of latches.
`In exemplary embodiments of the present invention, the
`second latch including a plurality of latches and a plurality
`of sWitches, arranged alternatively.
`In exemplary embodiments of the present invention, the
`plurality of sWitches are arranged to be triggered on the
`leading and falling edge of an inverse of the differential
`output signal.
`In exemplary embodiments of the present invention, a
`?rst sWitch receives the odd number data of the output signal
`of the data input buffer and passes the odd number data of
`the output signal to a ?rst of the plurality of latches.
`In exemplary embodiments of the present invention, the
`data buffer is a data input buffer instead of, or in addition to,
`a data strobe buffer.
`In exemplary embodiments of the present invention, the
`semiconductor memory device further includes a data strobe
`input buffer for receiving an inverse data signal or a refer
`ence voltage, respectively, depending on a level of a control
`signal, and outputting at least tWo differential output signals,
`a control circuit for outputting the control signal to said data
`strobe input buffer, and a data Write circuit for receiving the
`data input signal from the data input buffer and the Writing
`even number data of the data input signal into a ?rst latch in
`response to a rising edge of the output data signal and
`Writing odd number data of the data input signal into a
`second latch in response to a falling edge of the output data
`strobe signal.
`Exemplary embodiments of the present invention are also
`directed to a method of controlling propagation delay time
`of a semiconductor memory, including receiving an inverse
`data signal or a reference voltage, respectively, depending
`on a level of a control signal, receiving a data signal and
`either the inverse data signal or the reference voltage, and
`amplifying and outputting at least tWo different differentially
`ampli?ed signals.
`In exemplary embodiments of the method of the present
`invention, the inverse data signal is an inverse data strobe
`signal and the data signal is a data strobe signal.
`In exemplary embodiments of the method of the present
`invention, in a single mode, the reference voltage is received
`and a level of the control signal is a ?rst logic state and in
`a dual mode, the inverse data strobe signal is received and
`the level of the control signal is a second logic state.
`In exemplary embodiments of the method of the present
`invention, the control signal is received from an external
`source.
`In exemplary embodiments of the method of the present
`invention, the method also includes receiving an external
`command and an address and generating the control signal,
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 30-4 Filed 12/19/14 Page 18 of 24 PageID# 845
`
`US 6,819,602 B2
`
`5
`wherein a level of the control signal determines an operation
`mode of the semiconductor memory.
`In exemplary embodiments of the method of the present
`invention, a state of a fuse determines a level of the control
`signal.
`In exemplary embodiments of the method of the present
`invention, a connection to Vcc or ground via a bonding pad
`determines a level of the control signal.
`In exemplary embodiments of the method of the present
`invention, the amplifying is performed by a single differen
`tial ampli?er.
`In exemplary embodiments of the method of the present
`invention, the method further comprises compensating one
`of the inverse data strobe signal, the reference voltage, or the
`data strobe signal or one of the at least tWo different
`differentially ampli?ed signals so that each of at least tWo
`differential output signals have substantially the same delay
`time.
`In exemplary embodiments of the method of the present
`invention, the compensating includes receiving the differ
`entially ampli?ed signal and delaying the differentially
`ampli?ed signal, and outputting the differentially ampli?ed
`signal or the delayed differentially ampli?ed signal, as one
`of the at least tWo differential output signals, depending on
`the level of the control signal.
`In exemplary embodiments of the method of the present
`invention, the compensating is performed With a dummy
`load applied to one of the inverse data strobe signal, the
`reference voltage, or the data strobe signal.
`In exemplary embodiments of the method of the present
`invention, the amplifying is performed by at least tWo
`differential ampli?ers.
`In exemplary embodiments of the method of the present
`invention, a gain of a ?rst of the at least tWo differential
`ampli?ers is substantially different from a gain of a second
`of the at least tWo differential ampli?ers so that each of at
`least tWo differential output signals have substantially the
`same delay time.
`In exemplary embodiments of the method of the present
`invention, a gain of a ?rst of the at least tWo differential
`ampli?ers is substantially the same as a gain of a second of
`the at least tWo differential ampli?ers.
`In exemplary embodiments of the method of the present
`invention, the method further comprises compensating one
`of the inverse data strobe signal, the reference voltage, or the
`data strobe signal or one of the at least tWo different
`differentially ampli?ed signals so that each of at least tWo
`differential output signals have substantially the same delay
`time.
`In exemplary embodiments of the method of the present
`invention, the compensating includes receiving the differ
`entially ampli?ed signal, delaying the differentially ampli
`?ed signal, and outputting the differentially ampli?ed signal
`or the delayed differentially ampli?ed signal, as one of the
`at least tWo differential output signals, depending on the
`level of the control signal.
`In exemplary embodiments of the method of the present
`invention, the compensating is performed With a dummy
`load applied to one of the inverse data strobe signal, the
`reference voltage, or the data strobe signal.
`In exemplary embodiments of the method of the present
`invention, the method further includes receiving a data
`signal and a reference voltage and outputting a data input
`signal, outputting the control signal, and receiving the data
`input signal and the Writing even number data of the data
`input signal into a ?rst latch in response to a rising edge of
`the output data signal and Writing odd number data of the
`
`10
`
`15
`
`25
`
`35
`
`40
`
`45
`
`55
`
`65
`
`6
`data input signal into a second latch in response to a falling
`edge of the output data strobe signal.
`In exemplary embodiments of the method of the present
`invention, the ?rst latch includes a plurality of latches and a
`plurality of sWitches, arranged alternatively.
`In exemplary embodiments of the method of the present
`invention, the plurality of sWitches are arranged to be
`triggered on the leading and falling edge of an inverse of the
`differential output signal.
`In exemplary embodiments of the method of the present
`invention, a ?rst sWitch receives the even number data of the
`output signal and passes the even number data of the output
`signal to a ?rst of the plurality of latches.
`In exemplary embodiments of the method of the present
`invention, the second latch includes a plurality of latches and
`a plurality of sWitches, arranged alternatively.
`In exemplary embodiments of the method of the present
`invention, the plurality of sWitches are arranged to be
`triggered on the leading and falling edge of an inverse of the
`differential output signal.
`In exemplary embodiments of the method of the present
`invention, a ?rst sWitch receives the odd number data of the
`output signal and passes the odd number data of the output
`signal to a ?rst of the plurality of latches.
`In exemplary embodiments of the method of the present
`invention, the data buffer is a data input buffer instead of, or
`in addition to, a data strobe buffer.
`In exemplary embodiments of the method of the present
`invention, the method further includes receiving a data
`signal and a reference voltage and outputting a data input
`signal, outputting the control signal, and receiving the data
`input signal and the Writing even number data of the data
`input signal into a ?rst latch in response to a rising edge of
`the output data signal and Writing odd number data of the
`data input signal into a second latch in response to a falling
`edge of the output data strobe signal.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`The present invention Will become more apparent by
`describing in detail exemplary embodiments thereof With
`reference to the attached draWings in Which:
`FIG. 1 illustrates Waveforms produced in accordance With
`the prior art;
`FIG. 2 is a block diagram of a data strobe input buffer
`according to an exemplary embodiment of the present
`invention;
`FIG. 3A is a block diagram of the sWitches according to
`an exemplary embodiment of the present invention;
`FIG. 3B is a block diagram Which illustrates the conver
`sion from the control signal (CNT) to the inverse control
`signal (CNTB) according to an exemplary embodiment of
`the present invention;
`FIG. 4 is a block diagram of a control circuit according to
`an exemplary embodiment of the present invention;
`FIG. 5A is a block diagram of a control circuit according
`to another exemplary embodiment of the present invention;
`FIG. 5B illustrates a time versus voltage level plot relative
`to VCCH for the exemplary circuit of FIG. 5A;
`FIG. 6 is a block diagram of another control circuit
`according to another exemplary embodiment of the present
`invention;
`FIG. 7 is a block diagram of a data strobe input buffer
`according to another exemplary embodiment of the present
`invention;
`FIG. 8 is a block diagram of the sWitches according to an
`exemplary embodiment of the present invention;
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 30-4 Filed 12/19/14 Page 19 of 24 PageID# 846
`
`US 6,819,602 B2
`
`7
`FIG. 9 illustrates Waveforms produced in accordance With
`one or more exemplary embodiments of the present inven
`tion;
`FIG. 10 is a block diagram of a data strobe input buffer
`according to another exemplary embodiment of the present
`invention;
`FIG. 11 is a block diagram of a data strobe input buffer
`according to another exemplary embodiment of the present
`invention;
`FIG. 12 is a block diagram of a data strobe input buffer
`according to another exemplary embodiment of the present
`invention;
`FIG. 13 is a block diagram of a data strobe input buffer
`according to another exemplary embodiment of the present
`invention;
`FIG. 14 is a block diagram of a data input buffer according
`to an exemplary embodiment of the present invention;
`FIG. 15 is a block diagram of a data input buffer according
`to another exemplary embodiment of the present invention;
`FIG. 16 is a block diagram of a data input buffer according
`to another exemplary embodiment of the present invention;
`FIG. 17 is a block diagram of a data input buffer according
`to another exemplary embodiment of the present invention;
`FIG. 18 is a block diagram of a data input buffer according
`to another exemplary embodiment of the present invention;
`FIG. 19 is a block diagram of a data input buffer according
`to another exemplary embodiment of the present invention;
`FIG. 20 is a block diagram of a semiconductor memory
`device according to an exemplary embodiment of the
`present invention;
`FIG. 21 illustrates the output of the data strobe signal
`(DOS) and the data signal (DQ) during DDR operation
`according to a semiconductor memory device according to
`an exemplary embodiment of the present invention;
`FIG. 22 is a block diagram of the latch circuit according
`to an exemplary embodiment of the present invention;
`FIG. 23 is a block diagram of a semiconductor memory
`device according to another exemplary embodiment of the
`present invention.
`DETAILED DESCRIPTION OF THE
`EXEMPLARY EMBODIMENTS OF THE
`PRESENT INVENTION
`FIG. 2 is a block diagram of a data strobe input buffer
`according to an exemplary embodiment of the present
`invention. The data strobe input buffer 13 is a multimode
`data strobe input buffer, for example, a single mode/dual
`mode (SM/DM) double-use data strobe input buffer. In
`response to a control signal (CNT/CNTB), the data strobe
`input buffer 13 differentially ampli?es a data strobe signal
`(DOS) and a reference voltage (VREF), or the data strobe
`signal (DOS) and an inverse data strobe signal (DQSB).
`More speci?cally, the data strobe input buffer 13 includes
`a differential ampli?cation circuit 21. The differential ampli
`?cation circuit 21 further includes one or more sWitches 211
`and 212, and a differential ampli?er 213. In an exemplary
`embodiment, th