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`EXHIBIT B
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`EXHIBIT B
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`case 3:14-cv-oo7s7-REP-DJN Documentsolllllliilllilulllllilillflllulllllllllilelllllllllliilllllllllllllilllilliws
`Case 3:14-cv-00757-REP-DJN Document 30-2 Filed 12/19/14 Page 2 of 22 PageID# 798
`USOO6262938B1
`
`(12) United States Patent
`(10) Patent N0.:
`US 6,262,938 B1
`
`Lee et al.
`(45) Date of Patent:
`Jul. 17, 2001
`
`(54) SYNCHRONOUS DRAM HAVING POSTED
`CAS LATENCY AND METHOD FOR
`CONTROLLING CAS LATENCY
`
`(75)
`
`Inventors: Jung-bae Lee; Choong-sun Shin;
`Dong-yang Lee, all of Kyungki-do
`(KR)
`
`5,835,956
`6,088,255 *
`
`11/1998 Park et al..
`7/2000 Matsuzaki et a1.
`
`.................... 365/76
`
`* cited by examiner
`
`Primary Examiner—David Nelms
`Assistant Examiner—Thong Le
`(74) Attorney, Agent, or Firm—Jones Volentine, L.L.C.
`
`(73) Assignee: Samsung Electronics C0., Ltd., Suwon
`(KR)
`
`(57)
`
`ABSTRACT
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 09/518,144
`
`(22)
`
`Filed:
`
`Mar. 3, 2000
`
`(30)
`
`Foreign Application Priority Data
`
`Mar. 3, 1999
`Jun. 5, 1999
`
`(KR)
`(KR)
`
`................................................... 99—6939
`................................................. 99—20821
`
`Int. Cl? ....................................................... G11C 8/00
`(51)
`(52) US. Cl.
`.......................... 365/233; 365/194; 365/240;
`365/236
`
`(58) Field of Search .............................. 365/78, 194, 205,
`365/230.02, 230.03, 236, 240, 233
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`A synchronous DRAM (SDRAM) having a posted column
`access strobe (CAS) latency and a method of controlling
`CAS latency are provided. In order to control a delay time
`from the application of a CAS command and a column
`address to the beginning of memory, reading or writing
`operations in units of clock cycles, a first method of pro-
`graming the delay time as a mode register set (MRS) and a
`second method of detecting the delay time using an internal
`signal and an external signal, are provided. In the second
`method, the SDRAM can include a counter for controlling
`the CAS latency. This counter controls the CAS latency of
`the SDRAM by generating a signal for controlling the CAS
`latency according to the number of clock cycles of a clock
`signal from the generation of a row access command to a
`column access command in the same memory bank and
`reading the signal. It is therefore possible to appropriately
`perform a posted CAS latency operation and a general CAS
`latency operation by the SDRAM Without an additional
`MRS command according to this SDRAM and the method
`of controlling the CAS latency.
`
`5,587,950 * 12/1996 Sawada et al.
`
`...................... 365/201
`
`24 Claims, 11 Drawing Sheets
`
`
`
`MEMORY
`CELL
`BANK
`
`CLK
`
`
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 30-2 Filed 12/19/14 Page 3 of 22 PageID# 799
`Case 3:14-cv-OO757-REP-DJN Document 30-2 Filed 12/19/14 Page 3 of 22 Page|D# 799
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`US. Patent
`
`Jul. 17, 2001
`
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`US 6,262,938 B1
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`Case 3:14-cv-00757-REP-DJN Document 30-2 Filed 12/19/14 Page 4 of 22 PageID# 800
`Case 3:14-cv-OO757-REP-DJN Document 30-2 Filed 12/19/14 Page 4 of 22 Page|D# 800
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`US. Patent
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`Jul. 17, 2001
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`Case 3:14-cv-00757-REP-DJN Document 30-2 Filed 12/19/14 Page 5 of 22 PageID# 801
`Case 3:14-cv-OO757-REP-DJN Document 30-2 Filed 12/19/14 Page 5 of 22 Page|D# 801
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`US. Patent
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`Jul. 17, 2001
`
`Sheet 3 0f 11
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`US 6,262,938 B1
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`Case 3:14-cv-00757-REP-DJN Document 30-2 Filed 12/19/14 Page 7 of 22 PageID# 803
`Case 3 14 cv 00757 REP DJN Document 30 2 Flled 12/19/14 Page 7 of 22 Page|D# 803
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`US. Patent
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`Jul. 17, 2001
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`Case 3:14-cv-00757-REP-DJN Document 30-2 Filed 12/19/14 Page 8 of 22 PageID# 804
`Case 3:14-cv-OO757-REP-DJN Document 30-2 Filed 12/19/14 Page 8 of 22 Page|D# 804
`
`US. Patent
`
`Jul. 17, 2001
`
`Sheet 6 0f 11
`
`US 6,262,938 B1
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`Case 3:14-cv-00757-REP-DJN Document 30-2 Filed 12/19/14 Page 9 of 22 PageID# 805
`Case 3:14-cv-OO757-REP-DJN Document 30-2 Filed 12/19/14 Page 9 of 22 Page|D# 805
`
`US. Patent
`
`Jul. 17, 2001
`
`Sheet 7 0f 11
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`US 6,262,938 B1
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`Case 3:14-cv-00757-REP-DJN Document 30-2 Filed 12/19/14 Page 10 of 22 PageID# 806
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`Case 3:14-cv-00757-REP-DJN Document 30-2 Filed 12/19/14 Page 11 of 22 PageID# 807
`Case 3:14-cv-OO757-REP-DJN Document 30-2 Filed 12/19/14 Page 11 of 22 Page|D# 807
`
`US. Patent
`
`Jul. 17, 2001
`
`Sheet 9 0f 11
`
`US 6,262,938 B1
`
`FIG. 9
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`Case 3:14-cv-00757-REP-DJN Document 30-2 Filed 12/19/14 Page 12 of 22 PageID# 808
`Case 3:14-cv-OO757-REP-DJN Document 30-2 Filed 12/19/14 Page 12 of 22 Page|D# 808
`
`US. Patent
`
`Jul. 17, 2001
`
`Sheet 10 0f 11
`
`US 6,262,938 B1
`
`FIG. 12
`
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`
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`

`

`Case 3:14-cv-00757-REP-DJN Document 30-2 Filed 12/19/14 Page 13 of 22 PageID# 809
`Case 3:14-cv-OO757-REP-DJN Document 30-2 Filed 12/19/14 Page 13 of 22 Page|D# 809
`
`US. Patent
`
`Jul. 17, 2001
`
`Sheet 11 0f 11
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`US 6,262,938 B1
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`Case 3:14-cv-00757-REP-DJN Document 30-2 Filed 12/19/14 Page 14 of 22 PageID# 810
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`US 6,262,938 B1
`
`1
`SYNCHRONOUS DRAM HAVING POSTED
`CAS LATENCY AND METHOD FOR
`CONTROLLING CAS LATENCY
`
`This application relies for priority upon Korean Patent
`Application Nos. 99-6939 and 99-20821, filed on Mar. 3,
`1999, and Jun. 5, 1999, respectively, the contents of which
`are herein incorporated by reference in their entirety.
`
`BACKGROUND OF THE INVENTION
`
`The present invention relates to a synchronous DRAM
`(SDRAM). More particularly, the present invention relates
`to an SDRAM having a column access strobe (CAS) latency,
`as well as a method for controlling the CAS latency.
`In general, an SDRAM is synchronized with a clock
`signal input from outside the circuit and so the read or write
`operation of the SRAM is controlled. FIG. 13 describes the
`latency from the application of a row access command or a
`column access command to the output of data.
`The number of clock cycles of an external clock signal
`from the application of a row access command to the output
`of first data is called the RAS latency (RL). The number of
`clock cycles of the external clock signal from the application
`of a column access command to the output of the first data
`is called the CAS latency (CL). The number of clock cycles
`of the external clock signal from the application of the row
`access command to the application of the column access
`command with respect to the same memory bank is called
`the RAS-CAS latency (RCL). The relationship between
`RCL, RL, and CL is shown in Equation 1.
`
`RL=RCL+CL
`
`(1)
`
`When the minimum value of the RAS latency in the
`frequency of a specific external clock signal is RL
`then
`RL must satisfy Equation 2.
`
`RL iRLm-n
`
`(2)
`
`When the minimum value of the CAS latency in the
`frequency of the specific external clock signal is Cme, then
`min
`RCL
`(the minimum RAS-CAS latency) is expressed as
`shown in Equation 3.
`min—
`RCL —RL
`min_
`min
`
`CL
`
`(3)
`
`In a system using an SDRAM, a function of normally
`outputting data even when RCL<RCme, namely, in posted
`CAS latency, is required in order to improve the perfor-
`mance of the system. In this application, posted CAS latency
`refers to the fact that the CAS command comes earlier than
`
`the conventional RCLml—n. In other words,RL§RLml—n, which
`is generally the product specification, must be satisfied even
`when RCL<RCme.
`In order
`to satisfy the equality
`RLERLml-n in the posted CAS latency, the CAS latency CL
`must satisfy Equation 4
`mm
`CL>CL . +(RCme—RCL)
`
`(4)
`
`In a conventional SDRAM, since the specification of
`(RCLml—n—RCL)<0 is required, it is enough to determine the
`CL, which guarantees the minimum CAS latency Cme by
`a mode register set (MRS) command. However, in a posted
`CAS state, it is possible to input a CAS command (including
`a column address command), which controls an appropriate
`delay time and the latency of a data path only when each of
`the values in Equation 4, i.e., (RCLml—n—RCL) and Cme, are
`known.
`
`2
`SUMMARY OF THE INVENTION
`
`invention to provide a
`is an object of the present
`It
`synchronous DRAM (SDRAM) by which it is possible to
`perform a posted column access strobe (CAS) command.
`It is another object of the present invention to provide a
`method for outputting data using the SDRAM.
`Accordingly, to achieve the first object, A synchronous
`DRAM (SDRAM), operating in synchronization with a
`clock signal, is provided. The SDRAM comprises a memory
`bank having a plurality of memory cells arranged in rows
`and columns, a column decoder for selecting a column of the
`memory bank, a column address input port for inputting a
`column address that selects the column of the memory bank,
`a first shift register for delaying the column address by a first
`number of delay clock cycles between the column address
`input port and the column decoder, and a delay counter for
`sensing the number of clock cycles RCL of the clock signal
`from the application of the row access command to the
`application of the column access command with respect to
`the same bank, and for providing a first delay clock control
`signal
`to the first shift register. Rme is the minimum
`number of clock cycles of the clock signal required from the
`application of a row access command to the output of the
`data of the memory, and Cme is the minimum number of
`clock cycles of the clock signal required from the applica-
`tion of a column access command to the output of the data
`of the memory cell. The first delay clock control signal has
`information on the difference between RCL and (Rme—
`CLml—n), and the first number of delay clock cycles is
`determined in response to the difference between RCL and
`(Rme—Cme).
`The first shift register my comprise a plurality of registers
`serially coupled to each other for continuously transmitting
`the column address in response to the clock signal of every
`period, and a multiplexer for selectively providing one
`signal among the output signals of the plurality of registers
`to the column decoder. The registers are preferably D
`flip-flops.
`The delay counter may comprise a down counter for
`reducing the value of (RLml—n—CLml-n) by 1 in response to the
`clock signal, a register for providing a first delay clock
`control signal having information on an output value stored
`as an output value of the down counter when the column
`access command is generated or an output value of the down
`counter having the value of 0 to the first shift register after
`the row access command is generated, a clock controller that
`is disabled when the output value of the down counter is 0,
`for providing a first clock control signal which is enabled by
`the generation of the row access command and responds to
`the clock signal
`to the down counter, and a logic unit
`disabled by the generation of the column access command,
`for providing a second clock control signal that is enabled by
`the generation of the row access command and responds to
`the first clock control signal. The delay counter may further
`comprise an RCL measuring unit for providing an output
`signal activated by the generation of the row access com-
`mand and disabled by the generation of the column access
`command to the logic unit.
`The synchronous DRAM may further comprise a second
`shift register for delaying the output data of a selected
`memory cell by CLml—n, and a buffer for buffering the output
`signal of the second shift register and delaying the output
`signal of the second shift register by a second number of
`delay clock cycles in response to a second predetermined
`delay clock control signal.
`The SDRAM may further comprising a buffer controller
`for generating a second delay clock control signal
`for
`
`5
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`10
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`

`

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`US 6,262,938 B1
`
`3
`controlling the buffer. The buffer controller itself may com-
`prise a first register for delaying the column access com-
`mand by the second number of delay clock cycles and
`outputting the delayed column access command, every cycle
`of the clock signal, and a second register for delaying the
`output signal of the first register by Cme and generating a
`second delay control signal for controlling the buffer.
`A synchronous DRAM (SDRAM) operating in synchro-
`nization with a clock signal, is also provided. The SDRAM
`comprises a memory bank having a plurality of memory
`cells arranged in rows and columns, a column decoder for
`selecting a column of the memory bank, a pair of bit lines
`for outputting data from the selected column, a sense ampli-
`fier for amplifying the data of the bit lines, a column address
`input port for inputting a column address for selecting the
`column of the memory bank, a first shift register for delaying
`the column address by a first number of delay clock cycles
`between the column address input port and the column
`decoder, and a delay counter for providing a first delay clock
`control signal having information on the difference between
`RCL and SAE to the first shift register. RCL is the number
`of clock cycles of the clock signal from the application of a
`row access command to the application of a column access
`command with respect to the same bank; SAE is the number
`of clock cycles of the clock signal from the application of the
`row access command to the point of time at which the sense
`amplifier is enabled are determined; and the first number of
`delay clock cycles is determined in response to the differ-
`ence between RCL and SAE.
`
`The first shift register may comprise a plurality of regis-
`ters serially coupled to each other, for continuously trans-
`mitting the column address every cycle of the clock signal,
`and a multiplexer for selectively providing one signal among
`the output signals of the registers to the column decoder in
`response to the difference between RCL and SAE.
`Preferably, the registers are D flip-flops.
`The delay counter may comprise a first counting circuit
`for counting SAE and generating a first number of clock
`cycles, a second counting circuit for counting RCL and
`generating a second number of clock cycles, and a subtracter
`for calculating a third number of clock cycles by subtracting
`the first number of clock cycles from the second number of
`clock cycles and using 0 as the third number of clock cycles
`when the first number of clock cycles is larger than the
`second number of clock cycles.
`The first counting circuit may comprise a first logic latch
`unit for generating a first logic latch output signal activated
`by the generation of the row access command and deacti-
`vated by the activation of the sense amplifier enable signal,
`and a first counter enabled in a period when the first logic
`latch output signal is activated, for counting the number of
`clock cycles of the clock signal generated in the activation
`period, and for generating the number of first clock cycles.
`The second counting circuit may comprise a second logic
`latch unit for generating a second logic latch output signal
`activated by the generation of the row access command and
`deactivated by the generation of the column access
`command, and a second counter enabled in a period where
`the second logic latch output signal is activated, for counting
`the number of clock cycles of the clock signal generated in
`the activation period, and for generating the number of
`second clock cycles.
`The delay counter may comprise a logic unit for gener-
`ating a logic output signal that is activated in response to the
`generation of the column access command and is deacti-
`vated in response to a sense amplifier enable signal, the logic
`
`10
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`4
`output signal operating to enable the sense amplifier, and a
`clock counter for counting the number of clock cycles of the
`clock signal generated in a period where the output signal of
`the logic unit is activated.
`The synchronous DRAM may further comprise a second
`shift register for delaying the output data of the memory cell
`by Cer-m where Cme is the minimum number of clock
`cycles of the clock signal required from the application of a
`column access command to the output of the data of the
`memory cell, and a buffer for buffering the output signal of
`the second shift register, and for delaying the output signal
`of the second shift register by the first number of delay clock
`cycles in response to a second delay clock control signal.
`The synchronous DRAM may further comprise a buffer
`controller for generating a second delay clock control signal
`for controlling the buffer. The buffer controller may itself
`comprise a first register for delaying the column access
`command by the first number of delay clock cycles and
`outputting the delayed column access command, and a
`second register for generating a second delay control signal
`for delaying the output signal of the first register by the first
`number of delay clock cycles and controlling the buffer
`every cycle of the clock signal. The first delay clock signal
`is preferably provided from outside of the SDRAM.
`A synchronous DRAM (SDRAM) synchronized with a
`clock signal after predetermined column access strobe
`(CAS) latency has lapsed from a column access command,
`is also provided. The SDRAM comprises a memory bank
`having a plurality of memory cells arranged in rows and
`columns, and a decoder for selecting one of the memory
`cells based on a column address and a row address. The CAS
`
`latency is determined by the number of clock cycles of the
`clock signal from the application of a row access command
`to the application of a column access command with respect
`to the memory bank.
`A synchronous DRAM (SDRAM) is also provided, com-
`prising a memory bank having a plurality of memory cells
`arranged in rows and columns, and a decoder for selecting
`one of the memory cells based on a column address and a
`row address. RLml—n is the minimum number of clock cycles
`of the clock signal required from the application of a row
`access command to the output of the data of the selected
`memory cell; Cme is the minimum number of clock cycles
`of the clock signal required from the application of a column
`access command to the output of the data of the selected
`memory cell; and RCL is the number of clock cycles of the
`clock signal from the application of a row access command
`to the application of a column access command with respect
`to the memory bank. A CAS latency, which is the number of
`clock cycles of the clock signal required from the applica-
`tion of the column access command to the output of data, is
`determined to be (RLmin—RCL) when RCL is less than
`(RLml—n—CLml-n), and is determined to be CL when RCL is
`not less than (RLml—n—CLml-n). The quantity (RL —CL,m-n) is
`preferably input from the outside of the SDRAM.
`A synchronous DRAM (SDRAM), operating in synchro-
`nization with a clock signal, is also provided. The SDRAM
`comprises a memory bank having a plurality of memory
`cells arranged in rows and columns, a column decoder for
`selecting the column of the memory bank, a pair of bit lines
`for outputting data from a selected memory cell, and a sense
`amplifier for amplifying the data of the pair of bit lines.
`RLml—n is the minimum number of clock cycles of the clock
`signal required from the application of a row access com-
`mand to the output of the data of the selected memory cell;
`Cme is the minimum number of clock cycles of the clock
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`signal required from the application of a column access
`command to the output of the data of the selected memory
`cell; RCL is the number of clock cycles of the clock signal
`from the application of a row access command to the
`application of a column access command with respect to the
`memory bank; and SAE is the number of clock cycles of the
`clock signal from the application of the row access com-
`mand to the point of time at which the sense amplifier is
`enabled. The CAS latency, which is the number of clock
`cycles of the clock signal required from the application of
`the column access command to the output of data,
`is
`determined by the difference between RCL and SAE.
`The CAS latency is preferably determined to be (RLml—n—
`RCL) when RCL is less than SAE and the difference
`between RCL and SAE is no less than the predetermined
`number of reference clock cycles, and is determined to be
`Cme when RCL is no less than SAE and the difference
`between RCL and SAE is no more than the number of
`
`reference clock cycles.
`A method of controlling CAS latency of an SDRAM,
`synchronized with a clock signal, that includes a memory
`bank having a plurality of memory cells arranged in rows
`and columns and outputs the data of a selected memory cell,
`is also provided. The method comprises inputting a quantity
`(RLmin—CLml—n) from the outside of the SDRAM, where
`RLml—n is the minimum number of clock cycles of the clock
`signal required from the application of a row access com-
`mand to the output of the data of the selected memory cell,
`and Cme is the minimum number of clock cycles of the
`clock signal required from the application of a column
`access command to the output of the data of the selected
`memory cell, comparing RCL with (RLmin—CLml—n), where
`RCL is a number of clock cycles of the clock signal from the
`application of a row access command to the application of
`a column access command with respect to the memory bank,
`determining CAS latency, which is the number of clock
`cycles of the clock signal required from the application of
`the column access command to the output of the data, to be
`(RLmin—RCL) when RCL is less than (RLmin—Clmm), and
`determining the CAS latency to be Cme when RCL is no
`
`less than (RL - —CLmm
`min) ’
`A of controlling CAS latency of an SDRAM which
`includes a bank having a plurality of memory cells arranged
`in rows and columns that outputs the data of a selected
`memory cell in synchronization with the clock signal, is also
`provided. The method comprises sensing RCL, where RCL
`is the number of clock cycles of the clock signal from an
`application of a row access command to an application of a
`column access command, sensing SAE, where SAE is the
`number of clock cycles of the clock signal from the appli-
`cation of the row access command to a point of time at which
`a sense amplifier is enabled, comparing RCL with SAE,
`determining CAS latency, which is the number of clock
`cycles of the clock signal required from the application of
`the column access command to the output of the data, to be
`m
`(RLm. —RCL) when RCL is less than SAE and the difference
`between RCL and SAE is not less than a predetermined
`number of reference clock cycles, and determining the CAS
`latency to be Cme when RCL is not less than SAE or the
`difference between RCL and SAE is less than the predeter-
`mined number of reference clock cycles. RLml—nis the mini-
`mum number of clock cycles of a clock signal required from
`the application of a row access command to the output of the
`data of the selected memory cell; and Cme is the minimum
`number of clock cycles of the clock signal required from the
`application of a column access command to the output of the
`data of the selected memory cell.
`
`6
`According to the SDRAM and the method for controlling
`the CAS latency of the present invention, a posted CAS
`latency operation and a general CAS latency operation can
`be appropriately performed by the SDRAM without a mode
`register set (MRS) command.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The above objects and advantages of the present invention
`will become more apparent by describing in detail preferred
`embodiments thereof with reference to the attached draw-
`
`10
`
`ings in which:
`FIG. 1 is a block diagram schematically showing a
`synchronous DRAM (SDRAM) having a posted column
`access strobe (CAS) latency according to a first preferred
`embodiment of the present invention;
`FIG. 2 is a detailed circuit diagram showing the counter
`of FIG. 1;
`FIG. 3 is a detailed circuit diagram showing the buffer
`controller of FIG. 1;
`FIG. 4 is a timing diagram of the main terminal of the
`SDRAM in a posted CAS command mode according to the
`first preferred embodiment;
`FIG. 5 is a timing diagram of the main terminal of the
`SDRAM in a general CAS command mode according to the
`first preferred embodiment;
`FIG. 6 is a flowchart describing a method of controlling
`CAS latency using the SDRAM according to the first
`preferred embodiment;
`FIG. 7 is a block diagram schematically showing an
`SDRAM having a posted CAS latency according to a second
`preferred embodiment of the present invention;
`FIG. 8 is a detailed circuit diagram showing a first design
`for the counter of FIG. 7;
`FIG. 9 is a detailed circuit diagram showing the first sense
`signal generator of FIG. 8;
`FIG. 10 is a detailed circuit diagram showing the second
`sense signal generator of FIG. 8;
`FIG. 11 is another detailed circuit diagram showing a
`second design for the counter of FIG. 7;
`FIG. 12 is a flowchart describing a method of controlling
`CAS latency using an SDRAM according to a second
`preferred embodiment; and
`FIG. 13 is a view for describing latency from the appli-
`cation of a general row access command or a general column
`access command to the output of data.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`The present invention now will be described more fully
`with reference to the accompanying drawings,
`in which
`preferred embodiments of the invention are shown. The
`same reference numerals in different drawings represent the
`same element.
`
`Structural elements related to the output of data from a
`general synchronous DRAM (SDRAM) and a data output
`operation are as follows. The SDRAM has a plurality of
`memory banks. Each memory bank includes a plurality of
`memory cells arranged in rows and columns. Arow decoder
`for selecting rows and a column decoder for selecting
`columns are included in order to select a specific memory
`cell from among the plurality of memory cells included in
`one memory bank. The data of the memory cells of the row
`selected by the row decoder are then output to a pair of bit
`lines, and the output data is amplified by a sense amplifier.
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`The amplified data of the pair of bit lines corresponding
`to a selected column is then output to a data input and output
`line through a transmission switch. At this time, the trans-
`mission switch is selectively turned on by a decoded column
`address input through a column decoder. The data sent to the
`input and output line is provided to the outside through an
`output buffer. The output operation of the SDRAM is
`preferably controlled in synchronization with the clock
`signal input from the outside.
`First Preferred Embodiment
`FIG. 1 is a block diagram schematically showing an
`SDRAM having posted column access strobe (CAS) latency
`according to a first preferred embodiment of the present
`invention. Elements related to the present
`invention are
`shown. Referring to FIG. 1, the SDRAM according to the
`first preferred embodiment includes a column address input
`port N1, a first shift register 103, a column decoder 109, a
`counter 115, and a memory cell bank 105.
`The memory cell bank 105 includes a plurality of memory
`cells arranged in rows and columns, although only one is
`specifically shown in the specification. The column decoder
`109 operates to select a column of the memory cell bank
`105. The column address input port N1 receives a column
`address CA for selecting the column of the bank 105. The
`first shift register 103 delays the column address CA input
`through the column address input port N1 by a number of
`delay clock cycles Tm and provides the delayed column
`address to the column decoder 109. Here, the number of
`delay clock cycles Tm satisfies Equation 5.
`TDl=(RLmin_CLmin)_RCL
`
`(5)
`
`where RLml—n represents the minimum number of clock
`cycles of a clock signal CLK required from the application
`of a row access command to the output of data from the
`memory cell; Cme represents the minimum number of
`clock cycles of the clock signal CLK required from the
`application of a column access command to the output of
`data from the memory cell; and RCL represents the number
`of clock cycles of the clock signal CLK from the application
`of the row access command to the application of the column
`access command with respect to the same memory bank.
`The first shift register 103 preferably includes a plurality
`of registers 103a, 103b, and 103C, and a multiplexer 103x.
`The registers 103a, 103b, and 1036 are serially coupled to
`each other and sequentially transmit the column address CA
`in response to the clock signal CLK. In operation,
`the
`column address CA is transmitted to the next register every
`clock cycle of the clock signal CLK. The multiplexer 103x
`provides one signal selected in response to a first delay clock
`control signal DCC, output from the counter 115,
`to the
`column decoder 109, using the output signals of the column
`address input port N1 and the registers 103a, 103b, and 1036
`as input signals. The number of registers included in the first
`shift register 103 can be varied, although only three registers
`are shown in the present specification. According to the first
`preferred embodiment, the registers 103a, 103b, and 1036
`are D flip-flops.
`The counter 115 senses the RAS-CAS latency (RCL) and
`provides the first delay clock control signal DCCl, which
`includes information on the difference between RCL and
`
`(RLml—n—CLml-n), to the multiplexer 103x of the first shift
`register 103. The value of (RLmin—CLml—n) can be input from
`the outside of the SDRAM through an MRS command. The
`structure and operation of the counter 115 will be described
`in detail with reference to FIG. 2.
`
`The SDRAM according to the first preferred embodiment
`shown in FIG. 1 further includes a sense amplifier 107, a
`second shift register 111, and a buffer 113.
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`The sense amplifier 107 controls the transmission of the
`data output from the memory cell. In particular, it amplifies
`the data of the memory cell, which is output via a pair of bit
`lines.
`
`The second shift register 111 delays the output data of the
`memory cell by Cme and provides the delayed output data
`to the buffer 113. Since the second shift register 111 has the
`same structure and operation as the first shift register 103, a
`detailed description of the second shift register 111 will be
`omitted. The multiplexer 111x of the second shift register
`111 is preferably controlled by CLmin’
`The buffer 113 buffers an