`Case 2:17-cv—00547-RAJ-RJK Document 1-9 Filed 10/18/17 Page 1 of 18 Page|D# 199
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`EXHIBIT I
`EXHIBIT I
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`Claim 1
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`Case 2:17-cv-00547-RAJ-RJK Document 1-9 Filed 10/18/17 Page 2 of 18 PageID# 200
`Exhibit I - US 7,620,800 SRC Labs – Amazon F1 / Mipsology / Xilinx
`
`A (P) method for data processing in a reconfigurable (A) computing system, the reconfigurable computing system comprising at
`least one (G) reconfigurable processor, the reconfigurable processor comprising a plurality of functional units, said method
`comprising:
`
`(G)
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`(A)
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`(P)
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`Source: http://www.mipsology.com/aws/
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`3
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`Claim 1
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`Case 2:17-cv-00547-RAJ-RJK Document 1-9 Filed 10/18/17 Page 3 of 18 PageID# 201
`Exhibit I - US 7,620,800 SRC Labs – Amazon F1 / Mipsology / Xilinx
`
`A (P) method for data processing in a reconfigurable (A) computing system, the reconfigurable computing system comprising at
`least one (G) reconfigurable processor, the reconfigurable processor comprising a plurality of functional units, said method
`comprising:
`
`(P)
`
`(A)
`
`(G)
`
`Source: https://aws.amazon.com/marketplace/pp/B073SHB43M
`https://www.slideshare.net/AmazonWebServices/deep-dive-on-amazon-ec2-f1-instance-may-2017-aws-online-tech-talks
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`4
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`Claim 1
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`Case 2:17-cv-00547-RAJ-RJK Document 1-9 Filed 10/18/17 Page 4 of 18 PageID# 202
`Exhibit I - US 7,620,800 SRC Labs – Amazon F1 / Mipsology / Xilinx
`
`A method for data processing in a (A) reconfigurable computing system, the reconfigurable computing system comprising at least
`one (G) reconfigurable processor, the reconfigurable processor comprising a plurality of (FU) functional units, said method
`comprising:
`
`(A)
`
`(G)
`
`(FU)
`
`(G)
`
`(FU)
`
`Source: https://www.slideshare.net/AmazonWebServices/deep-dive-on-amazon-ec2-f1-instance-may-2017-aws-online-tech-talks;
`https://www.xilinx.com/support/documentation/product-briefs/mipsology-aws-f1.pdf
`
`5
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`Claim 1
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`Case 2:17-cv-00547-RAJ-RJK Document 1-9 Filed 10/18/17 Page 5 of 18 PageID# 203
`Exhibit I - US 7,620,800 SRC Labs – Amazon F1 / Mipsology / Xilinx
`
`A (P) method for data processing in a reconfigurable (A) computing system, the reconfigurable computing system comprising at
`least one (G) reconfigurable processor, the reconfigurable processor comprising a (FU) plurality of functional units, said method
`comprising:
`
`(P)
`
`(A)
`
`(G)
`
`(FU)
`
`Source: https://www.xilinx.com/support/documentation/product-briefs/mipsology-aws-f1.pdf
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`(A)
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`(G)
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`6
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`Claim 1
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`Case 2:17-cv-00547-RAJ-RJK Document 1-9 Filed 10/18/17 Page 6 of 18 PageID# 204
`Exhibit I - US 7,620,800 SRC Labs – Amazon F1 / Mipsology / Xilinx
`
`A method for data processing in a reconfigurable computing system, the reconfigurable computing system comprising at least one (G)
`reconfigurable processor, the reconfigurable processor comprising a plurality of (FU) functional units, said method comprising:
`
`(G)
`
`(FU)
`
`Source: https://www.xilinx.com/support/documentation/product-briefs/mipsology-aws-f1.pdf
`
`7
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`Claim 1
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`Case 2:17-cv-00547-RAJ-RJK Document 1-9 Filed 10/18/17 Page 7 of 18 PageID# 205
`Exhibit I - US 7,620,800 SRC Labs – Amazon F1 / Mipsology / Xilinx
`
`A method for data processing in a reconfigurable computing system, the reconfigurable computing system comprising at least one (G)
`reconfigurable processor, the reconfigurable processor comprising a plurality of (FU) functional units, said method comprising:
`
`(G)
`
`(FU)
`
`Source: https://www.xilinx.com/support/documentation/product-briefs/mipsology-aws-f1.pdf
`
`8
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`Claim 1
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`Case 2:17-cv-00547-RAJ-RJK Document 1-9 Filed 10/18/17 Page 8 of 18 PageID# 206
`Exhibit I - US 7,620,800 SRC Labs – Amazon F1 / Mipsology / Xilinx
`
`A method for data processing in a reconfigurable computing system, the reconfigurable computing system comprising at least one (G)
`reconfigurable processor, the reconfigurable processor comprising a plurality of (FU) functional units, said method comprising:
`
`(FU)
`
`(G)
`
`(G)
`
`(FU)
`
`Source: https://www.slideshare.net/AmazonWebServices/deep-dive-on-amazon-ec2-f1-instance-may-2017-aws-online-tech-talks
`https://www.xilinx.com/support/documentation/product-briefs/mipsology-aws-f1.pdf;
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`9
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`Claim 1
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`Case 2:17-cv-00547-RAJ-RJK Document 1-9 Filed 10/18/17 Page 9 of 18 PageID# 207
`Exhibit I - US 7,620,800 SRC Labs – Amazon F1 / Mipsology / Xilinx
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`transforming an (R) algorithm into a (Q) data driven calculation that is implemented by said reconfigurable computing system at
`the at least one (G) reconfigurable processor;
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`(R)
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`(G)
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`(Q)
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`Source: http://www.mipsology.com/aws/
`https://www.xilinx.com/support/documentation/product-briefs/mipsology-aws-f1.pdf
`
`10
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`
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`Claim 1
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`Case 2:17-cv-00547-RAJ-RJK Document 1-9 Filed 10/18/17 Page 10 of 18 PageID# 208
`Exhibit I - US 7,620,800 SRC Labs – Amazon F1 / Mipsology / Xilinx
`
`transforming an algorithm into a (Q) data driven calculation that is implemented by said reconfigurable computing system at the at
`least one reconfigurable processor;
`
`(Q)
`
`Source: http://www.mipsology.com/aws/
`https://www.xilinx.com/support/documentation/product-briefs/mipsology-aws-f1.pdf
`
`11
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`Claim 1
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`Case 2:17-cv-00547-RAJ-RJK Document 1-9 Filed 10/18/17 Page 11 of 18 PageID# 209
`Exhibit I - US 7,620,800 SRC Labs – Amazon F1 / Mipsology / Xilinx
`
`transforming an algorithm into a (Q) data driven calculation that is implemented by said reconfigurable computing system at the at
`least one reconfigurable processor;
`
`(Q)
`
`Source: http://www.mipsology.com/aws/
`https://www.xilinx.com/support/documentation/product-briefs/mipsology-aws-f1.pdf
`http://cv-tricks.com/cnn/understand-resnet-alexnet-vgg-inception/
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`12
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`Claim 1
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`Case 2:17-cv-00547-RAJ-RJK Document 1-9 Filed 10/18/17 Page 12 of 18 PageID# 210
`Exhibit I - US 7,620,800 SRC Labs – Amazon F1 / Mipsology / Xilinx
`
`forming at least two of said (FU) functional units at the at least one (G) reconfigurable processor to perform said calculation
`wherein only functional units needed to solve the calculation are formed and wherein each formed functional unit at the at least one
`reconfigurable processor (I) interconnects with each other instantiated functional unit at the at least one reconfigurable processor
`based on reconfigurable routing resources within the at least one reconfigurable processor as established at formation, and wherein
`lines of code of said calculation are formed as clusters of functional units within the at least one reconfigurable processor;
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`(G)
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`(FU)
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`(I)
`
`Source: https://www.slideshare.net/AmazonWebServices/deep-dive-on-amazon-ec2-f1-instance-may-2017-aws-online-tech-talks
`https://www.xilinx.com/support/documentation/white_papers/wp486-deep-learning-int8.pdf
`
`13
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`
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`Claim 1
`
`Case 2:17-cv-00547-RAJ-RJK Document 1-9 Filed 10/18/17 Page 13 of 18 PageID# 211
`Exhibit I - US 7,620,800 SRC Labs – Amazon F1 / Mipsology / Xilinx
`
`instantiating at least two of said (FU) functional units at the at least one (G) reconfigurable processor to perform said calculation
`wherein only functional units needed to solve the calculation are instantiated and wherein each instantiated functional unit at the at
`least one reconfigurable processor interconnects with each other instantiated functional unit at the at least one reconfigurable
`processor based on (RRS) reconfigurable routing resources within the at least one reconfigurable processor as established at
`instantiation, and wherein systolically linked lines of code of said calculation are instantiated as clusters of functional units within the
`at least one reconfigurable processor;
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`(G)
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`(Q)
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`(FU)
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`Source: https://www.xilinx.com/support/documentation/white_papers/wp486-deep-learning-int8.pdf
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`(RRS)
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`14
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`
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`Claim 1
`
`Case 2:17-cv-00547-RAJ-RJK Document 1-9 Filed 10/18/17 Page 14 of 18 PageID# 212
`Exhibit I - US 7,620,800 SRC Labs – Amazon F1 / Mipsology / Xilinx
`
`forming at least two of said (FU) functional units at the at least one reconfigurable processor to perform said calculation wherein
`only functional units needed to solve the calculation are formed and wherein each formed functional unit at the at least one
`reconfigurable processor (I) interconnects with each other instantiated functional unit at the at least one reconfigurable processor
`based on reconfigurable routing resources within the at least one reconfigurable processor as established at formation, and wherein
`lines of code of said calculation are formed as clusters of functional units within the at least one reconfigurable processor;
`
`(FU)
`
`(I)
`
`Source: https://www.xilinx.com/support/documentation/white_papers/wp486-deep-learning-int8.pdf
`https://www.embedded-vision.com/sites/default/files/webinars/May%2024,%202017%20Webinar.pdf
`
`15
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`
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`Claim 1
`
`Case 2:17-cv-00547-RAJ-RJK Document 1-9 Filed 10/18/17 Page 15 of 18 PageID# 213
`Exhibit I - US 7,620,800 SRC Labs – Amazon F1 / Mipsology / Xilinx
`
`forming at least two of said (FU) functional units at the at least one reconfigurable processor to perform said calculation wherein
`only functional units needed to solve the calculation are formed and wherein each formed functional unit at the at least one
`reconfigurable processor (I) interconnects with each other instantiated functional unit at the at least one reconfigurable processor
`based on reconfigurable routing resources within the at least one reconfigurable processor as established at formation, and wherein
`lines of code of said calculation are formed as clusters of functional units within the at least one reconfigurable processor;
`
`Source: https://www.xilinx.com/support/documentation/white_papers/wp486-deep-learning-int8.pdf
`
`(I)
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`(FU)
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`16
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`
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`Claim 1
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`Case 2:17-cv-00547-RAJ-RJK Document 1-9 Filed 10/18/17 Page 16 of 18 PageID# 214
`Exhibit I - US 7,620,800 SRC Labs – Amazon F1 / Mipsology / Xilinx
`
`utilizing a first of said formed functional units to operate upon a (SDD) subsequent data dimension of said (Q) calculation forming
`a (CL1) first computational loop; and
`substantially concurrently utilizing a second of said formed functional units to operate upon a (PDD) previous data dimension of
`said calculation generating a (CL2) second computational loop wherein said implementation of said calculation enables said first
`computational loop and said second computational loop execute concurrently and pass computed data seamlessly between said
`computational loops.
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`(CL1)
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`(CL2)
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`(SDD)
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`(Q)
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`(PDD)
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`Source: https://www.xilinx.com/support/documentation/white_papers/wp486-deep-learning-int8.pdf
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`(CL1) (CL2)
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`17
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`
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`Claim 1
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`Case 2:17-cv-00547-RAJ-RJK Document 1-9 Filed 10/18/17 Page 17 of 18 PageID# 215
`Exhibit I - US 7,620,800 SRC Labs – Amazon F1 / Mipsology / Xilinx
`
`utilizing a first of said formed functional units to operate upon a (SDD) subsequent data dimension of said (Q) calculation forming
`a (CL1) first computational loop; and
`substantially concurrently utilizing a second of said formed functional units to operate upon a (PDD) previous data dimension of
`said calculation generating a (CL2) second computational loop wherein said implementation of said calculation enables said first
`computational loop and said second computational loop execute concurrently and pass computed data seamlessly between said
`computational loops.
`
`(CL1)
`
`(CL2)
`
`(SDD)
`
`(Q)
`
`(PDD)
`
`Source: https://www.xilinx.com/support/documentation/white_papers/wp486-deep-learning-int8.pdf
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`18
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`Claim 17
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`Case 2:17-cv-00547-RAJ-RJK Document 1-9 Filed 10/18/17 Page 18 of 18 PageID# 216
`Exhibit I - US 7,620,800 SRC Labs – Amazon F1 / Mipsology / Xilinx
`
`The method of claim 1 wherein said calculation comprises a (SA) search algorithm for an image search.
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`(SA)
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`Source: https://aws.amazon.com/marketplace/pp/B0719156K8#product-description
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`19
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