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`Case 2:17-cv—00547-RAJ-RJK Document 1-7 Filed 10/18/17 Page 1 of 10 Page|D# 171
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`EXHIBIT G
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`EXHIBIT G
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`Claim 1
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`Case 2:17-cv-00547-RAJ-RJK Document 1-7 Filed 10/18/17 Page 2 of 10 PageID# 172
`Exhibit G - U.S. Patent No. 7,149,867 – Amazon F1
`
`A (RP) reconfigurable processor that instantiates an algorithm as hardware comprising:
`
`(RP)
`
`Source: https://www.xilinx.com/support/documentation/ip_documentation/axi_cdma/v4_1/pg034-axi-cdma.pdf;
`https://www.slideshare.net/AmazonWebServices/deep-dive-on-amazon-ec2-f1-instance-may-2017-aws-online-tech-talks
`
`1
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`
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`Claim 1
`
`Case 2:17-cv-00547-RAJ-RJK Document 1-7 Filed 10/18/17 Page 3 of 10 PageID# 173
`Exhibit G - U.S. Patent No. 7,149,867 – Amazon F1
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`a (FM) first memory having a first characteristic memory bandwidth and/or memory utilization; and
`
`(FM)
`
`Source: https://www.slideshare.net/AmazonWebServices/deep-dive-on-amazon-ec2-f1-instance-may-2017-aws-online-tech-talks
`
`2
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`Claim 1
`
`Case 2:17-cv-00547-RAJ-RJK Document 1-7 Filed 10/18/17 Page 4 of 10 PageID# 174
`Exhibit G - U.S. Patent No. 7,149,867 – Amazon F1
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`a (DP) data prefetch unit (CT) coupled to the (FM) memory,
`
`(DP)
`
`(CT)
`
`(FM)
`
`Source: https://www.slideshare.net/AmazonWebServices/deep-dive-on-amazon-ec2-f1-instance-may-2017-aws-online-tech-talks
`
`3
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`Claim 1
`
`Case 2:17-cv-00547-RAJ-RJK Document 1-7 Filed 10/18/17 Page 5 of 10 PageID# 175
`Exhibit G - U.S. Patent No. 7,149,867 – Amazon F1
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`wherein the (DP) data prefetch unit (CD) retrieves only computational data required by the algorithm from a (SM) second
`memory of second characteristic memory bandwidth and/or memory utilization and places the retrieved computational data in the
`(FM) first memory
`
`(SM)
`
`Host Memory
`
`(DP)
`
`(CD)
`
`(FM)
`
`(CD)
`
`Source: https://www.slideshare.net/AmazonWebServices/deep-dive-on-amazon-ec2-f1-instance-may-2017-aws-online-tech-talks;
`https://github.com/aws/aws-fpga/blob/master/hdk/cl/examples/cl_dram_dma/README.md
`
`4
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`
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`Claim 1
`
`Case 2:17-cv-00547-RAJ-RJK Document 1-7 Filed 10/18/17 Page 6 of 10 PageID# 176
`Exhibit G - U.S. Patent No. 7,149,867 – Amazon F1
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`wherein the (DP) data prefetch unit operates (I) independent of and in parallel with logic blocks using the computational data, and
`
`(I)
`
`(DP)
`
`Source: https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf;
`https://aws.amazon.com/blogs/big-data/scaling-writes-on-amazon-dynamodb-tables-with-global-secondary-indexes
`
`5
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`
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`Claim 1
`
`Case 2:17-cv-00547-RAJ-RJK Document 1-7 Filed 10/18/17 Page 7 of 10 PageID# 177
`Exhibit G - U.S. Patent No. 7,149,867 – Amazon F1
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`wherein at least the (FM) first memory and (DP) data prefetch unit are (CWA) configured to conform to needs of the algorithm,
`and
`
`(FM)
`
`(CWA)
`
`(DP)
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`Source: https://github.com/aws/aws-fpga/blob/master/hdk/docs/AWS_Shell_Interface_Specification.md#ddr4-dram-interface;
`https://github.com/aws/aws-fpga/tree/master/hdk/cl/examples/cl_dram_dma
`
`6
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`Claim 1
`
`Case 2:17-cv-00547-RAJ-RJK Document 1-7 Filed 10/18/17 Page 8 of 10 PageID# 178
`Exhibit G - U.S. Patent No. 7,149,867 – Amazon F1
`
`the (DP) data prefetch unit is configured to (MF) match format and location of data in the (SM) second memory.
`
`(DP)
`
`(MF)
`
`(SM)
`
`Source: https://github.com/aws/aws-fpga/blob/master/hdk/docs/AWS_Shell_Interface_Specification.md#ddr4-dram-interface
`
`7
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`
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`Claim 3
`
`Case 2:17-cv-00547-RAJ-RJK Document 1-7 Filed 10/18/17 Page 9 of 10 PageID# 179
`Exhibit G - U.S. Patent No. 7,149,867 – Amazon F1
`
`The reconfigurable processor of claim 1, wherein the (DP) data prefetch unit receives processed data from (OM) on-processor
`memory and writes the processed data to an (EM) external off-processor memory.
`
`External Off-Processor Memory
`
`(EM)
`
`(DP)
`
`(OM)
`
`Source: https://www.slideshare.net/AmazonWebServices/deep-dive-on-amazon-ec2-f1-instance-may-2017-aws-online-tech-talks
`
`8
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`
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`Claim 4
`
`Case 2:17-cv-00547-RAJ-RJK Document 1-7 Filed 10/18/17 Page 10 of 10 PageID# 180
`Exhibit G - U.S. Patent No. 7,149,867 – Amazon F1
`
`The reconfigurable processor of claim 1, wherein the (DP) data prefetch unit comprises (R) at least one register from the (RP)
`reconfigurable processor.
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`(RP)
`
`(DP)
`
`(R)
`
`Source: https://www.slideshare.net/AmazonWebServices/deep-dive-on-amazon-ec2-f1-instance-may-2017-aws-online-tech-talks;
`https://github.com/aws/aws-fpga/blob/master/hdk/docs/AWS_Shell_Interface_Specification.md#ddr4-dram-interface
`
`9
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`
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