`
`Exhibit F
`
`
`
`Case 6:22-cv-00466-ADA-DTG Document 72-6 Filed 05/09/23 Page 2 of 21
`
`EXHIBIT F
`U.S. Patent No. 8,933,945
`
`Claim 1
`A graphics processing
`circuit, comprising:
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`To the extent that the preamble is limiting, the NXP processors meet this limitation.
`
`The NXP processors perform graphics processing. To illustrate:
`
`i.MX 8QuadMax Applications Processor Reference Manual, § 1.1.1, Document No.: IMX8QMRM, Rev 0,
`9/2021 (downloaded from nxp.com).
`
`The NXP processors include one or more Graphics Processing Unit (GPU) subsystems that include one or
`more GPUs. To illustrate:
`
`Id., § 16.1.1. To illustrate further:
`
`—1—
`
`
`
`Case 6:22-cv-00466-ADA-DTG Document 72-6 Filed 05/09/23 Page 3 of 21
`
`EXHIBIT F
`U.S. Patent No. 8,933,945
`
`Claim 1
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`Id.
`
`—2—
`
`
`
`Case 6:22-cv-00466-ADA-DTG Document 72-6 Filed 05/09/23 Page 4 of 21
`
`EXHIBIT F
`U.S. Patent No. 8,933,945
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`On information and belief, the NXP processors meet this limitation.
`
`For instance, the NXP processors perform “massively parallel data processing” across “multiple compute
`engines,” and “each compute unit has its own arithmetic logic units (ALUs) . . . that can perform
`computations.”
`
`Claim 1
`at least two graphics
`pipelines on a same
`chip operative to
`process data in a
`corresponding set of
`tiles of a repeating tile
`pattern corresponding
`to screen locations,
`
`i.MX Graphic User’s Guide, § 5.1.1, Document No. IMXGRAPHICUG, Rev. 0, 05/2018, available at
`https://www.nxp.com/docs/en/user-guide/i.MX_AA_Graphics_User's_Guide.pdf.
`
`To illustrate further, NXP’s user guides show the Vivante OpenCL data pipeline used in its GPUs and
`NXP’s public demonstrations of its processors depicts the use of multiple graphics pipelines on a chip:
`
`—3—
`
`
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`Case 6:22-cv-00466-ADA-DTG Document 72-6 Filed 05/09/23 Page 5 of 21
`
`EXHIBIT F
`U.S. Patent No. 8,933,945
`
`Claim 1
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`Id., § 5.2.1. To illustrate further, the NXP processors exhibit “massive data parallelism” and “tile
`rasterization”:
`
`—4—
`
`
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`Case 6:22-cv-00466-ADA-DTG Document 72-6 Filed 05/09/23 Page 6 of 21
`
`EXHIBIT F
`U.S. Patent No. 8,933,945
`
`Claim 1
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`R. Malewski, i.MX 8 Graphics Architecture, FTF-DES-N1940, FTF 2016 Technology Forum (May 18,
`2016), https://community.nxp.com/pwmxy87654/attachments/pwmxy87654/ftf2016/88/1/FTF-DES-
`N1940%20i.MX%208%20Graphics%20Architecture.pdf. The presence of multiple shaders, rendering
`engines, textures engines, and pixel engines indicates the presence of multiple pipelines.
`
`On information and belief, the pipelines are operative to process data in a corresponding set of tiles of a
`repeating tile pattern corresponding to screen locations. As shown in the figure above, the NXP processors
`use “tile rasterization,” which is believed to refer to a rasterizer that rasterizes graphics on a per-tile basis
`and with the tiles comprising a repeating tile pattern corresponding to screen locations. Documentation for
`the processor also includes additional references to tiles.
`
`—5—
`
`
`
`Case 6:22-cv-00466-ADA-DTG Document 72-6 Filed 05/09/23 Page 7 of 21
`
`EXHIBIT F
`U.S. Patent No. 8,933,945
`
`Claim 1
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`i.MX 8QuadMax Applications Processor Reference Manual, § 15.7.1.2.4, Document No.: IMX8QMRM,
`Rev 0, 9/2021 (downloaded from nxp.com). To illustrate further:
`
`Id., § 15.7.1.2.5. To illustrate further:
`
`—6—
`
`
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`Case 6:22-cv-00466-ADA-DTG Document 72-6 Filed 05/09/23 Page 8 of 21
`
`EXHIBIT F
`U.S. Patent No. 8,933,945
`
`Claim 1
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`Id., § 15.7.1.2.7.1. To illustrate further, NXP public demonstrations of the related i.MX 6 processors
`suggests those processors also use tile-based rendering:
`
`—7—
`
`
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`Case 6:22-cv-00466-ADA-DTG Document 72-6 Filed 05/09/23 Page 9 of 21
`
`EXHIBIT F
`U.S. Patent No. 8,933,945
`
`Claim 1
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`i.MX 6 Series Portfolio Overview dated August 2013, available at
`https://www.nxp.com/docs/en/supporting-information/DWF13_AMF_CON_T0060.pdf.
`On information and belief, the NXP processors meet this limitation.
`
`The NXP processors exhibit “tile rasterization”:
`
`a respective one of the
`at least two graphics
`pipelines operative to
`process data in a
`dedicated tile; and
`
`R. Malewski, i.MX 8 Graphics Architecture, FTF-DES-N1940, FTF 2016 Technology Forum (May 18,
`2016), https://community.nxp.com/pwmxy87654/attachments/pwmxy87654/ftf2016/88/1/FTF-DES-
`N1940%20i.MX%208%20Graphics%20Architecture.pdf.
`
`—8—
`
`
`
`Case 6:22-cv-00466-ADA-DTG Document 72-6 Filed 05/09/23 Page 10 of 21
`
`EXHIBIT F
`U.S. Patent No. 8,933,945
`
`Claim 1
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`On information and belief, a respective one of the at least two graphics pipelines operative to process data
`in a dedicated tile. As shown in the figure above, the NXP processors use “tile rasterization,” which on
`information and belief refers to a rasterizer that processes data in a dedicated tile. Documentation for the
`processor also includes additional references to tiles. To illustrate further:
`
`i.MX 8QuadMax Applications Processor Reference Manual, § 15.7.1.2.4, Document No.: IMX8QMRM,
`Rev 0, 9/2021 (downloaded from nxp.com). To illustrate further:
`
`—9—
`
`
`
`Case 6:22-cv-00466-ADA-DTG Document 72-6 Filed 05/09/23 Page 11 of 21
`
`EXHIBIT F
`U.S. Patent No. 8,933,945
`
`Claim 1
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`Id., § 15.7.1.2.5. To illustrate further:
`
`Id., § 15.7.1.2.7.1. To illustrate further, NXP public demonstrations of the related i.MX 6 processors
`suggests those processors also use tile-based rendering and on information and believe process data in a
`dedicated tile:
`
`—10—
`
`
`
`Case 6:22-cv-00466-ADA-DTG Document 72-6 Filed 05/09/23 Page 12 of 21
`
`EXHIBIT F
`U.S. Patent No. 8,933,945
`
`Claim 1
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`i.MX 6 Series Portfolio Overview dated August 2013, available at
`https://www.nxp.com/docs/en/supporting-information/DWF13_AMF_CON_T0060.pdf.
`
`—11—
`
`
`
`Case 6:22-cv-00466-ADA-DTG Document 72-6 Filed 05/09/23 Page 13 of 21
`
`EXHIBIT F
`U.S. Patent No. 8,933,945
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`On information and belief, the NXP processors meet this limitation.
`
`Each GPU includes a memory controller. To illustrate:
`
`Claim 1
`a memory controller
`on the chip in
`communication with
`the at least two
`graphics pipelines,
`operative to transfer
`pixel data between
`each of a first pipeline
`and a second pipeline
`and a memory shared
`among the at least two
`graphics pipelines;
`
`i.MX 8QuadMax Applications Processor Reference Manual, Document No.: IMX8QMRM, Rev 0, 9/2021
`(downloaded from nxp.com).
`
`—12—
`
`
`
`Case 6:22-cv-00466-ADA-DTG Document 72-6 Filed 05/09/23 Page 14 of 21
`
`EXHIBIT F
`U.S. Patent No. 8,933,945
`
`Claim 1
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`The memory controller is defined as an “[i]nternal memory management unit that controls the block-to-
`host memory request interface”:
`
`Id., § 16.4.1.1.
`
`On information and belief, the memory controller is operative to transfer pixel data between each of the
`shader cores and a memory shared by at least two shader cores. For example, the display subsystem can
`pre-fetch display data before the display data needs the data. The display subsystem obtains pixel data
`from “GPU buffers.” To illustrate:
`
`—13—
`
`
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`Case 6:22-cv-00466-ADA-DTG Document 72-6 Filed 05/09/23 Page 15 of 21
`
`EXHIBIT F
`U.S. Patent No. 8,933,945
`
`Claim 1
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`Id., § 15.7.1.2.5. On information and belief, the GPU buffers are shared by the shader cores and are
`managed by the memory controller.
`
`As another example, the GPU can in some cases store pixel data in global memory. To illustrate:
`
`—14—
`
`
`
`Case 6:22-cv-00466-ADA-DTG Document 72-6 Filed 05/09/23 Page 16 of 21
`
`EXHIBIT F
`U.S. Patent No. 8,933,945
`
`Claim 1
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`i.MX Graphic User’s Guide, § 5.1.2.3, Document No. IMXGRAPHICUG, Rev. 0, 05/2018, available at
`https://www.nxp.com/docs/en/user-guide/i.MX_AA_Graphics_User’s_Guide.pdf.
`
`On information and belief, the global memory is shared by the shader cores. Indeed, by definition, global
`memory is available to the entire system. NXP’s documents show that each “compute device” has a global
`memory space, meaning this memory space is shared by all shader cores on the GPU. As shown in Fig. 16-
`3, above, the memory controller controls communication with the system bus and the global memory.
`
`—15—
`
`
`
`Case 6:22-cv-00466-ADA-DTG Document 72-6 Filed 05/09/23 Page 17 of 21
`
`EXHIBIT F
`U.S. Patent No. 8,933,945
`
`Claim 1
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`i.MX 8QuadMax applications Processor Reference Manual, Document No.: IMX8QMRM, Rev 0, 9/2021
`(downloaded from nxp.com).
`
`—16—
`
`
`
`Case 6:22-cv-00466-ADA-DTG Document 72-6 Filed 05/09/23 Page 18 of 21
`
`EXHIBIT F
`U.S. Patent No. 8,933,945
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`On information and belief, the NXP processors meet this limitation.
`
`The NXP processors exhibit “tile rasterization”:
`
`Claim 1
`wherein the repeating
`tile pattern includes a
`horizontally and
`vertically repeating
`pattern of square
`regions.
`
`R. Malewski, i.MX 8 Graphics Architecture, FTF-DES-N1940, FTF 2016 Technology Forum (May 18,
`2016), https://community.nxp.com/pwmxy87654/attachments/pwmxy87654/ftf2016/88/1/FTF-DES-
`N1940%20i.MX%208%20Graphics%20Architecture.pdf.
`
`—17—
`
`
`
`Case 6:22-cv-00466-ADA-DTG Document 72-6 Filed 05/09/23 Page 19 of 21
`
`EXHIBIT F
`U.S. Patent No. 8,933,945
`
`Claim 1
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`On information and belief, tile rasterization involves a repeating tile pattern with a horizontally and
`vertically repeating pattern of square regions. To illustrate further:
`
`i.MX 8QuadMax Applications Processor Reference Manual, § 15.7.1.2.4, Document No.: IMX8QMRM,
`Rev 0, 9/2021 (downloaded from nxp.com). To illustrate further:
`
`Id., § 15.7.1.2.5. To illustrate further:
`
`—18—
`
`
`
`Case 6:22-cv-00466-ADA-DTG Document 72-6 Filed 05/09/23 Page 20 of 21
`
`EXHIBIT F
`U.S. Patent No. 8,933,945
`
`Claim 1
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`Id., § 15.7.1.2.7.1. To illustrate further, NXP public demonstrations of the related i.MX 6 processors
`suggests those processors also use tile-based rendering and on information and believe process data in a
`dedicated tile:
`
`—19—
`
`
`
`Case 6:22-cv-00466-ADA-DTG Document 72-6 Filed 05/09/23 Page 21 of 21
`
`EXHIBIT F
`U.S. Patent No. 8,933,945
`
`Claim 1
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`i.MX 6 Series Portfolio Overview dated August 2013, available at
`https://www.nxp.com/docs/en/supporting-information/DWF13_AMF_CON_T0060.pdf.
`
`—20—
`
`