throbber
Case 6:22-cv-00466-ADA-DTG Document 72-5 Filed 05/09/23 Page 1 of 12
`
`Exhibit E
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 72-5 Filed 05/09/23 Page 2 of 12
`
`EXHIBIT E
`U.S. Patent No. 7,804,435
`
`Claim 1
`An apparatus
`comprising:
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`To the extent that the preamble is limiting, the NXP processors meet this limitation.
`
`The NXP processors include a Video Processing Unit:
`
`i.MX 8QuadMax Applications Processor Reference Manual, § 1.1.1, Document No.: IMX8QMRM, Rev 0,
`9/2021 (downloaded from nxp.com). To illustrate further:
`
`Id., § 1.1.2.
`
`—1—
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 72-5 Filed 05/09/23 Page 3 of 12
`
`EXHIBIT E
`U.S. Patent No. 7,804,435
`
`Claim 1
`a power management
`controller
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`The NXP processors include a System Control Unit (SCU) that handles power management.
`
`i.MX 8QuadMax Applications Processor Reference Manual, § 1.2.1.1, Document No.: IMX8QMRM, Rev
`0, 9/2021 (downloaded from nxp.com).
`
`Id., § 8.18.4. To illustrate further:
`
`—2—
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 72-5 Filed 05/09/23 Page 4 of 12
`
`EXHIBIT E
`U.S. Patent No. 7,804,435
`
`Claim 1
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`Id., § 13.1.7.1.
`
`System Controller Firmware API Reference Guide, § 1.1, i.MX8 QXP Die (Version 1.5), March 22, 2019,
`available at https://community.nxp.com/pwmxy87654/attachments/pwmxy87654/imx-
`processors/150415/1/sc_fw_api_qx_b0.pdf.
`
`—3—
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 72-5 Filed 05/09/23 Page 5 of 12
`
`EXHIBIT E
`U.S. Patent No. 7,804,435
`
`Claim 1
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`To illustrate further:
`
`Id., § 1.3.1.
`
`—4—
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 72-5 Filed 05/09/23 Page 6 of 12
`
`EXHIBIT E
`U.S. Patent No. 7,804,435
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`The NXP processors include a Video Processing Unit.
`
`Claim 1
`operatively coupled
`to a video decoder
`that decodes at least
`one encoded digital
`input stream
`
`i.MX 8QuadMax Applications Processor Reference Manual, § 1.1.2, Document No.: IMX8QMRM, Rev 0,
`9/2021 (downloaded from nxp.com).
`
`The Video Processing Unit includes a Multi-Format Video Decoder (MFD) capable of decoding input
`streams using a variety of different encoding formats:
`
`—5—
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 72-5 Filed 05/09/23 Page 7 of 12
`
`EXHIBIT E
`U.S. Patent No. 7,804,435
`
`Claim 1
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`Id., § 16.1.1.2. To illustrate further:
`
`—6—
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 72-5 Filed 05/09/23 Page 8 of 12
`
`EXHIBIT E
`U.S. Patent No. 7,804,435
`
`Claim 1
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`Id. To illustrate further:
`
`—7—
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 72-5 Filed 05/09/23 Page 9 of 12
`
`EXHIBIT E
`U.S. Patent No. 7,804,435
`
`Claim 1
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`Id., § 16.5.1.1. To illustrate further:
`
`Id., § 16.5.2.
`
`—8—
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 72-5 Filed 05/09/23 Page 10 of 12
`
`EXHIBIT E
`U.S. Patent No. 7,804,435
`
`Claim 1
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`The MFD (and the VPU as a whole) is operatively coupled to the SCU:
`
`i.MX 8QuadMax Applications Processor Reference Manual, Document No.: IMX8QMRM, Rev 0, 9/2021
`(downloaded from nxp.com).
`
`—9—
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 72-5 Filed 05/09/23 Page 11 of 12
`
`EXHIBIT E
`U.S. Patent No. 7,804,435
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`The NXP processors meet this limitation.
`
`The i.MX 8QuadMax Applications Processor uses different clocks for decoding video using different
`encoding schemes:
`
`Claim 1
`and in response to a
`determination of
`encoding description
`that describes a
`scheme used to
`encode the input
`stream, varies power
`consumption of at
`least one operational
`portion of the video
`decoder.
`
`i.MX 8QuadMax Applications Processor Reference Manual, § 8.18.4, Document No.: IMX8QMRM, Rev
`0, 9/2021 (downloaded from nxp.com).
`
`The “default” frequency for each of these clocks is 600 MHz, but the VPU subsystem contains different
`clocks based on different encoding schemes, such as “h264” and “mpgd”. On information and belief, the
`frequency of these clocks may be changed during operation or by the user. Indeed, there would be no reason
`to have different clocks for each different type of encoding format unless different frequencies were or
`
`—10—
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 72-5 Filed 05/09/23 Page 12 of 12
`
`EXHIBIT E
`U.S. Patent No. 7,804,435
`
`Claim 1
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`could be used for the different encoding formats, or unless the clock’s variation from its default frequency
`differed based on the type of encoding format.
`
`On information and belief, because clock frequency is inextricably linked to the level of power
`consumption, the VPU employing different clocks for different encoding formats means that the power
`consumption level of at least one operational portion of the video decoder varies in response to determining
`the encoding format.
`
`—11—
`
`

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